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Full text of "National Semiconductor Linear Applications Handbook 1994"

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400043 



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Linear 

Applications 

Handbook 



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LINEAR APPLICATIONS 
HANDBOOK 



3 
Q. 

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The purpose of this handbook is to provide a fully indexed 
and cross-referenced collection of linear integrated circuit 
applications using both monolithic and hybrid circuits from 
National Semiconductor. 

Individual application notes are normally written to explain 
the operation and use of one particular device or to detail 
various methods of accomplishing a given function. The or- 
ganization of this handbook takes advantage of this innate 
coherence by keeping each application note intact, arrang- 
ing them in numerical order, and providing a detailed Sub- 
ject Index. 

Many of the application schematics call out the generic fam- 
ily, identified by either the military temperature range version 
or commercial temperature range version of the device. 
Generally, any device in the generic family will work in the 
circuit. For example, an amplifier indicated as an LM108 
refers to the generic "108" family, and does not imply that 
only military-grade devices will work in the application. Mili- 
tary (or industrial) and prime electrical ("A") grade devices 
need only be considered when their tighter electrical limits 
or wider temperature range warrants their use. 



The temperature range of linear devices is indicated by ei- 
ther the first digit in the part number, or a letter following the 
base part number. 



Grade 

Military 
Extended* 
Industrial* 
Commercial 



Specified Temperature 
Range 

-55°C ^T A ^ +125°C 
-40°C <; T A ^ +125°C 
-25°C ^ T A ^ +85°C 
0°C ^ T A <: +70°C 



Part Number 

LMIXXorLMXXXM 
LMXXXE 

LM2XX or LMXXXI 
LM3XX or LMXXXC 



*Some industrial temperature range devices may be rated 
for the extended (also known as automotive) temperature 
range. Other extended temperature range devices may not 
include a temperature range designation in their part num- 
ber. Check the device datasheet for the specified tempera- 
ture range(s). 

Because commercial parts are less expensive than military 
or industrial, these points should be kept in mind when try- 
ing to determine the most cost-effective approach to a given 
design. 



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2. A critical component is 


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which, (a) are intended for surgical implant into the body, 


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or (b) support or sustain life, and whose failure to per- 


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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time 


without notice, to change said circuitry or specifications. 







HH National 

SlM Semiconductor 



Linear Applications Numerical List 



Application Notes 

Date 

AN-3 Drift Compensation Techniques for Integrated DC Amplifiers 11 /67 

AN-4 Monolithic Op-Amp — The Universal Linear Component 4/68 

AN-13 Application of the LH0002 Current Amplifier 9/68 

AN-20 An Application Guide for Op Amps 8/80 

AN-23 The LM1 05— An Improved Positive Regulator 1/69 

AN-24 A Simplified Test Set for Op Amp Characterization 1 /86 

AN-29 IC Op Amp Beats FETs on Input Current 1 2/69 

AN-30 Log Converters 1 1/69 

AN-31 Op Amp Circuit Collection 2/78 

AN-32 FET Circuit Applications 2/70 

AN-41 Precision IC Comparator Runs from + 5V Logic Supply 1 0/70 

AN-42 IC Provides On-Card Regulation for Logic Circuits 2/71 

AN-46 The Phase Locked Loop IC as a Communications System Building Block 6/71 

AN-48 Applications for a New Ultra-High Speed Buffer 8/71 

AN-49 Pin Diode Drivers /75 

AN-56 1.2V Reference 12/71 

AN-69 LM380 Power Audio Amplifier 12/72 

AN-71 Micropower Circuits Using the LM4250 Programmable Op Amp 7/72 

AN-72 The LM3900— A New Current-Differencing Quad + Input Amplifiers 9/72 

AN-74 LM1 39/LM239/LM339— A Quad of Independently Functioning Comparators 1/73 

AN-79 IC Pre-Amp Challenges Choppers on Drift 2/73 

AN-82 LM125/LM126 Precision Dual-Tracking Regulators 8/80 

AN-87 Comparing the High Speed Comparators 6/73 

AN-88 CMOS Linear Applications 7/73 

AN-97 Versatile Timer Operates from Microseconds to Hours 12/73 

AN-103 LM340 Series Three Terminal Positive Regulators 8/80 

AN-104 Noise Specs Confusing? 5/74 

AN-1 10 Fast IC Power Transistor with Thermal Protection 5/74 

AN-1 16 Use the LM1 58/258/358 Dual, Single Supply Op Amp 8/80 

AN-127 LM143 Monolithic High Voltage Operation Amplifier Applications 4/76 

AN-1 46 FM Remote Speaker System 6/75 

AN-1 54 1 .3V IC Flasher, Oscillator, Trigger or Alarm 12/75 

AN-156 Specifying A/D and D/A Converters 2/76 

AN-161 IC Voltage Reference Has 1 ppm per Degree Drift 6/76 

AN-162 LM2907 Tachometer/Speed Switch Building Block Applications 6/76 

AN-173 IC Zener Eases Reference Design 11 /76 

AN-178 Applications for an Adjustable IC Power Regulator 1 /77 

AN-181 3-Terminal Regulator is Adjustable 3/77 

AN-182 Improving Power Supply Reliability with IC Power Regulators 4/77 

AN-184 References for A/D Converters 7/77 

AN-193 Single Chip Data Acquisition System Simplifies Analog to Digital Conversion 7/77 

AN-200 CMOS A/D Converter Chips Easily Interface to 8080A Microprocessor System 3/78 

AN-202 A Digital Multimeter Using ADD3501 7/80 

AN-210 New Phase-Locked Loops Have Advantage as Frequency to Voltage Converters 

(and more) 4/7g 

AN-211 New Op Amps Ideas 12/78 

AN-222 Super Matched Bipolar Transistor Pair Sets New Standard for Drift and Noise 7/79 



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Linear Applications Numerical List (continued) 

Application Notes _ . 

AN-225 IC Temperature Sensor Provides Thermocouple Cold-Junction Compensation 4/79 

AN-227 Applications of Wideband Buffers 10/79 

AN-233 The A/D Easily Allows Many Unusual Applications 1 /80 

AN-236 An Introduction to Sampling Theorem 1 /80 

AN-237 Convolution: Digital Signal Processing 1 /80 

AN-240 Wide-Range Current-to-Frequency Converters 5/80 

AN-241 Working with High Impedance Op Amps 2/80 

AN-242 Applying a New Precision Op Amp 4/80 

AN-245 Application of the ADC-1 210 CMOS A/D Converter — 

AN-247 Using the ADC0808/ADC0809 8-Bit juP Compatible A/D Converters with 8-Channel 

Analog Multiplexer 9/80 

AN-253 LH0024 and LH0032 High Speed Op Amp Applications /80 

AN-255 Power Spectrum Estimation 11 /80 

AN-256 Circuitry for Inexpensive Relative Humidity Measurement 8/81 

AN-258 Data Acquisition Using the ADC081 6 and ADC081 7 8-Bit A/D Converter with On-Chip 

1 6 Channel Multiplexer 1/81 

AN-260 A 20-Bit (1 ppm) Linear Slope-Integrating A/D Converter 1/81 

AN-261 Low Distortion Wideband Power Op Amp 7/81 

AN-262 Applying Dual and Quad FET Op Amps 5/81 

AN-263 Sine Wave Generation Techniques 3/81 

AN-265 An Electronic Watt-Watt Hour Meter 2/84 

AN-266 Circuit Applications of Sample-Hold Amplifiers 1/81 

AN-269 Circuit Applications of Multiplying CMOS A/D Converters 9/81 

AN-271 Applying the New CMOS MICRO-DAC 9/81 

AN-272 Op Amp Booster Designs 9/81 

AN-274 CMOS A/D Converter Interfaces Easily with Many Microprocessors 7/81 

AN-275 CMOS D/A Converters Match Most Microprocessors 7/81 

AN-276 A New Low-Cost Sampled Data 1 0-Bit CMOS A/D Converter 7/81 

AN-277 The New MICRO-DAC Product Line for Microprocessor Systems 7/81 

AN-278 Designing with a New Super Fast Dual Norton Amplifier 9/81 

AN-280 A/D Converters Easily Interface with 70 Series Microprocessors 11/81 

AN-281 Data Acquisition Using INS8048 1 1/81 

AN-284 Single-Supply Applications of CMOS MICRO-DACs 9/81 

AN-285 An Acoustic Transformer Powered Super-High Isolation Amplifier 10/81 

AN-286 Applications of the LM392 Comparator Op Amp IC 9/81 

AN-288 System-Oriented DC-DC Conversion Techniques 4/82 

AN-292 Applications of the LM3524 Pulse-Width Modulator 8/82 

AN-293 Control Applications of CMOS DACs 3/82 

AN-294 Special Sample and Hold Techniques 4/82 

AN-295 A High Performance Industrial Weighing System 3/82 

AN-298 Isolation Techniques for Signal Conditioning 5/82 

AN-299 Audio Applications of Linear Integrated Circuits 4/82 

AN-300 Simple Circuit Detects Loss of 4 mA-20 mA Signal 5/82 

AN-301 Signal Conditioning for Sophisticated Transducers 1/82 

AN-307 Introducing the MF 10: A Versatile Monolithic Active Filter Building Block 8/82 

AN-31 1 Theory and Applications of Logarithmic Amplifiers 7/82 

AN-336 Understanding Integrated Circuit Package Power Capabilities 3/83 

AN-343 LH1605 Switching Regulator 9/83 

AN-344 LF1 3006/LF1 3007 Precision Digital Gain Set Applications 3/84 

AN-346 High-Performance Audio Applications of the LM833 8/85 

AN-384 Audio Noise Reduction and Masking 3/85 

AN-386 A Non-Complementary Audio Noise Reduction System 3/85 

AN-390 DNR® Applications of the LM1894 3/85 

AN-391 The LM1 823: A High Quality TV Video I.F. Amplifier and Synchronous Detector 

for Cable Receivers 3/85 



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Linear Applications Numerical List (continued) 

Application Notes 

Date 

AN-402 LM2889 R.F. Modulator 6/85 

AN-435 LMC835 Digital Controlled Graphic Equalizer 3/86 

AN-446 A 1 50W IC Op Amp Simplifies Design of Power Circuits 4/86 

AN-447 Protection Schemes for BIFET Amplifiers and Switches 4/86 

AN-460 LM34/LM35 Precision Monolithic Temperature Sensors 6/86 

AN-656 Understanding the Operation of CRT Monitor 11/89 

AN-693 LM628 Programming Guide 4/90 

AN-694 A DMOS 3A, 55V H-Bridge: The LMD18200 6/90 

AN-706 LM628/LM629 User Guide 8/90 

AN-71 1 LM78S40 Switching Voltage Regulator Applications 1 1 /90 

AN-715 LM385 Feedback Provides Regulator Isolation 11/90 

AN-769 Dynamic Specifications for Sampling A/D Converters 5/91 

AN-775 Specifications and Architectures of Sample-and-Hold Amplifiers 7/92 

AN-776 20W Simple Switcher Forward Converter 6/91 

AN-777 LM2577 Three Output, Isolated Flyback Regulator 6/91 

AN-779 A Basic Introduction to Filters— Active, Passive, and Switched-Capacitor 4/91 

AN-813 Topics on Using the LM6181— A New Current Feedback Amplifier 3/92 

AN-828 Increasing the High Speed Torque of Bipolar Stepper Motors 5/93 

AN-840 Development of an Extensive SPICE Macromodel for "Current Feedback" Amplifiers ... 11/93 

AN-856 A SPICE Compatible Macromodel for CMOS Operational Amplifiers 11/93 

AN-861 Guide to CRT Design 1/93 

AN-867 Designing the Video Section of 1 600 x 1 280-Pixel CRTs 1 2/93 

AN-898 Audio Amplifiers Utilizing: SPIKEtm Protection 1 0/93 

AN-906 Interfacing the LM1 2454/8 Data Acquisition System Chips to Microprocessors 

and Microcontrollers 1 0/93 

AB-7 Multivibrator Timer CAD 3/86 

AB-10 Fluid Level Control System 11/83 

AB-1 1 High-Efficiency Regulator Has Low Drop-Out Voltage 9/83 

AB-12 Wide Adjustable Range PNP Voltage Regulator 2/84 

AB-24 Bench Testing LM3900 and LM359 Input Parameters 1 2/85 

AB-25 Dithering Display Expands Bar Graph's Resolution 8/81 

AB-30 RS-232 Line Driver Power Supply 6/86 

LB-1 Instrumentation Amplifier 3/69 

LB-2 Feedforward Compensation Speeds Op Amps 3/69 

LB-4 Fast Compensation Extends Power Bandwidth 4/69 

LB-5 High Q Notch Filter 3/69 

LB-6 Fast Voltage Comparators with Low Input Current 5/69 

LB-8 Precision AC/DC Converters 8/69 

LB-9 Universal Balancing Techniques 8/69 

LB-1 1 The LM1 10— An Improved IC Voltage Follower 3/70 

LB- 12 An IC Voltage Comparator for High Impedance Circuitry 1 /70 

LB-14 Speed Up the LM108 with Feedforward Compensation 1 1/70 

LB-15 High Stability Regulators 1/71 

LB-16 Easily Tuned Sine Wave Oscillators 3/71 

LB-17 LM1 18 Op Amp Slews 70V/ju,s 9/71 

LB-18 + 5V to - 1 5V Converter 7/72 

LB-19 Predicting Op Amp Slew Rate Limited Response 8/72 

LB-20 A Fully Differential Input Voltage Amplifier 1 2/72 

LB-21 Instrumentational Amplifier 6/73 

LB-22 Low Drift Amplifier 3/86 

LB-23 Precise Tri-Wave Generation 6/73 

LB-24 Versatile IC Pre-Amp Makes Thermocouple Amplifier with Cold Junction 

Compensation 6/73 

LB-25 True rms Detector 6/73 

LB-26 Specifying Selected Op Amps and Comparators 1 0/73 

LB-27 Micropower Thermometer 1 /74 



Revision 
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Linear Applications Numerical List (continued) 

Application Notes D t 

LB-28 General Purpose Power Supply 6/74 

LB-32 Microvolt Comparator 6/76 

LB-34 A Micropower Voltage Reference 6/76 

LB-35 Adjustable 3-Terminal Regulator for Low-Cost Battery Charging Systems 8/76 

LB-38 Wide Range Timer 2/77 

LB-39 Circuit Techniques for Avoiding Oscillations in Comparator Applications 1 /78 

LB-41 Precision Reference Uses Only Ten Microamperes 6/78 

LB-42 Get Fast Stable Response from Improved Unity-Gain Followers 8/78 

LB-44 Get More Power Out of Dual or Quad Op Amps 4/79 

LB-45 Frequency-to-Voltage Converter Uses Sample-and-Hold to Improve Response 

and Ripple 4/79 

LB-46 A New Production Technique for Trimming Voltage Regulators 7/79 

LB-47 High Voltage Adjustable Power Supplies 3/80 

LB-48 Simple Voltmeter Monitors TTL Supplies 2/80 

LB-49 Programmable Power Regulators Help Check Out Computer System Operating 

Margins 1 /85 

LB-51 Add Kelvin Sensing and Parallel Capability to 3-Terminal Regulators 3/81 

LB-52 A Low Noise Precision Op Amp 12/80 

LB-53 /xP Interface for a Free Running A/D Allows Asynchronous Reads 7/81 

Appendix A The Monolithic Operational Amplifier: A Tutorial Study 1 2/84 

Appendix C V/F Converter IC's Handle Frequency-to-Voltage Needs 8/80 

Appendix D Versatile Monolithic V/F's Can Compute as well as Convert with High Accuracy — 8/80 

Appendix H Standard Resistance Values 6/86 



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gH National 

MM Semiconductor 



Semiconductor 
Device/ Application Literature Cross-Reference 

Device Number Application Literature 

ADCXXXX AN-156 

ADC80 AN-360 

ADC0801 AN-233, AN-271, AN-274, AN-280, AN-281, AN-294, LB-53 

ADC0802 AN-233, AN-274, AN-280, AN-281 , LB-53 

ADC0803 AN-233, AN-274, AN-280, AN-281 , LB-53 

ADC08031 AN-460 

ADC0804 AN-233, AN-274, AN-276, AN-280, AN-281, AN-301, AN-460, LB-53 

ADC0805 AN-233, AN-274, AN-280, AN-281 , LB-53 

ADC0808 AN-247, AN-280, AN-281 

ADC0809 AN-247, AN-280 

ADC0816 AN-193, AN-247, AN-258, AN-280 

ADC0817 AN-247, AN-258, AN-280 

ADC0820 AN-237 

ADC0831 AN-280, AN-281 

ADC0832 AN-280, AN-281 

ADC0833 AN-280, AN-281 

ADC0834 AN-280, AN-281 

ADC0838 AN-280, AN-281 

ADC1001 AN-276, AN-280, AN-281 

ADC1005 AN-280 

ADC10461 AN-769 

ADC10462 AN-769 

ADC10464 AN-769 

ADC10662 AN-769 

ADC10664 AN-769 

ADC1210 AN-245 

ADC12441 AN-769 

ADC12451 AN-769 

ADC3501 AN-200, AN-202 

ADC351 1 AN-200 

ADC3701 AN-200 

ADC371 1 AN-200 

CD4016 AB-10 

DACXXXX AN-156 

DAC0800 AN-693 

DAC0830 AN-284 

DAC0831 AN-271, AN-284 

DAC0832 AN-271 , AN-284 

DAC1000 AN-271, AN-275, AN-277, AN-284 

DAC1001 AN-271, AN-275, AN-277, AN-284 

DAC1002 AN-271 , AN-275, AN-277, AN-284 

DAC1006 AN-271, AN-275, AN-277, AN-284 

DAC1007 AN-271, AN-275, AN-277, AN-284 



Device/Application Literature Cross-Reference (continued) 

Device Number Application Literature 

DAC1008 AN-271, AN-275, AN-277, AN-284 

DAC1020 AN-263, AN-269, AN-2293, AN-294, AN-299 

DAC1021 AN-269 

DAC1022 AN-269 

DAC1208 AN-271, AN-284 

DAC1209 AN-271, AN-284 

DAC1210 AN-271, AN-284 

DAC1218 AN-293 

DAC1219 AN-693 

DAC1220 AN-253, AN-269 

DAC1221 AN-269 

DAC1222 AN-269 

DAC1230 AN-284 

DAC1 231 AN-271 , AN-284 

DAC1232 AN-271, AN-284 

DAC1280 AN-261, AN-263 

DH0034 AN-253 

DH0035 AN-49 

INS8070 AN-260 

LF1 1 1 LB-39 

LF155 AN-263, AN-447 

LF198 AN-245, AN-294 

LF31 1 AN-301 

LF347 AN-256, AN-262, AN-263, AN-265, AN-266, AN-301 , AN-344, AN-447, LB-44 

LF351 AN-242, AN-263, AN-266, AN-271 , AN-275, AN-293, AN-447, Appendix C 

LF351A AN-240 

LF351B Appendix D 

LF353 AN-256, AN-258, AN-262, AN-263, AN-266, AN-271, AN-285, AN-293, AN-447, LB-44, Appendix D 

LF356 AN-253, AN-258, AN-260, AN-263, AN-266, AN-271, AN-272, 

AN-275, AN-293, AN-294, AN-295, AN-301 , AN-447, AN-693 

LF357 AN-263, AN-447, LB-42 

LF398 AN-247, AN-258, AN-266, AN-294, AN-298, LB-45 

LF41 1 AN-294, AN-301 , AN-344, AN-447 

LF412 AN-272, AN-299, AN-301, AN-344, AN-447 

LF441 AN-301, AN-447 

LF13006 AN-344 

LF13007 AN-344 

LF1 3331 AN-294, AN-447 

LH0002 AN-13, AN-227, AN-263, AN-272, AN-301 

LH0024 AN-253 

LH0032 AN-242, AN-253 

LH0033 AN-48, AN-227, AN-253 

LH0063 AN-227 

LH0070 AN-301 

LH0071 AN-245 

LH0094 AN-301 

LH0101 AN-261 

LH1605 AN-343 

LH2424 AN-867 

LM10 AN-21 1, AN-247, AN-258, AN-271, AN-288, AN-299, AN-300, AN-460, AN-693 

LM 1 1 AN-241 , AN-242, AN-260, AN-266, AN-271 



Device/Application Literature Cross-Reference (continued) 

Device Number Application Literature 

LM12 AN-446, AN-693, AN-706 

LM101 AN-4, AN-13, AN-20, AN-24, LB-42, Appendix A 

LM101 A AN-29, AN-30, AN-31, AN-79, AN-241 AN-711, LB-1, LB-2, LB-4, LB-8, LB-14, LB-16, LB-19, LB-28 

LM102 AN-4, AN-13, AN-30, LB-1, LB-5, LB-6, LB-1 1 

LM103 AN-1 10, LB-41 

LM1 05 AN-23, AN-110, LB-3 

LM106 AN-41, LB-6, LB-12 

LM107 AN-20, AN-31, LB-1, LB-12, LB-19, Appendix A 

LM108 AN-29, AN-30, AN-31, AN-79, AN-21 1, AN-241, LB-14, LB-15, LB-21 

LM108A AN-260, LB-15, LB-19 

LM109 AN-42, LB-15 

LM1 09A LB-1 5 

LM1 10 LB-1 1 , LB-42 

LM1 1 1 AN-41, AN-103, LB-12, LB-16, LB-32, LB-39 

LM112 LB-19 

LM113 AN-56, AN-110, LB-21, LB-24, LB-28, LB-37 

LM117 AN-178, AN-181, AN-182, LB-46, LB-47 

LM117HV LB-46, LB-47 

LM118 LB-17, LB-19, LB-21, LB-23, Appendix A 

LM1 1 9 LB-23 

LM120 AN-182 

LM121 AN-79, AN-104, AN-184, AN-260, LB-22 

LM121 A LB-32 

LM122 AN-97, LB-38 

LM125 AN-82 

LM126 AN-82 

LM129 AN-1 73, AN-178, AN-262, AN-266 

LM131 AN-210, AN-460, Appendix D 

LM131A AN-210 

LM134 LB-41, AN-460 

LM135 AN-225, AN-262, AN-292, AN-298, AN-460 

LM1 37 LB-46 

LM137HV LB-46 

LM138 LB-46 

LM139 AN-74 

LM143 AN-127, AN-271 

LM148 AN-260 

LM150 LB-46 

LM158 AN-1 16 

LM160 AN-87 

LM161 AN-87, AN-266 

LM163 AN-295 

LM194 AN-222, LB-21 

LM195 AN-110 

LM199 AN-161, AN-260 

LM199A AN-161 

LM21 1 LB-39 

LM231 AN-210 

LM231A AN-210 

LM235 AN-225 

LM239 AN . 74 



Device/Application Literature Cross-Reference (continued) 

Device Number Application Literature 

LM258 AN-1 16 

LM260 AN-87 

LM261 AN-87 

LM34 AN-460 

LM35 AN-460 

LM301A AN-178, AN-181, AN-222 

LM308 AN-88, AN-184, AN-272, LB-22, LB-28, Appendix D 

LM308A AN-225, LB-24 

LM309 AN-178, AN-182 

LM31 1 AN-41 , AN-1 03, AN-260, AN-263, AN-288, AN-294, AN-295, AN-307, LB-12, LB-16, LB-18, LB-39 

LM313 AN-263 

LM31 6 AN-258 

LM317 AN-178, LB-35, LB-46 

LM31 7H LB-47 

LM318 AN-299, LB-21 

LM319 AN-828, AN-271, AN-293 

LM320 AN-288 

LM321 LB-24 

LM324 AN-88, AN-258, AN-274, AN-284, AN-301, LB-44, AB-25, Appendix C 

LM329 AN-256, AN-263, AN-284, AN-295, AN-301 

LM329B AN-225 

LM330 AN-301 

LM331 AN-21 0, AN-240, AN-265, AN-278, AN-285, AN-31 1 , LB-45, Appendix C, Appendix D 

LM331A AN-210, Appendix C 

LM334 AN-242, AN-256, AN-284 

LM335 AN-225, AN-263, AN-295 

LM336 AN-202, AN-247, AN-258 

LM337 LB-46 

LM338 LB-49, LB-51 

LM339 AN-74, AN-245, AN-274 

LM340 AN-103, AN-182 

LM340L AN-256 

LM342 AN-288 

LM346 AN-202, LB-54 

LM348 AN-202, LB-42 

LM349 LB-42 

LM358 AN-1 1 6, AN-247, AN-271 , AN-274, AN-284, AN-298, Appendix C 

LM358A Appendix D 

LM359 AN-278, AB-24 

LM360 AN-87 

LM361 AN-87, AN-294 

LM363 AN-271 

LM380 AN-69, AN-146 

LM382 AN-147 

LM385 AN-242, AN-256, AN-301 , AN-344, AN-460, AN-693, AN-777 

LM386 LB-54 

LM391 AN-272 

LM392 AN-274, AN-286 

l_ M 393 AN-271, AN-274, AN-293, AN-694 

LM394 AN-262, AN-263, AN-271 , AN-293, AN-299, AN-31 1, LB-52 

LM395 AN-178, AN-181, AN-262, AN-263, AN-266, AN-301 , AN-460, LB-28 



Device/ Application Literature Cross-Reference (continued) 

Device Number Application Literature 

LM399 A N-1 84 

LM555 AN-694, AB-7 

LM556 AB-7 

LM 565 AN-46, AN-146 

LM566 AN-146 

LM6( > 4 AN-460 

LM628 AN-693, AN-706 

LM629 AN-693, AN-694, AN-706 

LM709 AN-24, AN-30 

LM710 AN-41, LB-12 

LM725 LB-22 

LM741 AN-79, LB-19, LB-22 

LM832 AN-386, AN-390 

LM833 AN-346 

LM1036 AN-390 

LM1202 AN-867 

LM1203 AN-861 

LM1458 AN-116 

LM1524 AN-272, AN-288, AN-292, AN-293 

LM1 558 AN-1 16 

LM1578A AB-30 

LM1823 AN-391 

LM1830 AB-10 

LM1865 AN-390 

LM1886 AN-402 

LM1889 AN-402 

LM1894 AN-384, AN-386, AN-390 

LM2419 AN-861 

LM2577 AN-776, AN-777 

LM2889 AN-391, AN-402 

LM2907 AN-162 

LM2917 AN-162 

LM2931 AB-12 

LM2931CT AB-11 

LM3045 AN-286 

LM3046 AN-146, AN-299 

LM3089 AN-147 

LM3524 AN-272, AN-288, AN-292, AN-293 

LM3525A AN-694 

LM3578A AB-30 

LM3876 AN-898 

LM3900 AN-72, AN-263, AN-274, AN-278, LB-20, AB-24 

LM3909 AN-1 54 

LM3911 LB-27, AN-460 

LM391 4 AN-460, LB-48, AB-25 

LM3915 AN-386 

LM3999 AN-161 

LM4250 AN-88, LB-34 

LM6181 AN-813, AN-840 

LM7800 AN-178 

LM12454/8 AN-906 

LM18293 AN-706 



XI 



Device/ Application Literature Cross-Reference (continued) 

Device Number Application Literature 

LM78L12 AN-146 

LM78S40 AN-711 

LMC555 AN-460, AN-828 

LMC660 AN-856 

LMC835 AN ' 435 

LMC6044 AN " 856 

LMC6062 AN-856 

LMC6082 AN-856 

LMC6484 AN-856 

LMD18200 AN-694, AN-828 

LMF40 AN-779 

LMF60 AN-779 

LMF90 AN-779 

LMF100 AN-779 

LMF120 AN-779 

LMF380 AN-779 

LMF390 AN-779 

LP324 AN-284 

LP395 AN-460 

LPC660 AN-856 

MF4 AN-779 

MF5 AN-779 

MF6 AN-779 

MF8 AN-779 

MF10 AN-307, AN-779 

MM2716 LB " 54 

MM54104 AN-252, AN-287, LB-54 

MM571 10 AN-382 

MM74C00 AN-88 

MM74C02 AN-88 

MM74C04 AN-88 

MM74C948 AN-193 

MM74HC86 AN-861 , AN-867 

MM74LS138 LB " 54 

MM53200 AN-290 

2N4339 AN-32 



23 National 






iii Semiconductor 








Subject Index 


A/D (See Analog-to-Digital) 




Current Amplifier: AN-4, AN-13, AN-227 


ABSOLUTE VALUE AMPLIFIER: AN-31 




Current Feedback Amplifier: AN-813, AN-840 


AC AMPLIFIER: AN-31, AN-48, AN-72 




Difference: AN-20, AN-29, AN-31, AN-72 


AC TO DC CONVERTER: AN-31, LB-8 




Differential Input: LB-20 


ACTIVE FILTER (See Filter) 




Differentiator: AN-20, AN-31, AN-72 


AGC 




Digitally Controlled: AN-269 


DC: AN-72 




Drift Testing: AN-79 


Methods: AN-72 




Dual Op Amp with Single Supply: AN-1 16 


Television Signal: AN-391 




FET Input: AN-4, AN-29, AN-32, AN-227, 


ALARM 




AN-253, AN-447 


Inexpensive IC: AN-154 




Fiber Optic Link: AN-253 


AM-FM: 




Follower (See Voltage Follower) 


Demodulators and Detectors: AN-46 




Frequency Compensation: AN-79 


AMMETER 




High Current Buffer: AN-4, AN-13, AN-29, 


AN-71, AN-242 




AN-31, AN-48, AN-227 


AMPLIFIERS: 




High Input Impedance: AN-29, AN-31, AN-32, AN-48, 
AN-72, AN-227, AN-241, AN-253, LB-1 


150 Watt Op Amp, LM12: AN-446 






AC: AN-31, AN-48, AN-72 




High Resolution (Video): AN-867, AN-813, AN-861 
High Speed: AN-227, AN-253, LB-42, AN-813, AN-840, 


Absolute Value: AN-31 




AN-861, AN-867 


AGC: AN-391 




High Speed Peak Detector: AN-227 


Anti-Log Generator: AN-30, AN-31 




High Speed Sample and Hold: AN-253 


Audio: AN-32, AN-69, AN-72, AN-898 




High Voltage: AN-72, AN- 127 


Battery Powered: AN-71, AN-211 




Improved DC Characteristics: AN-79 


Bias Current: AN-242 




Input Guarding: AN-29, AN-447 


Bridge: AN-29, AN-31 




Instrumentation: AN-29, AN-31, AN-71, AN-79, 


Bridged: AN-69 




AN-1 27, AN-222, AN-242, LB-1, LB-21 


Buffered: AN-253 




Instrumentation Shield/Line Driver: AN-48 


Buffered High Current Output: AN-4, AN-13, 


Integrator: AN-20, AN-29, AN-31, AN-72, AN-88 


AN-29, AN-31, AN-48, AN-253, AN-261 


AN-272 


Integrator, JFET AC Coupled: AN-32 


Cascode, FET: AN-32 




Inverting: AN-20, AN-31, AN-71, AN-72, LB-17 


Cascode, RF: AN-32 




Level Shifting: AN-4, AN-13, AN-32, AN-41, AN-48 


Circuit Description LH0002: AN-4, AN-13, 


AN-227 


Line Receiver: AN-72 


Circuit Description LH0024: AN-253 




Logarithmic Converter: AN-29, AN-30, AN-31 


Circuit Description LH0032: AN-253 




Low Drift: AN-79, AN-222, LB-22, LB-24 


Circuit Description LH0033: AN-48, AN-227 


Low Frequency: AN-74 


Circuit Description LH0063: AN-227 




Low Noise: AN-222, AN-346 


Circuit Description LM108/LM208/LM308: AN-29 


Low Offset: AN-242 


Circuit Description LM118/LM218/LM318 


LB-17 


Meter: AN-71 


Circuit Description LM3900: AN-72 




Micropower: AN-71 


Circuit Description LM4250 Micropower 




Microphone: AN-346 


Programmable Amp: AN-71 




Nano-Watt: AN-71 


Clamping: AN-31, LB-8 




Noise: AN-241 


CMOS as Linear Amp: AN-88 






Compensation: AN-242, AN-253, AN-813, 


AN-861 




CRT (Cathode Ray Tube): AN-861 







0) 



3 
Q. 
<D 
X 



Subject Index (Continued) 




Noise Specifications: AN-104, LB-26 


Current Source: AN-202 


Non-Inverting Amplifier: AN-20, AN-31, AN-72 


Dielectric Absorption: AN-260 


Non-Linear: AN-4, AN-31 


Differential Analog Input: AN-233 


Norton: AN-72, AN-278 


Dual Slope Converter: AN-260 


Operational: AN-4, AN-20, AN-29, AN-31, 


Errors: AN-1 56 


AN-63, AN-211, AN-241, AN-446, Appendix A 


FET Switched Multiplexer: AN-260 


Output Resistance: AN-29 


Free-Running Interface: LB-53 


Paralleling: LB-44 


Grounding Considerations: AN-274 


Photocell: AN-20 


Integrating Converters: AN-260 


Photodiode: AN-20, AN-29, AN-31, LB-12 


Integrating 10-Bit: AN-262 


Photoresistor Bridge: AN-29 


Integrator Comparator: AN-260 


Piezoelectric Transducer: AN-29, AN-31 


Linearity Error Specifications: AN-1 56 


Power: AN-69, AN-72, AN-110, AN-125, AN-127, 


Logarithmic: AN-274 


AN-446, AN-898, LB-44 

(See also Buffer, High Current) 


Microprocessor Compatible: AN-284 


Preamp: AN-79, AN-346, LB-24 


Microprocessor Controlled Offset Adjust: AN-274 


Pulse: AN-13 


Microprocessor Interfacing: AN-274 


Rejection, Power Supply: AN-29 


Offset Adjust: AN-274 


Reset Stabilized: AN-20 


Ramp Generator: AN-260 




Ratiometric Conversion: AN-247 


RF (See RF Amplifier) 






References: AN-1 84 


RGB: AN-861 






Resolution: AN-1 56, AN-276 


Sample and Hold: AN-4, AN-29, AN-31, AN-32, AN-48, 




AN-72, AN-245, LB-1 1 


Sampled Data Comparator: AN-276 


Single Supply: AN-72, AN-21 1 


Sampled Data Comparator Input: AN-274 


Solar Cell: AN-4 


Single Slope Converter: AN-260 


Specifying Selected Parameters: LB-26 


Single Supply: AN-245, AN-284 


Squaring: AN-72 


Span Adjustment: AN-233, AN-274 


Strain Gauge: AN-222 


Specifications: AN-1 56, AN-769 


Summing: AN-20, AN-31 


Successive Approximation Register: AN-1 93 


Temperature Probe: AN-31 , AN-56 


Testing: AN-1 79, AN-233 


Transmission Line Driver: AN-4, AN-1 3 


Voltage Comparator: AN-276 


Tutorial Study of Op Amps: Appendix A 


Voltage Mode: AN-284 


Variable Gain: AN-31, AN-32, AN-299, AN-346, 


Z-80 Interface: AN-247 


LB-1 (See also AGC) 


10-Bit Data Formats: AN-277 


Very High Current Booster with High 


12-Bit Serial Output: AN-245 


Compliance: AN-127 


15-Bit Single Slope Integrating Converter: AN-295 


Video: AN-813, AN-861 


6800 ju,P Interface: AN-247 


Wide Band Buffer: AN-227 


8080 ixP Interface: AN-247 


1A Class AB Current Booster: AN-127 


ANALOG-TO-DIGITAL CONVERTER 


100 mA Current Booster: AN-127 




90 Watt Audio: AN-127 


As a Divider: AN-233 


ANALOG COMMUTATOR (See Analog Switch) 


As a Voltage Comparator: AN-233 


ANALOG DIVIDER: AN-4, AN-30, AN-31 


High Speed: AN-237 


ANALOG MULTIPLIER: AN-4, AN-20, AN-30, AN-31 


AND GATE: AN-72, AN-74 


ANALOG SWITCH: AN-32 


ANTI-LOG GENERATOR: AN-30, AN-31 


ANALOG-TO-DIGITAL: AN-1 56, AN-245, AN-360 


ARC PROTECTION (CRT): AN-861 


Absolute Conversion: AN-247 


ATTENUATION 


Accuracy: AN-1 56, AN-276 


Digital: AN-284 (See also AGC) 


Analog Input Consideration: AN-247 


AUDIO AMPLIFIERS: AN-32, AN-69, AN-72, 
AN-346, AN-898 


Auto Gain Ranging Converter: AN-245 


Bridge Amplifier: AN-69 


Binary Codes: AN-1 56 


Intercom: AN-69 


Converters: AN-87, AN-1 56, AN-1 62, AN-1 93, AN-233, 




AN-245, AN-247, AN-258, AN-260, AN-274, AN-276, 


Phono: AN-346 


AN-281, LB-6, Appendix C, Appendix D 


Power Amplifier: AN-69 



Subject Index (Continued) 

RIAA: AN-346 

Tone Control: AN-69 

Voltage-Controlled: AN-299 

1A Class AB Current Booster: AN-127 

100 mA Current Booster: AN-127 
(See also FM Stereo, Amplifiers) 
AUDIO PREAMPLIFIER 

Flat: AN-346 

Phono: AN-346 
AUDIO MIXER: AN-72 
AUTO ERROR CORRECTION: AN-360 
AUTO GAIN RANGING: AN-360 
AUTOMATIC GAIN CONTROL (See AGC) 
AUTOMOTIVE 

Anti-Skid Circuit: AN-1 62 

Tachometer: AN-1 62 
BANDPASS FILTER: AN-72, AN-307, AN-346, AN-779, 
LB-11 

BANDWIDTH, EXTENDED: AN-29, LB-2, LB-4, 

LB-14.LB-19, AN-813 
BANDWIDTH, FULL POWER: LB-19, AN-769 
BATTERY 

Charger: LB-35 
BATTERY POWERED AMPLIFIERS: AN-71 
BESSEL FILTER: AN-779 
BI-QUAD FILTER: AN-72 
BIAS CURRENT (See Drift Compensation) 

Compensation: AN-3 

Drift Compensation: AN-3 
BIAS CURRENT TEST SET: AN-24 
BLINKER 

Lamp: AN-1 10 

Low Voltage IC: AN-1 54 

Two Wire: AN-1 54 
BOARD LAYOUT: AN-29, AN-813, AN-861 
BOLOMETER (COMPARATOR): LB-32 
BOOTSTRAPPED SHUNT FREQUENCY 

COMPENSATION: AN-29 
BREAKER POINT DWELL METER: AN-1 62 
BRIDGE AMPLIFIER: AN-29, AN-31 
BUFFERS: AN-49, AN-227 

High Current: AN-4, AN-1 3, AN-29, AN-31, 
AN-48, AN-272, LB-44 

Using CMOS Amplifiers: AN-88 
(See also Voltage Followers) 
BUTTERWORTH FILTER: AN-779 
BYPASSING, SUPPLY TERMINAL: AN-4, AN-227, 

AN-253, LB-2, LB-15 
CABLE DRIVER: AN-813 
CAD SYSTEM: AB-7 
CALIBRATOR 

Oscilloscope Square Wave: AN-1 54 



CAPACITANCE MULTIPLIER: AN-29, AN-31 

Digitally Controlled: AN-271 

Programmable: AN-344 
CAPACITIVE TRANSDUCER: AN-1 62 
CAPACITORS 

Bypass: AN-4, AN-428, LB-2, LB-15 

Compensation: AN-29 
(See also Frequency Compensation) 

Dielectric Polarization: AN-29 

Electrolytic as Timing Capacitor: AN-97 

Filter, Power Supply: AN-23 

Multiplier, Capacitance: AN-29, AN-31 

Tantalum Bypass: LB-15 
CARRIER CURRENT TRANSCEIVER: AN-1 46 
CASCODE AMPLIFIER: AN-32 
CHARGER: LB-35 
CHEBYSHEV FILTER: AN-779 
CHOPPER AMPLIFIERS, ALTERNATIVES: AN-79 
CHOPPER DRIVES: AN-828 
CHOPPER STABILIZED AMPLIFIER: AN-49 
CIRCUIT DESCRIPTIONS: AN-49 

LH0002 Current Amplifier: AN-1 3 

LH0033 Buffer Amplifier: AN-48 

LM34/LM35 Temperature Sensor: AN-460 

LM105/LM205/LM305 Positive Voltage 
Regulator: AN-23 

LM108/LM208/LM308 Operational Amplifier: AN-29 

LM109/LM209/LM309 Three Terminal 
Regulator: AN-42 

LM110/LM210/LM310 Voltage Follower: LB-11 

LM111/LM211/LM311 Voltage 
Comparator: AN-41, LB-12 

LM113 1.2 Volt Reference Diode: AN-56 

LM118/LM218/LM318 High Slew Rate Op Amp: LB-17 

LM565 Phase Locked Loop: AN-46 

LM1894 DNRTM; AN-386 

LM3900 Quad Amplifier: AN-72 

LM4250 Micropower Programmable Op Amp: AN-71 
CLAMP 

Back Porch: AN-861 

Grid (CRT): AN-867 

Precision: AN-31 , LB-8 
CLASS A AUDIO AMPLIFIER: AN-72 
CMOS LINEAR AMPLIFIERS (See Amplifiers, CMOS) 
CMOS LOGIC VOLTAGE REGULATOR: AN-71 
COAXIAL CABLE DRIVE: AN-227 
COLD JUNCTION COMPENSATION: AN-222, AN-225 
COMMUTATION: AN-49 
COMPARATORS (See Voltage Comparators) 
COMPENSATION, DRIFT (See Drift Compensation) 
COMPENSATION, FREQUENCY 

(See Frequency Compensation) 
COMPENSATION, TEMPERATURE 

(See Drift Compensation) 



(/> 



a 

X 



Subject Index (Continued) 




COMPONENT NOISE (See Noise, Component) 


High Current: AN-42 


CONTINUITY CHECKER, AUDIBLE: AN-1 54 


Multiple: AN-72 


CONTROL SYSTEM, ENVIRONMENTAL: AN-193 


Precision: AN-20, AN-31, AN-32 


CONVERTER 


Programmable: AN-344 


100 MHz: AN-32 


Two Terminal: AN-1 10 


AC to DC: AN-31, LB-8 


200 mA: AN-1 03 


Analog-to-Digital: (See Analog-to-Digital) 


CURRENT-TO-FREQUENCY CONVERTER: AN-240 


Cable: AN-391 


CURRENT-TO-VOLTAGE CONVERTER: AN-20, AN-31 


Current-to-Voltage: AN-20, AN-31 


DATA ACQUISITION SYSTEM: AN-906 


DC-to-DC: LB-18 (See also Switching Regulator) 


D-TO-A CONVERTER: (See Digital-to-Analog) 


Digitally Programmable Band Pass Filter: AN-299 


DC SERVO-MOTOR CONTROLLERS: AN-460 


Digitally Programmable Panner Attenuator: AN-299 


DC-TO-AC CONVERTER: LB-18 


Frequency to Voltage: AN-97, AN-210, LB-45, 


DELAY SWITCH: AN-110 


Appendix C, Appendix D 


Two Terminal: AN-97 (See also Timers) 


Logarithmic: AN-29, AN-30, AN-31 


DEMODULATORS: AN-49 


Phono Preamp: AN-299 


AM-FM: AN-46 


Voltage Controlled Amplifier: AN-299 


Frequency Shift Keying: AN-46 


Voltage-to-Frequency: AN-286, AN-299, Appendix D 


IRIG Channel: AN-46 


COUNTER, PULSE: AN-72 


Weather Satellite Picture: AN-46 


CRT DEFLECTION CIRCUITRY: AN-656 


DETECTORS: AN-391 


CRT MONITOR: AN-656 


Peak: AN-87, AN-386 


CROSSOVERS 


Pulse Width: (See Pulse Width Detectors) 


Active: AN-346 


Synchronous: AN-391 


CRYSTAL OSCILLATOR: AN-32, AN-41, AN-74, AN-402 


True RMS: LB-25 


CUBE GENERATOR: AN-30, AN-31 


Zero Cross: AN-74 


CURRENT AMPLIFIER 


(See also Demodulators) 


High Output: AN-227, AN-262 


DIELECTRIC ABSORPTION: AN-260 


CURRENT BOOSTER: AN-127, AN-227 


DIELECTRIC POLARIZATION CAPACITOR: AN-29 


CURRENT LIMITING 


DIFFERENCE AMPLIFIER: AN-20, AN-29, AN-31, 


Adjustable: AN-21 


AN-72 


External: AN-21 , AN-29, AN-227 


DIFFERENCE INTEGRATOR: AN-72 


External Circuit: AN-82, AN-227 


DIFFERENTIAL SIGNAL COMMUTATOR: AN-49 


Foldback: AN-82 (See Foldback Current Limiting) 


DIFFERENTIATOR: AN-20, AN-31, AN-72 


Output Short Circuit: AN-72, AN-227 


DIGITAL DIVIDER 




Variable Ratio: AN-286 


Sense Voltage Reduction: AN-21 , AN-31 , AN-32 






DIGITAL GAINSET: AN-344 


Switchback (See Foldback Current Limiting) 






DIGITAL INSTRUMENTATION AMPLIFIER: AN-344 


Switching Regulator: AN-21 






DIGITAL MULTIMETER: AN-202 


Two Terminal Current Limiter: AN-110 






DIGITAL SWITCHING CIRCUITS: AN-72 


1A, 65V Power Supply with Variable Current 




Limit: AN-127 


DIGITAL-TO-ANALOG CONVERTER: AN-48 


CURRENT LOOP: AN-300 


Amplifier Gain Control: AN-271 , AN-284 


CURRENT MEASUREMENT: AN-300 


Composite Low Offset Fast Amplifier: AN-271 


CURRENT MIRROR: AN-72 


Digitally Controlled AC Attenuator: AN-284 


CURRENT MOTOR: AN-31, AN-32, AN-300 


Digitally Controlled Capacitance Amplifier: AN-271 


(See also Current-to-Voltage Converter) 


Digitally Controlled Current Sink: AN-271 


CURRENT NOISE (See Noise, Current) 


Digitally Controlled Function Generator: AN-271 


CURRENT SINK 


High Voltage Output: AN-271, AN-293 


Digitally Controlled: AN-271 


Output Range Level Shifting: AN-271 


Fixed: AN-72 


Plate Driving Deflection Amplifier: AN-293 


Precision: AN-20, AN-31, AN-32 


Processor Controlled Shaker Table Driver: AN-293 


CURRENT SOURCE 


Scanner Control: AN-293 


Bilateral: AN-29, AN-31 




High Compliance: AN-127 





Subject Index (continued) 




Single Supply Voltage Mode: AN-271 


DUAL TRACKING REGULATORS 


Temperature Limit Controller: AN-293 


(See Regulators, Dual Tracking) 


Used as a Digitally Programmable 


DIGITAL VOLT METER (DVM): AN-200 


Potentiometer: AN-271 


DWELL METER: AN-162 


Vernier Adjustment: AN-271 


DYNAMIC SPECIFICATIONS: AN-769 


4-Quadrant Multiplexing: AN-271 


ECL (See Emitter Coupled Logic) 


4 to 20 mA Current Loop: AN-271 


ELECTRONIC SHUTDOWN: AN-82, AN-103 


DIODE 


ELLIPTIC FILTER: AN-779 


Catch: AN-22 


EMI (Electromagnetic Interference): AN-861 


Clamps: AN-861 


EMITTER COUPLED LOGIC, DIRECT 


Precision: AN-31, AN-173, LB-8 


INTERFACING: AN-87 


Protective: AN-21 , AN-861 


EQUALIZER, GRAPHIC: AN-435 


Reference: AN-56, AN-110 


ERRORS 


Zener: AN-56 


Low Error Amplifiers: LB-21 


Zenered Transistor Base-Emitter Junction: AN-71 


Reducing Comparator Errors for 1 jaV Sensitivity: LB-32 


DISCRETE TIME SYSTEM: AN-236 


FEEDFORWARD COMPENSATION: LB-2, LB-14, LB-17 


DISCRIMINATOR, MULTIPLE APERTURE 


FERRITE BEAD: AN-23 


WINDOW: AN-31 


FET 


DIVIDER, ANALOG: AN-4, AN-30, AN-31, AN-222 


Amplifier: AN-32 


DNRtm 


Operational Amplifier Input: AN-4, AN-29, AN-32, 


Applications: AN-390 


AN-447 


Calibration: AN-390 


Switches: AN-32, AN-447 


Cascading: AN-390 


Volt Meter, FET VM: AN-32 


Circuit Design: AN-386 


FILTER: AN-307 


Operating Principles: AN-384 


Adjustable Q: AN-31, LB-5 


DOUBLE ENDED LIMIT DETECTOR: AN-31 


Bandpass: AN-72, AN-71 2, AN-779, LB-11 (See also 


DOUBLE SIDEBAND MODULATOR: AN-38, AN-49 


Filter, Notch) 


DOUBLER, FREQUENCY: AN-41 


Bessel: AN-779 


DRIFT 


Bi-Quad: AN-72 


Minimizing in Amplifiers: LB-22, LB-32, AN-242 


Butterworth: AN-779 


DRIFT COMPENSATION: AN-79, AN-242 


Chebeyshev: AN-779 


Bias Current: AN-3, AN-20, AN-29, AN-31 


Digitally Programmable Gain: AN-269 


Board Layout: AN-29 


Elliptic: AN-779 


Gain, Transistor: AN-56 


Full Wave Rectifying and Averaging: AN-20, AN-31 


Guarding Inputs: AN-29 


High Pass Active Filter: AN-31, AN-72, AN-227, 
AN-346, LB-11, AN-779 


Integrator, Low Drift: AN-31 


Infrasound: AN-346 


Non-Linear Amplifiers: AN-4, AN-31 


Low Pass Active Filter: AN-20, AN-31 , AN-72, 


Offset Voltage: AN-3, AN-20, AN-31, AN-242 


AN-286, AN-346, AN-779 


Reset Stabilized Amplifier: AN-20 


Low Distortion: AN-346, AN-386 


Sample and Hold: AN-4, AN-29 


Low Pass Adjustable: AN-384, AN-386 


Transistor Gain: AN-56 


Notch: AN-31, AN-48, AN-227, AN-71 2, AN-779, LB-5, 


Voltage Regulator: AN-21, AN-23, AN-42, LB-15 


LB-11 


DRIFT, VOLTAGE AND CURRENT: AN-29 


Notch, Adjustable Q: AN-31, AN-779, LB-5 


(See also Drift Compensation) 


PID: AN-693, AN-706 


DRIVERS 


Power Supply: AN-23, LB-10 


Cable: AN-813 


Programmable: AN-344 


Chopper: AN-828 


Sallen Key: AN-779 


L/R: AN-828 


Sensitivity Functions: AN-72 


MOS Clock Driver: AN-74 


Surface Acoustic Wave: AN-391 


Zero Crossing Detector and Line Driver: AN-162 


Switched Capacitor: AN-779 


(See also Voltage Followers, Buffers, Amplifiers) 


Tone Control: AN-32 




Ultrasound: AN-346 




Vestigial Side Band: AN-402 



CO 

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Subject Index (Continued) 




FLASHER 


Pulse Generator: AN-74 


Inexpensive IC: AN-154 


Sine Wave: AN-115 


Lamp: AN-110 


Square Wave: AN-74, AN-88, AN-154, LB-23 


Two Wire: AN-154 


Staircase: AN-88, AN-162 


FLIP-FLOP, TRIGGER: AN-72 


Time Delay: AN- 14 


FLUID LEVEL CONTROL: AB-10 


Triangle Wave: LB-23 (See also Oscillator) 


FLYBACK POWER SUPPLY: AN-656 


GRAPHIC EQUALIZER 


FM 


Digitally Controlled: AN-435 


Blend: AN-390 


GUARD DRIVER: AN-48, AN-227 


Calibration Modulation Level: AN-402 


GUARDING AMPLIFIER INPUTS: AN-29 


FM STEREO 


GYRATOR (See Inductor, Simulated) 


Remote Speaker: AN- 146 


H-BRIDGE: AN-693, AN-694 


FOLDBACK CURRENT LIMITING 


HALL EFFECT SENSOR (COMPARATOR): LB-32 


Negative Voltage Regulator: AN-21, LB-3 


HARMONIC DISTORTION: AN-769 


Positive Voltage Regulator: AN-23, LB-3 


HIGH FREQUENCY: AN-227, AN-253, AN-391 


Power Dissipation Curve: AN-23 


HIGH PASS ACTIVE FILTER: AN-31, AN-72, AN-307, 


Temperature Sensitivity: AN-23 


AN-346, AN-779, LB-1 1 


(See also Current Limiting, Foldback) 


HIGH PASS FILTER: AN-227, AN-307, AN-346 


FOLLOWERS, VOLTAGE (See Voltage Followers) 


HIGH SPEED DUAL COMPARATOR: AN-115 


FREQUENCY COMPENSATION: AN-79 


HIGH SPEED OP AMP: AN-278, AN-428, AN-813, LB-42 


Bandwidth, Extended: AN-29, LB-2, LB-4, LB-14, 


HIGH SPEED PEAK DETECTOR: AN-227 


LB-19, LB-42 


HIGH SPEED SHIELD/LINE DRIVER: AN-227 


Bootstrapped Shunt: AN-29 


HIGH VOLTAGE 


Capacitance, Stray: AN-4, AN-31, AN-428 


Driver: AN-49 


Capacitive Loads: AN-4, AN-447, LB-14, LB-42 


Flasher: AN-154 


Differentiator: AN-20 


Op Amp: AN-127 


Feedforward: LB-2, LB-14, LB-17 


Regulator: AN-103 


Ferrite Bead: AN-23 


HUMIDITY MEASUREMENT: AN-256 


Hints: AN-4, AN-20, AN-23, AN-41, AN-447, 


INDICATOR 


LB-2, LB-4, LB-42 






Applications: AN-154 


Multiplier: AN-21 


INDUCTANCE-RESISTANCE (L/R) DRIVERS: AN-828 


Multivibrator: AN-4 


INDUCTOR 


Oscillation, Involuntary: AN-4, AN-20, AN-29 


Core, Switching Regulator: AN-21 


FREQUENCY DOUBLER: AN-41 


Ferrite Bead: AN-23 


FREQUENCY RESPONSE: LB-19 


Simulated: AN-31, AN-435, AN-712 


(See also Frequency Compensation) 




FREQUENCY SHIFT KEYING DEMODULATOR: AN-46 


Voltage-Controlled: AN-712 


FREQUENCY-TO-CURRENT CONVERTER: AN-162 


INSTRUMENTATION AMPLIFIER 
(See Amplifiers, Instrumentation) 


FREQUENCY-TO-VOLTAGE CONVERTER: AN-97, 


INPUT GUARDING: AN-29, AN-48 


AN-162, AN-21 




FULL POWER BANDWIDTH: LB-19, AN-769 


INTEGRATOR: AN-20, AN-29, AN-31, AN-32, 
AN-72 


FUNCTION GENERATOR (See Generator) 


INTERMODULATION DISTORTION: AN-769 


GAIN CONTROL 


INTERNAL TIMER: AN-31 


Digital: AN-269 


INTRUSION ALARM 


Voltage Controlled: AN-299 (See also AGC) 


Fiber Optic: AN-266 
INVERTING AMPLIFIER: AN-20, AN-31, AN-71, 


GAIN TEST SET: AN-24 


GATES, OR AND AND: AN-72 


AN-72, LB-17 


GENERATOR 


ISOLATED INPUT SIGNAL CONDITIONING 


Digitally Controlled: AN-435 


AMPLIFIER: AN-266 


Multiple Function: AN-115, LB-23 


ISOLATION AMPLIFIER: AN-266, AN-285 


One Shot: AN-88 


ISOLATION, DIGITAL: AN-41 


Programmable: AN-344 





Subject Index (Continued) 
ISOLATION TECHNIQUES 

Thermocouple: AN-298 

Transformer: AN-266, AN-285 
JFETs: AN-32 

JUNCTION TEMPERATURE, MAX ALLOWABLE: AN-336 
LAMP DRIVER 

Ground Referenced: AN-72 

Voltage Comparator: AN-4, AN-72, LB-12 
LARGE SIGNAL RESPONSE: LB-19 
LED (See Light Emitting Diode) 
LEVEL DETECTOR WITH HYSTERESIS: AN-87 
LEVEL SHIFTING AMPLIFIER: AN-4, AN-13, 

AN-32, AN-41, AN-48 
LIGHT ACTIVATED SWITCH: AN-10 
LIGHT EMITTING DIODE 

1.5V LED Flasher: AN-1 54 
LIMIT DETECTOR: AN-31 
LIMITER (See Clamp) 
LINE DRIVER: AN-13, AN-48 
LINE RECEIVER AMPLIFIER: AN-72 

LINE RECEIVERS, COMPARATORS SUITABLE 

FOR: AN-87 
LIQUID DETECTOR: AB-10, AN-1 54 
LM12 150- WATT OP AMP: AN-446 
LOGARITHMIC AMPLIFIER: AN-29, AN-30, 

AN-31, AN-211 

DAC Controlled Scale Factor: AN-269 

Digitally Programmable: AN-269 
LOGARITHMIC CONVERTER: AN-31 1 
LOW PASS ACTIVE FILTER: AN-20, AN-31, AN-72, 

AN-307, AN-346, AN-779 

LOW DRIFT AMPLIFIERS (See Amplifiers, Low Drift) 
LVDT 

Position Sensor: AN-30 1 
MACROMODELS (See Models, Spice) 
MAGNETIC 

Variable Reluctance Pickup Buffer: AN-1 62 
MAGNETIC FIELD SENSOR: AN-301 
MAGNETIC TAPE: AN-390 
MAGNETIC TRANSDUCER AMPLIFIER: AN-74 
METER AMPLIFIER: AN-71, AN-222, AN-265 
MICROPHONE PREAMPLIFIER: AN-299, AN-346 
MICROPOWER 

Amplifier: AN-71, AN-211 

Circuit Description LM4250 Programmable 
Op Amp: AN-71 

Voltage Comparator: AN-71 
MIXER 

Audio: AN-72 

Low Frequency: AN-72 
MODELS 

Spice: AN-813, AN-840, AN-856 



MODEM FILTER: AN-307 

MODULATION AND DEMODULATION: AN-38, AN-49, 

AN-402 
MODULATOR 

FM Audio: AN-402 

Pulse Width: AN-31 
MOISTURE DETECTOR: AB-10, AN-1 54 
MONOSTABLE MULTIVIBRATORS (See Multivibrator) 
MOS ANALOG SWITCH: AN-49 
MOS DIFFERENTIAL SWITCH: AN-49 
MOTION CONTROL: AN-693, AN-706 
MOTION DETECTOR (See Sensor, Air; Sensor, Liquid) 
MOTOR CONTROL: AN-693, AN-694 
MOTOR SPEED CONTROLLER: AN-292 
MOTOR, STEPPER: AN-828 

MOTOR TORQUE CONTROLLER: AN-693, AN-828 
MULTIPLEXER (See Analog Switch) 
MULTIPLIER 

Analog: AN-4, AN-20, AN-30, AN-31 , AN-222 

Capacitance: AN-29, AN-31 

Cube Generator: AN-30, AN-31 

Resistance: AN-29 

MULTIVIBRATOR: AN-4, AN-24, AN-31, AN-41, 
AN-71, AN-72, AN-74 

NEGATIVE AND POSITIVE VOLTAGE REGULATORS 

(See Symmetrical Voltage Regulators) 
NEGATIVE REGULATOR 

(See Negative Voltage Regulators) 
NEGATIVE VOLTAGE REFERENCE: AN-20, AN-31 
NEGATIVE VOLTAGE REGULATOR 

Circuit Description LM104/LM204/LM304: AN-21 

Drift Compensation 
(See Drift Compensation, Voltage Regulator) 

Foldback Current Limiting: AN-21, LB-3 

High Current: AN-21 

High Voltage: AN-21 

Hints: LB-15 

Line Regulation Improvement: AN-21 

Low Dropout Voltage: AN-21 1 

Overvoltage Protection: AN-21 

Power Dissipation: AN-21 

Precision, Stable: LB-15 

Programmable: AN-20, AN-31 

Protective Diodes: AN-21 

Remote Sensing: AN-21 

Ripple: AN-21 

Switching: AN-21 

Three Terminal: AN-1 82 

Transient Response: AN-21 
NIXIE DRIVER: AN-32 



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Subject Index (Continued) 




NOISE: 


L/C: AN-402 


Component: AN-104 


Morse Code: AN-1 54 


Figure: AN-104, AN-222, AN-391 


Multivibrator: AN-4, AN-24, AN-31, AN-41, 


Filtering in Microvolt Comparators: LB-32 


AN-71, AN-72 


Generator, "Buzz Box": AN-154 


One Shot: AN-88 


l/F: AN-104 


Piezoelectric Driver: AN-72 


Measurement: AN-180 


Programmable "Unijunction": AN-72 


Television Receiver: AN-391 


Pulse: AN-97 


Thermal: AN-104 


Pulse Output: AN-71, AN-72 


Theory: AN-222 


Quadrature Output: AN-31, LB-16 


Voltage: AN-104 


RF: AN-402 


Weighting: AN-384 


RF JFET: AN-32 


NOISE REDUCTION 


Sawtooth: AN-72 


Audio: AN-384, AN-386 


Sine Wave: AN-20, AN-29, AN-31, AN-32, 


Comparison of Types: AN-384 


AN-72, AN-1 15, AN-264, AN-712, LB-16 


Complementary: AN-384 


Square Wave: AN-88 


FM: AN-390 


Staircase: AN-72 


Masking: AN-384, AN-386 


Television: AN-402 


Single-Ended: AN-384, AN-386, AN-390 


Triangle Wave: AN-20, AN-24, AN-31, AN-72 


Tape: AN-390 


Tunable Frequency: LB-16 


Television Audio: AN-390 


Vestigial Side Band: AN-402 


VTR: AN-390 


Video: AN-402 


NON-INVERTING AMPLIFIER: AN-20, AN-31, AN-72 


Voltage-Controlled: AN-24, AN-72, AN-81, 




AN-1 46, AN-1 62, AN-391, Appendix C 


NON-LINEAR AMPLIFIER: AN-4, AN-31 






Wien Bridge: AN-20, AN-31, AN-32 


NORTON AMPLIFIER: AN-72, AN-278 






OVERSPEED LATCHES/INDICATORS 


NOTCH FILTER: AN-31, AN-48, AN-307, AN-779, LB-5, 

LB-11 
OFFSET 


(See Frequency-to-Voltage) 


PACKAGE POWER CAPABILITIES: AN-336 


PARALLELING OP AMP: LB-44 


Ajusting Offset and Drift to Almost 
Zero: AN-79, LB-32, AN-242 


PEAK DETECTOR: AN-4, AN-31, AN-72, AN-74, 




AN-87, AN-227, AN-386 


Drift Compensation: AN-3 


PHASE 


Voltage Compensation: AN-3 


Phase Shift Oscillator: AN-88 


OFFSET CURRENT TEST SET: AN-24 






PLL Range Extender: AN-1 62 


OFFSET VOLTAGE ADJUSTMENT: LB-9 






Wide Range Phase Shifter: AN-391 


OFFSET VOLTAGE COMPENSATION 




(See Drift Compensation) 


PHASE COMPARATOR: AN-72 


OFFSET VOLTAGE TEST SET: AN-24 


PHASE LOCKED LOOP: AN-1 46, AN-391, AN-81 


ONE SHOT: AN-72, AN-88 


Advantages as Voltage-to-Frequency 




Converter: AN-210 


OPERATIONAL AMPLIFIERS: 




(See Amplifiers, Operational) 


Circuit Description LM565: AN-46 


OPERATIONAL AMPLIFIER TESTING: AB-12 


Damping: AN-46 


OPERATIONAL AMPLIFIER TEST SET: AN-24 


FM Audio Modulation: AN-402 


OPERATIONAL AMPLIFIER VOLTAGE 


Locking: AN-46 


REFERENCE: AN-288 


Loop Filter: AN-46 


OPTICALLY ISOLATED SWITCHES 


Multiamplifier: AN-72 


(See Switches, Optically Isolated) 


Noise Performance: AN-46 


OR GATE: AN-72, AN-74 


Phase Comparator: AN-72 


Regulator: AN-103 


Theory: AN-46 


OSCILLATION, INVOLUNTARY 


VCO: AN-72 


(See Frequency Compensation) 


PHASE SHIFT OSCILLATOR: AN-88 


OSCILLATOR 


PHASE SHIFTER: AN-32 


Crystal: AN-41, AN-74, AN-402 


PHONO PREAMPLIFIER: AN-32, AN-222, AN-346 


Crystal JFET: AN-32 


PHOTOCELL AMPLIFIER: AN-20 


Fiber Optic: AN-266 




Inexpensive IC: AN-154 





Subject Index (Continued) 
PHOTODIODE 

Amplifier: AN-20, AN-29, AN-31, AN-244, LB-12 

Level Detector: AN-41, AN-244 
PHOTORESISTOR AMPLIFIER: AN-29 
PID CONTROLLER: AN-693, AN-706 
PIN DIODE DRIVER: AN-49 
PIN DIODE SWITCHING: AN-49 
POLARITY SWITCHER: AN-344 
POLARIZATION, DIELECTRIC: AN-29 
POSITION SENSOR: AN-162 

LVDT: AN-301 
POSITIVE AND NEGATIVE VOLTAGE REGULATORS 

(See Symmetrical Voltage Regulators) 
POSITIVE REGULATOR (See Regulator, Positive) 
POSITIVE VOLTAGE REFERENCE: AN-20, AN-31, AN-56 
POSITIVE VOLTAGE REGULATOR 

Adjustable Output: AN-42, AN-178, AN-181, 
AN-182, LB-35 

Bootstrapped Regulator: AN-21 1 

Circuit Description LM105/LM205/LM305: AN-23, 
AN-21 1 

Circuit Description LM109/LM209/LM309: AN-42 

CMOS Compatible: AN-71 

Current Limit: AN-72, AN-21 1 

Drift Compensation 
(See Drift Compensation, Voltage Regulator) 

Failure Mechanisms: AN-23 

Filtering, Power Supply: AN-23 

Fixed Output: AN-42 

Foldback Current Limiting: AN-23 

Heat Dissipation: AN-23 

High-Current: AN-23, AN-72 

High Voltage: AN-72, AN-21 1 , LB-47 

Hints: AN-23, LB-15 

Low Voltage: AN-56, AN-21 1 

Micropower Quiescent Power Drain: AN-71, AN-21 1 

NPN Pass Transistors: AN-72 

Power Limitations: AN-23 

Precision: AN-42, LB-15 

Programmable Low Power: AN-20, AN-31 

Protection: AN-23, AN-72 

Ripple Induced Failures: AN-23 

Switching Regulator (See Switching Regulator) 

Temperature Compensation: AN-42, LB-15 

Three Terminal: AN-103, AN-178, AN-182, LB-35 

Trimming Output Voltage: LB-46 
(See also Voltage Regulators) 
POWER AMPLIFIER (See Buffer, High Current) 
POWER CAPABILITIES, IC PACKAGE: AN-336 
POWER DISSIPATION 

Regulator: AN-82, AN-103 

H-Bridge: AN-694 
POWER LINE CARRIER: AN-146 



POWER SUPPLY: AN-56 

General Purpose: LB-28 

Monitor: LB-48 

Programmable: LB-49 (See also Regulators) 

Split: AN-69, AN-71 
PREAMPLIFIER 

CRT: AN-861 

Phono: AN-32, AN-222, AN-346 

Servo: AN-4, AN-31 

Stereo: AN-346 

Video: AN-861 
(See also Amplifiers, Preamp) 
PRECISION REFERENCE: AN-161, AN-173 
PROGRAMMABLE GAIN: AN-289 
PROGRAMMABLE OP AMP: AN-71 

PROGRAMMABLE "UNIJUNCTION" 
OSCILLATOR: AN-72 

PROGRAMMABLE VOLTAGE REGULATOR: 

AN-20, AN-31 

PULSE AMPLIFIER: AN-13, AN-813 
PULSE COUNTER: AN-72 
PULSE GENERATOR: AN-71, AN-72, AN-74 
PULSE STRETCHER: 

Proportional: AN-266 
PULSE WIDTH DETECTOR: AN-97 
PULSE WIDTH MODULATOR: AN-21, 

AN-31, AN-74, LB-18 

PULSE WIDTH MULTIVIBRATOR: AN-292 
PYROELECTRIC 

Accelerometer: AN-301 

Detector Amplifier: AN-301 

Resonator Temperature Sensor: AN-301 
QUAD AMPLIFIER: AN-71, AN-72 
QUAD COMPARATOR: AN-74 

QUADRATURE OSCILLATOR: AN-31, AN-307, LB-16 
RATE GYRO: AN-301 
RECEIVER 

FM Remote Speaker: AN-146 

Infared: AN-290 

Television: AN-391 

VHF: AN-290 

Ultrasonic: AN-290 
RECTIFIER, FAST HALF-WAVE: AN-31, LB-8 
RECTIFIER, FULL-WAVE: AN-20, LB-8 
REFERENCE 

Low Drift Precision 6.9V: AN-161, AN-173, AN-184 

Micropower: AN-222, LB-34, LB-41 

Precision: AN-79, AN-161, LB-41 
REFERENCE DIODE: AN-110 
REFERENCE VOLTAGE: AN-21 1 
REFERENCE VOLTAGE DETECTOR: AN-300 
REFERENCE VOLTAGE REGULATOR: AN-20, AN-31 
REGULATORS (See Voltage Regulators) 



c 
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a 

X 



Subject Index (Continued) 
RELAY DRIVER: AN-72 
REMOTE LINKS 

Infared: AN-290 

VHF: AN-290 

Ultrasonic: AN-290 
REMOTE SENSING 

High Current Negative Regulator: AN-21 

High Negative Voltage: AN-21 
REMOTE SPEAKER SYSTEM: AN-146 
REMOTE TEMP SENSOR/ ALARM: AN-74 
RESET STABILIZED AMPLIFIER: AN-20 
RESISTANCE 

Choice of Resistors for Op Amps: AN-79 

Tester for Low Values of Resistance: LB-32 
RESISTANCE MULTIPLICATION: AN-29 
RESISTOR VALUES, STANDARD: Appendix E 
RF: AN-391 
RF AMPLIFIER 

Cascode: AN-32, AN-813 
RF OSCILLATOR (See Oscillator, RF) 
RIAA PHONO PREAMPLIFIER: AN-222, 

AN-299, AN-346 
RIPPLE, POWER SUPPLY: AN-21, AN-23, LB-10 
RISE TIME, AMPLIFIER: LB-19 
RMS 

True RMS Detector: LB-25 
ROOT EXTRACTOR: AN-4, AN-31, AN-222 
RTD CONTROLLER: AN-292 
SAFE AREA PROTECTION: AN-103 
SALLEN-KEY FILTER: AN-779 
SAMPLE AND HOLD: AN-4, AN-29, AN-31, AN-32, 

AN-72, AN-266, AN-294, LB-1 1 , LB-45 

Circuit: AN-286 

Extended HOLD Time: AN-245, AN-294 

High Speed: AN-253, AN-294 

HOLD Step: AN-294 

Infinite: AN-245 

Infinite HOLD Time: AN-245, AN-294 

Reduction of HOLD Step: AN-245, AN-294 

Terms: AN-266 
SAMPLING THEOREM: AN-236 
SAWTOOTH GENERATOR: AN-72 
SCHMITT TRIGGER: AN-32, AN-72 
SENSE VOLTAGE (See Current Limiting) 
SENSITIVITY FUNCTIONS: AN-72 
SENSOR 

Mass Velocity: AN-162 

Rotational Velocity: AN-162 
SERVO PREAMPLIFIER: AN-4, AN-31 
SETTLING TIME: LB-1 7 

SHORT CIRCUIT PROTECTION (See Current Limiting) 
SIGNAL-TO-NOISE RATIO: AN-104, AN-769 



SINE SHAPER: AN-263 

SINE WAVE GENERATOR: AN-115, AN-263, 

AN-269, AN-307 
SINE WAVE OSCILLATOR: AN-20, AN-29, AN-31, 

AN-32, AN-72, AN-263, LB-1 6 

Crystal: AN-263 

Digital: AN-263 

High Voltage: AN-263 

Phase Shift: AN-263 

Sine Wave Voltage Reference: AN-262 

Tuning Fork: AN-263 

Voltage-Controlled: AN-262 

Wien Bridge: AN-263 
SINE WAVE RESPONSE: LB-19 
SINGLE SUPPLY AMPLIFIER: AN-72 
SINGLE SUPPLY OPERATION: AN-31, AN-48 
SIREN OSCILLATOR: AN-154 
SLEW RATE: LB-1 7, LB-19, LB-42 

(See also Frequency Compensation, Feedforward) 
SLEW RATE LIMITING: LB-19 
SMALL SIGNAL RESPONSE: LB-19 
S/N RATIO (See Signal-to-Noise Ratio) 
SOLAR CELL AMPLIFIER: AN-4 
SOUND 

Peak: AN-384 

Pressure: AN-384 

Sound Effects Oscillator: AN-154 
SPEED SENSOR (See Sensor, Speed) 
SPEED SWITCH (See Frequency-to-Voltage Converter) 
SPICE (See Models) 

SQUARE ROOT CIRCUIT: AN-4, AN-31, AN-222 
SQUARE WAVE GENERATOR: AN-74, AN-88, AN-115, 

AN-154, AN-222, LB-23 
SQUARING AMPLIFIER: AN-72, AN-222 
SQUARING CIRCUITS: AN-222 
STAIRCASE GENERATOR: AN-72, AN-88 

(See also Generator, Staircase) 
STANDARD VALUES RESISTOR: Appendix E 
STEP RESPONSE: LB-19 
STEPPER MOTOR: AN-828 
STEREO (See FM Stereo) 
STEREO PREAMPLIFIER: AN-346 
STRAIN GAUGE CONVERTER: AN-301 
SUBTRACTOR (See Difference Amplifier) 
SUMMING AMPLIFIER: AN-20, AN-31 
SUPPLY VOLTAGE SPLITTING: AN-31 
SWITCHED CAPACITOR FILTER: AN-307, AN-779 
SWITCHES 

Optically Isolated: AN-110 

Two Terminal Time Delay: AN-97 
SWITCH, ANALOG: AN-32 
SWITCHBACK CURRENT LIMITING 
(See Foldback Current Limiting) 



Subject Index (Continued) 
SWITCHING REGULATOR: AN-343, AN-97, 

AN-110, AB-30, AN-711 

Buck Converter: AN-343, AN-71 1 

Boost (Step-Up) Converters: AN-711 

Circuit Description LH1605: AN-343 

Circuit Description LM78S40: AN-711 

Current Limiting: AN-2, AN-21 

DC Motor Speed Regulation: AN-343 

Dissipation: AN-21 

Driver: AN-2, AN-21 

Dual-Output: AB-30 

Efficiency: AN-21 

Forward Converter: AN-776 

High Negative Current: AN-21 

Hint: AN-21 

Inductor Core Selection: AN-21 , AN-71 1 

Inverting (DC Plus to DC Minus) 
Converter: AN-711, LB-18 

Isolated Flyback: AN-777 

Line Regulation: AN-21 

Negative: AN-21 

Overload Shutdown: AN-21 

Polarity Conversion: LB-18 

Theory: AN-711, LB-18 
SYMMETRICAL VOLTAGE REGULATOR 

Tracking Regulator: AN-20 
SYNCHRONOUS 

Video Detector: AN-391 
TACHOMETER: AN-72, AN-97 
TAPE READER 

Magnetic: AN-74 
TAPE COMPENSATION 

Weighing System: AN-271 
TELEVISION: AN-402 
TEMPERATURE: AN-292 

Centigrade Sensors: AN-460 

Controller: AN-293 

Farenheit Sensors: AN-460 

Oven Controller: AN-262 

Platinum RTD High Temperature: AN-262 

Timer Used as Controller: AN-97 

Transducer: AN-225, AN-460 

Transducer, Micropower: LB-27 
TEMPERATURE COMPENSATED ZENER DIODE: AN-56 
TEMPERATURE COMPENSATION 

(See Drift Compensation) 
TEMPERATURE CONTROLLER: AN-286, AN-292, AN-293 
TEMPERATURE CONTROL: AN-262, AN-293 

Precision: AN-266 

High Efficiency: AN-266 
TEMPERATURE PROBE AMPLIFIER: AN-31, AN-56 



TEMPERATURE PROBE COMPARATOR: AN-72 
TEST SET, OPERATIONAL AMPLIFIER: AN-24 
THERMAL CAPABILITIES, DEVICE: AN-336 
THERMAL FEEDBACK REDUCTION IN 

MICROVOLT COMPARATORS: LB-32 
THERMAL NOISE (See Noise, Thermal) 
THERMAL SHUTDOWN: AN-82, AN- 103 
THERMOCOUPLE: AN-225 

Amplifier with Cold Junction Compensation: AN-21 1 , 
AN-222, AN-225, LB-24 

Comparator: LB-32 

Effects on IC's: AN-79, LB-22, LB-32 
THERMOMETER: AN-262 

Electronic: AN-225, AN-233 

Micropower: LB-27, AN-21 1 

Temperature Controller: AN-97 

Thermocouple: LB-24 

Using Platinum Sensor: AN-286 
THERMOMETER, ELECTRONIC: AN-31, AN-56 
THRESHOLD DETECTOR: AN-20, AN-31 
TIME DELAY GENERATOR: AN-74 
TIME, INTERVAL: AN-31 
TIMER CIRCUITS: AB-7, AN-97, AN-110 
TIMERS 

Chain of Timer: AN-97 

Cycle Interrupt: AN-97 

Dual Supply Operation: AN-97 

Electrolytic Timing Capacitors: AN-97 

Eliminating Timing Cycle upon Initial 
Application of Power: AN-97 

Linearizing Charging Sweep: AN-97 

Negative Pulse Triggering: AN-97 

Noise Immunity: AN-97 

One Hour: AN-97 

Time Delay Circuit: AN-1 10 

Time Out, Power Up: AN-97 

Wide Range Timer: LB-38 

Zero Power Dissipation between 
Timing Intervals: AN-97 

5V Logic Supply Driving 28V Relay: AN-97 

30V Supply Interfacing with 5V Logic: AN-97 
TIMING ERROR: AN-97 
TONE CONTROL: AN-32, AN-435 

Stereo: AN-435 
TOTAL HARMONIC DISTORTION: AN-1 80 
TRANSCONDUCTANCE AMPLIFIER: AN-386 
TRANSDUCER 

Amplifier: LB-24 

Signal Conditioners: AN-301 

Temperature: LB-27 
TRANSFER FUNCTION TEST SET: AN-24 



Subject Index (Continued) 
TRANSISTOR 

Low Noise: AN-222 

Optically Isolated: AN-110 

Power, Protected: AN-110 
TRANSMITTER 

FM Remote Speaker: AN-146 

Infared: AN-290 

Two Wire: AN-21 1 

VHF: AN-290 

Ultrasonic: AN-290 
TRIAC TRIGGER: AN-154 
TRIANGLE WAVE OSCILLATOR: AN-20, AN-24, 

AN-31, AN-72 
TRIGGER APPLICATIONS: AN-154 
TRIGGER, FLIP-FLOP: AN-72 
TRIGGER, SCHMITT: AN-32, AN-72 
TUNED RF CIRCUITS (See Amplifiers) 
TV (See Television) 
UNITY-GAIN BUFFER: AN-20 
VCO (See Voltage-Controlled Oscillator) 
VELOCITY SENSOR (See Sensor, Velocity) 
VIDEO: AN-391, AN-656 
VOLTAGE COMPARATOR: AN-41, AN-74, 

AN-103, AN-288, LB-39 

A-to-D Converter Circuit: LB-6 

AC Coupled: LB-6 

Avoiding Oscillations: LB-39 

Buffered Output: AN-29 

Circuit Description LM1 1 1 /LM21 1 /LM31 1 : 
AN-41, LB-12 

Comparison: AN-87, LB-12 

DTL Driver: AN-4, AN-29, AN-31, LB-12 

Dual Limit, High Speed: AN-48 

Fast: LB-6 

High Current: AN-71 

High Speed Differential: AN-87 

Hints: AN-41 

Inverting and Non-Inverting with Hysteresis: AN-74 

Lamp Driver: AN-4, AN-72, LB-12 

Micropower: AN-71 

Microvolt: LB-32 

MOS Driver. AN-41, LB-12 

Op Amp Voltage Comparator: AN-4, AN-71, AN-72 

Preamplifier: LB-32 

Quad Array: AN-74 

Specifying Selected Parameters: LB-26 

Timers Used as: AN-97 

TTL Driver: AN-4, AN-29, AN-31, AN-41, LB-12 

Zero Crossing: AN-31, AN-41, LB-6, LB-12 
VOLTAGE CONTROLLED AMPLIFIER: AN-299 



VOLTAGE CONTROLLED OSCILLATOR: AN-72, 

AN-74, AN-81, AN-146, AN-162, AN-391 

(See also Voltage-to-Frequency Converter) 
VOLTAGE FOLLOWER: AN-63 

Bias Current: AN-20 

Circuit Description LH0033: AN-48 

Circuit Description LM110/LM210/LM310: LB-11 

Comparison: LB-11 

Frequency Compensation: LB-42 

Hints, Operating: AN-20 

Offset Adjustment: AN-31, LB-9 

Single Supply: AN-72 

Voltage Reference: AN-20, AN-31, AN-56 

1 Amp: AN-110 
VOLTAGE NOISE (See Noise, Voltage) 
VOLTAGE REFERENCES (See Reference) 
VOLTAGE REGULATORS: AN-178 

(See also Regulators, Voltage; Positive, Negative, 

or Switching Voltage Regulator) 

Adjustables: AN-178, AN-181, AN-21 1, AB-11, 
AB-12, LB-46 

Automotive: AB-12 

Battery Charging: AB-11, AB-12 

Current: AN-103, AN-110, AN-127 

Dual Tracking: AN-82, AN-103 

High Current: AN-103, AN-110 

High Current Dual Tracking: AN-82 

High Current Regulators: AB-1 1 

High Input Voltage: AN-103, AN-21 1 

Improving Reliability: AN-182 

Low Dropout: AB-11, AB-12 

PNP: AB-11, AB-12 

Trimming: LB-46 

1A, 65V with Variable Current Limit: AN-127 

± 32.5V Dual Tracking: AN-127 
VOLTAGE-TO-FREQUENCY CONVERTER: AN-21 0, 

AN-240, LB-45, Appendix C, Appendix D 

(See also Analog-to-Digital Converters and 

Voltage-Controlled Oscillators) 
VOLT METER: AN-32, AN-71, LB-45 
WEIGHING SYSTEM 

Precision: AN-295 
WIEN BRIDGE OSCILLATOR: AN-20, AN-31, 

AN-32, AN-263 
WINDOW DISCRIMINATOR, MULTIPLE 

APERATURE: AN-31 
ZENER DIODE 

IC: AN-56 

Transistor Base-Emitter Junction: AN-71 
ZENERS (See Reference) 
ZERO CROSSING DETECTOR: AN-31, AN-41, AN-74, 

LB-6, LB-12 

Comparators Suitable for "Two Shot": AN-87, AN-162 
8080 MICROPROCESSOR: AN-200 



Drift Compensation 
Techniques for Integrated 
DC Amplifiers 

Robert J. Widlar 
Apartado Postal 541 
Puerto Vallarta, Jalisco 
Mexico 

introduction 

With DC amplifiers, it is usually possible to substantially im- 
prove drift performance by using additional circuitry along 
with some form of adjustment. In fact, one of the reasons 
that discrete-component operational amplifiers have better 
input current specifications than monolithic amplifiers is that 
current compensation is used. Monolithic circuits cannot in- 
corporate these techniques because it is not possible to 
select components or make adjustments. These adjust- 
ments can, however, be made external to the amplifier. This 
article will discuss a number of compensation methods 
which can substantially reduce the input currents of mono- 
lithic amplifiers, especially in limited-temperature-range ap- 
plications. 

Bias current compensation reduces offset and drift when 
the amplifier is operated from high source resistances. With 
low source resistances, such as a thermocouple, the drift 
contribution due to bias current can be made quite small. In 
this case, the offset voltage drift becomes important. 
A technique is presented here by which offset voltage drifts 
better than 0.5 jaVVC can be realized. The compensation 
technique involves only a single room-temperature balance 
adjustment. Therefore, chopper-stabilized performance can 
be realized, with low source resistances, in a fairly-simple 
amplifier without tedious cut-and-try compensation 
methods. 

bias current compensation 

The simplest and most effective way of compensating for 
bias currents is shown in Figure 1. Here, the offset produced 
by the bias current on the inverting input is cancelled by the 
offset voltage produced across the variable resistor, R3. 
The main advantage of this scheme, besides its simplicity, is 
that the bias currents of the two input transistors tend to 
track well over temperature so that low drift is also 
achieved. The disadvantage of the method is that a given 
compensation setting works only with fixed feedback resis- 
tors, and the compensation must be readjusted if the equiv- 
alent parallel resistance of R1 and R2 is changed. 



National Semiconductor 
Application Note 3 





Figure 1. Summing amplifier with bias-current compen- 
sation for fixed source resistances 

Figure 2 shows a similar circuit for a non-inverting amplifier. 
The offset voltage produced across the DC resistance of 
the source due to the input current is cancelled by the drop 
across R3. For proper adjustment range, R3 should have a 
maximum value about three times the source resistance 
and the equivalent parallel resistance of R1 and R2 should 
be less than one-third the input source resistance. 
This circuit has the same advantages as that in Figure 1, 
however, it can only be used when the input source has a 
fixed DC resistance. In many applications, such as long-in- 
terval integrators, sample-and-hold circuits, switched-gain 
amplifiers or voltage followers operating from unknown 
source, the source impedance is not defined. In these cases 
other compensation schemes must be used. 
Figure 3 gives a compensation technique which does not 
depend upon having a fixed source resistance. A current is 
injected into the input terminal from the base of a PNP tran- 
sistor. Since NPN input transistors are used on the integrat- 
ed amplifier,* the base current of the PNP balances out the 

•This is true for all monolithic operational amplifiers presently available. 




TL/H/6925-2 



Figure 2. Non-inverting amplifier with bias-current compensation for fixed source resistances 




Select for zero input current 



Figure 3. Summing amplifier with bias-current compen- 
sation 




•Select for zero input current 



TL/H/6925-4 

Figure 4. Bias-current compensation for non-inverting 
amplifier operated over large common mode 
range 

base current of the NPN. Further, since a silicon-planar PNP 
transistor has approximately the same current-gain versus 
temperature characteristic as the integrated transistors, an 
improvement in temperature drift will also be realized.'*' 
However, perfect compensation should not be expected be- 
cause of unit-to-unit variations in the temperature character- 
istics of both the PNP transistor and the integrated circuit. 
Although the circuit in Figure 3 works well for the summing 
amplifier connection, it does have limitations in other appli- 
cations. It could, for example, be used for the voltage follow- 
er configuration by connecting the base of the PNP to the 
non-inverting input. However, this would reduce the input 
t|f the operational amplifier uses a Darlington input stage, however, the drift 
compensation will not be nearly as good. 



impedance (to about 1 50 Mil) because the current supplied 
by the PNP will vary with the input voltage level. 
If this characteristic is objectionable, the more-complicated 
circuit shown in Figure 4 can be used. 
The emitter of the PNP transistor is fed from a current 
source so that the compensating current does not vary with 
input-voltage level. The design of the current source is such 
as to give it about the same characteristics as those on the 
input stage of the better monolithic amplifiers! to give clos- 
er compensation with changes in temperature and supply 
voltage. The circuit makes use of the emitter base voltage 
differential between two transistors operated at different 
collector currents. 1 > 2 Although it is recommended in the ref- 
erences that these transistors be well matched, it is not 
really necessary since the devices are operated at much 
different collector currents. 

Figure 5 shows another compensation scheme for the volt- 
age follower connection. This circuit is much simpler than 
that shown in Figure 4, but the temperature compensation is 
not quite as good. The compensating current is obtained 
through a resistor connected across a diode which is boot- 
strapped to the output. The diode acts as a regulator so that 
the compensating current does not change appreciably with 
signal level, giving input impedances about 1 000 MH. The 
negative temperature coefficient of the diode voltage also 
provides some temperature compensation. 




•Select for zero input current 



Figure 5. Voltage follower with bias-current compensa- 
tion 

All the circuits discussed thus far have been tailored for 
particular applications. Figure 6 shows a completely-general 
scheme wherein both inputs are current compensated over 
the full common mode range as well as against power sup- 
ply and temperature variations. This circuit is suitable for 
use either as a summing amplifier or as a non-inverting am- 
plifier. It is not required that the DC impedance seen by both 
inputs be equal, although lower drift can be expected if they 
are. 

As was mentioned earlier, all the bias compensation circuits 
require adjustment. With the circuits in Figures 1 and 2, this 
is merely a matter of adjusting the potentiometer for zero 
output with zero input. It is not so simple with the other 
circuits, however. For one, it is difficult to use potentiome- 
ters because a very wide range of resistance values are 
required to accommodate expected unit-to-unit variations. 
Resistor selection must therefore be used. Test circuits for 
selecting bias compensation resistors are given in Figure 7. 

rrhe709andtheLM101. 



rf 



•Select for zero input current on 
non-inverting input 
"Select for zero input current on 
inverting input 




TL/H/6925-6 

Figure 6. Bias-current compensation for differential in- 
puts 

offset voltage compensation 

The highly predictable behavior of the emitter-base voltage 
of transistors has suggested a unique drift compensation 
method; it is shown in Reference 3 that the offset voltage 
drift of a differential transistor pair can be reduced by about 
an order of magnitude by unbalancing the collector currents 
such that the initial offset voltage is zero. The basis for this 
comes from the equation for the emitter-base voltage differ- 
ential of two transistors operating at the same temperature: 



... kT l S 2 kT l C2 

AV BE = — log e : — log e p^ 

q 'si q 'ci 



(D 



where k is Boltzmann's constant, T is the absolute tempera- 
ture, q is the charge of an electron, Is is a constant which 
depends only on how the transistor is made and Iq is the 
collector current. This equation is derived in Reference 2. 



It is worthwhile noting here that these expressions make no 
assumptions about the current gain of the transistors. It is 
shown in References 5 and 6 that the emitter-base voltage 
is a function of collector current, not emitter current. There- 
fore, the balance will not be upset by base current (except 
for interaction with the DC source resistance). 
The first term in Equation (1) is the offset voltage of the two 
transistors for equal collector currents. It can be seen that 
this offset voltage is directly proportional to the absolute 
temperature-a fact which is substantiated by experiment. 4 
The second term is the change of offset voltage which aris- 
es from operating the transistors at unequal collector cur- 
rents. For a fixed ratio of collector currents, this is also pro- 
portional to absolute temperature. Hence, if the collector 
currents are unbalanced in a fixed ratio to give a zero emit- 
ter-base voltage differential, the temperature drift will also 
be zero. 

Experiment indicates that this is indeed true. Thermal drifts 
less than 1 00 juV over the - 55°C to + 1 25°C temperature 
range have been realized consistently. In order to obtain 
these low drifts, however, it is almost necessary to use a 
monolithic transistor pair, since a 0.05°C temperature differ- 
ential will give a 100 ju,V drift. With a monolithic pair, the 
physical proximity of the devices as well as the high thermal 
conductivity of silicon holds this differential to an absolute 
minimum. 

For low drift, the transistors must operate from a low 
enough source resistance that the voltage drop across the 
source due to base current (or base current differential if 
both bases see the same resistance) is insignificant. Fur- 
thermore, the transistors must be operated at a low enough 
collector current that the emitter-contact and base-spread- 
ing resistances are negligible, since Equation (1) assumes 
that they are zero. 

A complete amplifier using this principle is shown in Figure 
8. A monolithic transistor pair is used as a preamplifier for a 
conventional operational amplifier. A null potentiometer, 
which is set for zero output for zero input, unbalances the 
collector load resistors of the transistor pair such that the 
collector currents are unbalanced for zero offset. This gives 
minimum drift. An interesting feature of the circuit is that the 
performance is relatively unaffected by supply voltage varia- 
tions: a 1 V change in either supply causes an offset voltage 
change of about 1 juV. This happens because neither term 
in Equation (1) is affected by the magnitude of the collector 
currents. 




R1 
10M 




l> 


\ 


S i 











f * 




II II 






" II 

CI 
JL 100 pF 




C2 
30 pF 



Figure 7. Test circuits for selecting bias-compensation resistors 



CO 

z 

< 



R1 

ion 

1% 



i— VW— ♦ 



THERMOCOUPLE 




Figure 8. Example of a DC amplifier using the drift-compensation technique 



In order to get low drift, it is necessary that the gain of the 
preamplifier be high enough so that the drift of the opera- 
tional amplifier does not degrade performance. The gain 
can be determined from the expression for the transcon- 
ductance of the input transistors: 

ale = qjc 
3V BE kT 
The voltage gain is 

9VOUT 



(2) 



A V = 



3V| N 

sic 

3V BE 



R L 



(3) 



(4) 



where Rl is the average value of the two collector load 
resistors on the input stage and lc is the average of the two 
collector currents. 

Substituting Equation (2), this becomes 
QIcRl 



_ qVRL 
kT 
The input referred drift is then 

AVqs + Rl AIqs 



AV, N = 



A V 



(5) 



(6) 



(7) 



where AVos is the offset voltage drive of the operational 
amplifier and Alos is ite offset current drift. 
Using Equation (7), 

kT (AV s + RlAIqs) 



AV| N = 



qVRL 



(8) 



With the circuit shown in Figure 8, Equation (8) gives a 25 
jaV input-referred drift for every 1 mV of offset voltage drift 
or for every 100 nA of offset current drift. It is obvious from 
this that the offset current drift is most important if an opera- 
tional amplifier with bipolar input transistors is used. 
Another important consideration is the matching of the col- 
lector load resistors on the preamplifier stage. A 0.1 -percent 
imbalance in the load resistors due to thermal mismatches 
or any other cause will produce a 25 /xV shift in offset. This 
includes the balancing potentiometer which can introduce 
an error that will depend on how far it is set off midpoint if it 
has a different temperature coefficient than the resistors. 
The most obvious use of this type of low drift amplifier is 
with thermocouples, magnetometers, current shunts, wire 
strain gauges or similar signal sources where very low drift 
is required and the source resistance is low enough that the 
bias currents do not cause a problem. The 0.5 to 1 liV/°C 
drift* realized with this relatively simple amplifier over a 
-55°C to +125°C temperature range compares favorably 
with the drift figures achieved with chopper amplifiers: 0.4 
ju,V/°C for mechanical choppers, 0.5 ju.V/°C with photoelec- 
tric choppers over a 0°C to 55°C temperature range and 2 
fiV/°C with field-effect-transistor choppers over a -55°C to 
+ 1 25°C temperature range. In order to give some apprecia- 
tion of the level of performance, it is interesting to note that 
no substantial improvement in performance would be real- 
ized by operating the amplifier in a temperature-controlled 
oven. Any improvement would be masked by various ther- 
mo-electric effects not directly associated with the amplifier 
unless extreme care were taken in the choice of input lead 

•Drifts of 0.05 jliV/°C over a 0-50°C temperature range were reported in 
Reference 3 using matched discrete transistors in one can. 



material, the method of making connections and the balanc- 
ing of thermal paths. These factors are, in fact, important 
when making oven tests to verify the drift of the amplifier 
since thermoelectric effects can easily produce drift volt- 
ages larger than those of the amplifier if they are not proper- 
ly handled. 

summary 

A number of compensation circuits designed to increase the 
DC resolution of monolithic operational amplifiers have 
been presented. Both current compensation techniques for 
high impedance levels as well as methods of achieving 
chopper-stabilized drift performance at low impedance lev- 
els have been covered. 

Fairly-simple current compensation which requires that the 
impedance levels be fixed have been described along with 
compensation which is effective in cases where the source 
impedance is not well defined. This latter category includes 
long-interval integrators, sample-and-hold circuits, 
switched-gain amplifiers or voltage followers which operate 
from an unknown source. The application of these schemes 
is generally limited to integrated amplifiers since modular 
amplifiers almost always incorporate current compensation. 
The drift-reduction techniques provide stabilities better than 
0.5 ju,V/°C for low impedance sources, such as thermocou- 
ples, current shunts or strain gauges. With a properly de- 
signed circuit, compensation depends only on a single room 
temperature adjustment, so excellent performance can be 
obtained from a fairly-simple amplifier. 



references 

1 . R. J. Widlar, "A Unique Circuit Design for a High Perform- 
ance Operational Amplifier Especially Suited to Monolith- 
ic Construction," Proa of NEC, Vol. XXI, pp. 85-89, Octo- 
ber, 1965. 

2. R. J. Widlar, "Some Circuit Design Techniques for Linear 
Integrated Circuits," IEEE Trans, on Circuit Theory, Vol. 
XII, pp. 586-590, December, 1965. 

3. A. H. Hoffait and R. D. Thorton, "Limitations of Transistor 
DC Amplifiers," IEEE Proc, Vol. 52, pp. 179-184, Febru- 
ary, 1964. 

4. A. Tuszynski, "Correlation Between the Base-Emitter 
Voltage and Its Temperature Coefficient," Solid State De- 
sign, pp. 32-35, July, 1962. 

5. C. T. Sah, "Effect of Surface Recombination and Channel 
on P-N Junction and Transistor Characteristics," IRE 
Trans, on Electron Devices, Vol. ED-9, pp. 94-108, Janu- 
ary, 1962. 

6. J. E. Iwersen, A. R. Bray, and J. J. Kleimack, "Low-Cur- 
rent Alpha in Silicon Transistors," IRE Trans, on Electron 
Devices, Vol. ED-9, pp. 474-478, November, 1962. 



> 
Z 
w 



Monolithic Op Amp — The 
Universal Linear 
Component 



Robert J. Widlar 
Apartado Postal 541 
Puerto Vallarta, Jalisco 
Mexico 



National Semiconductor 
Application Note 4 




introduction 

Operational amplifiers are undoubtedly the easiest and best 
way of performing a wide range of linear functions from sim- 
ple amplification to complex analog computation. The cost 
of monolithic amplifiers is now less than $2.00, in large 
quantities, which makes it attractive to design them into cir- 
cuits where they would not otherwise be considered. Yet 
low cost is not the only attraction of monolithic amplifiers. 
Since all components are simultaneously fabricated on one 
chip, much higher circuit complexities than can be used with 
discrete amplifiers are economical. This can be used to give 
improved performance. Further, there are no insurmount- 
able technical difficulties to temperature stabilizing the am- 
plifier chip, giving chopper-stabilized performance with little 
added cost. 

Operational amplifiers are designed for high gain, low offset 
voltage and low input current. As a result, dc biasing is con- 
siderably simplified in most applications; and they can be 
used with fairly simple design rules because many potential 
error terms can be neglected. This article will give examples 
demonstrating the range of usefulness of operational ampli- 
fiers in linear circuit design. The examples are certainly not 
all-inclusive, and it is hoped that they will stimulate even 
more ideas from others. A few practical hints on preventing 
oscillations in operational amplifiers will also be given since 
this is probably the largest single problem that many engi- 
neers have with these devices. 

Although the designs presented use the LM101 operational 
amplifier and the LM102 voltage follower produced by Na- 
tional Semiconductor, most are generally applicable to all 
monolithic devices if the manufacturer's recommended fre- 
quency compensation is used and differences in maximum 
ratings are taken into account. A complete description of 
the LM101 is given elsewhere; 1 but, briefly, it differs from 
most other monolithic amplifiers, such as the LM709 , 2 in 
that it has a ± 30V differential input voltage range, a + 1 5V, 
- 1 2V common mode range with + 1 5V supplies and it can 
be compensated with a single 30 pF capacitor. The 
LM 102,3 which is also used here, is designed specifically as 
a voltage follower and features a maximum input current of 
10 nA and a 10 Wjas slew rate. 

operational-amplifier oscillator 

The free-running multivibrator shown in Figure 1 is an excel- 
lent example of an application where one does not normally 
consider using an operational amplifier. However, this circuit 
operates at low frequencies with relatively small capacitors 
because it can use a longer portion of the capacitor time 
constant since the threshold point of the operational amplifi- 
er is well determined. In addition, it has a completely-sym- 
metrical output waveform along with a buffered output, al- 
though the symmetry can be varied by returning R2 to some 
voltage other than ground. 




Chosen for oscillation at 100 Hz. 



TL/H/7357-1 

Figure 1. Free-running multivibrator 

Another advantage of the circuit is that it will always self 
start and cannot hang up since there is more dc negative 
feedback than positive feedback. This can be a problem 
with many "textbook" multivibrators. 
Since the operational amplifier is used open loop, the usual 
frequency compensation components are not required 
since they will only slow it down. But even without the 30 pF 
capacitor, the LM101 does have speed limitations which re- 
strict the use of this circuit to frequencies below about 2 
kHz. 

The large input voltage range of the LM101 (both differential 
and single ended) permits large voltage swings on the input 
so that several time constants of the timing capacitor, C1, 
can be used. With most other amplifiers, R2 must be re- 
duced to keep from exceeding these ratings, which requires 
that C1 be increased. Nonetheless, even when large values 
are needed for C1, smaller polarized capacitors may be 
used by returning them to the positive supply voltage in- 
stead of ground. 

level shifting amplifier 

Frequently, in the design of linear equipment, it is necessary 
to take a voltage which is referred to some dc level and 
produce an amplified output which is referred to ground. 
The most straight-forward way of doing this is to use a dif- 
ferential amplifier similar to that shown in Figure 2a. This 
circuit, however, has the disadvantages that the signal 
source is loaded by current from the input divider, R3 and 
R4, and that the feedback resistors must be very well 
matched to prevent erroneous outputs from the common 
mode input signal. 



A circuit which does not have these problems is shown in 
Figure 2b. Here, an FET transistor on the output of the oper- 
ational amplifier produces a voltage drop across the feed- 
back resistor, R1, which is equal to the input voltage. The 
voltage across R2 will then be equal to the input voltage 
multiplied by the ratio, R2/R1 ; and the common mode rejec- 
tion will be as good as the basic rejection of the amplifier, 
independent of the resistor tolerances. This voltage is buff- 
ered by an LM102 voltage follower to give a low impedance 
output. 

An advantage of the LM101 in this circuit is that it will work 
with input voltages up to its positive supply voltages as long 
as the supplies are less than ± 1 5V. 

voltage comparators 

The LM101 is well suited to comparator applications for two 
reasons: first, it has a large differential input voltage range 
and, second, the output is easily clamped to make it com- 
patible with various driver and logic circuits. It is true that it 
doesn't have the speed of the LM710 4 (10 fis versus 40 ns, 
under equivalent conditions); however, in many linear appli- 
cations speed is not a problem and the lower input currents 
along with higher voltage capability of the LM101 is a tre- 
mendous benefit. 

Two comparator circuits using the LM101 are shown in Fig- 
ure 3. The one in Figure 3a shows a clamping scheme 



which makes the output signal directly compatible with DTL 
or TTL integrated circuits. An LM103 breakdown diode 
clamps the output at 0V or 4V in the low or high states, 
respectively. This particular diode was chosen because it 
has a sharp breakdown and low equivalent capacitance. 
When working as a comparator, the amplifier operates open 
loop so normally no frequency compensation is needed. 
Nonetheless, the stray capacitance between Pins 5 and 6 of 
the amplifier should be minimized to prevent low level oscil- 
lations when the comparator is in the active region. If this 
becomes a problem a 3 pF capacitor on the normal com- 
pensation terminals will eliminate it. 
Figure 3b shows the connection of the LM101 as a compar- 
ator and lamp driver. Q1 switches the lamp, with R2 limiting 
the current surge resulting from turning on a cold lamp. R1 
determines the base drive to Q1 while D1 keeps the amplifi- 
er from putting excessive reverse bias on the emitter-base 
junction of Q1 when it turns off. 

more output current swing 

Because almost all monolithic amplifiers use class-B output 
stages, they have good loaded output voltage swings, deliv- 
ering ± 10V at 5 mA with ± 15V supplies. Demanding much 
more current from the integrated circuit would require, for 
one, that the output transistors be made considerably larg- 



INPUT 




OUTPUT 



TL/H/7357-2 



a. standard differential amplifier 




b. level-isolation amplifier 
Figure 2. Level-shifting amplifiers 



+28V 





Vref 



TL/H/7357-5 



a. comparator for driving DTL and 
TTL integrated circuits 

Figure 3. Voltage comparator circuits 



b. comparator and lamp driver 




TL/H/7357-6 

Figure 4. High current output buffer 

er. In addition, the increased dissipation could give rise to 
troublesome thermal gradients on the chip as well as exces- 
sive package heating in high-temperature applications. It is 
therefore advisable to use an external buffer when large 
output currents are needed. 

A simple way of accomplishing this is shown in Figure 4. A 
pair of complementary transistors are used on the output of 
the LM101 to get the increased current swing. Although this 
circuit does have a dead zone, it can be neglected at fre- 
quencies below 100 Hz because of the high gain of the 
amplifier. R1 is included to eliminate parasitic oscillations 
from the output transistors. In addition, adequate bypassing 
should be used on the collectors of the output transistors to 
insure that the output signal is not coupled back into the 
amplifier. This circuit does not have current limiting, but it 
can be added by putting 50H resistors in series with the 
collectors of Q1 and Q2. 

an f et amplifier 

For ambient temperatures less than about 70°C, junction 
field effect transistors can give exceptionally low input cur- 
rents when they are used on the input stage of an opera- 
tional amplifier. However, monolithic FET amplifiers are not 
now available since it is no simple matter to diffuse high 
quality FET's on the same chip as the amplifier. Nonethe- 
less, it is possible to make a good FET amplifier using a 
discrete FET pair in conjunction with a monolithic circuit. 



Such a circuit is illustrated in Figure 5. A matched FET pair, 
connected as source followers, is put in front of an integrat- 
ed operational amplifier. The composite circuit has roughly 
the same gain as the integrated circuit by itself and is com- 
pensated for unity gain with a 30 pF capacitor as shown. 
Although it works well as a summing amplifier, the circuit 
leaves something to be desired in applications requiring 
high common mode rejection. This happens both because 
resistors are used for current sources and because the 
FET's by themself do not have good common mode rejec- 
tion. 

■ 16V 




OUTPUT 



TL/H/7357-7 

Figure 5. FET operational amplifier 

storage circuits 

A sample-and-hold circuit which combines the low input cur- 
rent of FET's with the low offset voltage of monolithic ampli- 
fiers is shown in Figure 6. The circuit is a unity gain amplifier 
employing an operational amplifier and an FET source fol- 
lower. In operation, when the sample switch, Q2, is turned 
on, it closes the feedback loop to make the output equal to 
the input, differing only by the offset voltage of the LM101. 
When the switch is opened, the charge stored on C2 holds 
the output at a level equal to the last value of the input 
voltage. 

Some care must be taken in the selection of the holding 
capacitor. Certain types, including paper and mylar, exhibit a 
polarization phenomenon which causes the sampled volt- 



Qt 
2N3456 




C2* 
1 0.1 //F 



•Polycarbonate-dielectric capacitor 

TL/H/7357-8 



Figure 6. Low drift sample and hold 



age to drop off by about 50 mV, and then stabilize, when the 
capacitor is exercised over a 5V range during the sample 
interval. This drop off has a time constant in the order of 
seconds. The effect, however, can be minimized by using 
capacitors with teflon, polyethylene, glass or polycarbonate 
dielectrics. 

Although this circuit does not have a particularly low output 
resistance, fixed loads do not upset the accuracy since the 
loading is automatically compensated for during the sample 
interval. However, if the load is expected to change after 
sampling, a buffer such as the LM102 must be added be- 
tween the FET and the output. 

A second pole is introduced into the loop response of the 
amplifier by the switch resistance and the holding capacitor, 
C2. This can cause problems with overshoot or oscillation if 
it is not compensated for by adding a resistor, R1, in series 
with the LM101 compensation capacitor such that the 
breakpoint of the R1C1 combination is roughly equal to that 
of the switch and the holding capacitor. 
It is possible to use an MOS transistor for Q1 without worry- 
ing about the threshold stability. The threshold voltage is 
balanced out during every sample interval so only the short- 
term threshold stability is important. When MOS transistors 
are used along with mechanical switches, drift rates less 
than 10 mV/min can be realized. 

Additional features of the circuit are that the amplifier acts 
as a buffer so that the circuit does not load the input signal. 




• C2 

' 0.01 nf 



TL/H/7357-! 

Figure 7. Positive peak detector with buffered output 



Further, gain can also be provided by feeding back to the 
inverting input of the LM101 through a resistive divider in- 
stead of directly. 

The peak detector in Figure 7 is similar in many respects to 
the sample-and-hold circuit. A diode is used in place of the 
sampling switch. Connected as shown, it will conduct when- 
ever the input is greater than the output, so the output will 
be equal to the peak value of the input voltage. In this case, 
an LM102 is used as a buffer for the storage capacitor, 
giving low drift along with a low output resistance. 
As with the sample and hold, the differential input voltage 
range of the LM101 permits differences between the input 
and output voltages when the circuit is holding. 

non-linear amplifiers 

When a non-linear transfer function is needed from an oper- 
ational amplifier, many methods of obtaining it present 
themself. However, they usually require diodes and are 
therefore difficult to temperature compensate for accurate 
breakpoints. One way of getting around this is to make the 
output swing so large that the diode threshold is negligible 
by comparison, but this is not always practical. 
A method of producing very sharp, temperature-stable 
breakpoints in the transfer function of an operational amplifi- 
er is shown in Figure 8. For small input signals, the gain is 
determined by R1 and R2. Both Q2 and Q3 are conducting 
to some degree, but they do not affect the gain because 
their current gain is high and they do not feed any apprecia- 
ble current back into the summing mode. When the output 
voltage rises to 2V (determined by R3, R4 and V~), Q3 
draws enough current to saturate, connecting R4 in parallel 
with R2. This cuts the gain in half. Similarly, when the output 
voltage rises to 4V, Q2 will saturate, again halving the gain. 
Temperature compensation is achieved in this circuit by in- 
cluding Q1 and Q4. Q4 compensates the emitter-base volt- 
age of Q2 and Q3 to keep the voltage across the feedback 
resistors, R4 and R6, very nearly equal to the output voltage 
while Q1 compensates for the emitter base voltage of these 
transistors as they go into saturation, making the voltage 
across R3 and R5 equal to the negative supply voltage. A 
detrimental effect of Q4 is that it causes the output resist- 
ance of the amplifier to increase at high output levels. It may 
therefore be necessary to use an output buffer if the circuit 
must drive an appreciable load. 

servo preamplifier 

In certain servo systems, it is desirable to get the rate signal 
required for loop stability from some sort of electrical, lead 
network. This can, for example, be accomplished with reac- 
tive elements in the feedback network of the servo pream- 
plifier. 



R5 Q2 

187.5K 2N2605 



W>r 



V -=-15V 




TL/H/7357-10 



Figure 8. Nonlinear operational amplifier with temperature-compensated breakpoints 



Many saturating servo amplifiers operate over an extremely 
wide dynamic range. For example, the maximum error signal 
could easily be 1000 times the signal required to saturate 
the system. Cases like this create problems with electrical 
rate networks because they cannot be placed in any part of 
the system which saturates. If the signal into the rate net- 
work saturates, a rate signal will only be developed over a 
narrow range of system operation; and instability will result 
when the error becomes large. Attempts to place the rate 
networks in front of the error amplifier or make the error 
amplifier linear over the entire range of error signals fre- 
quently gives rise to excessive dc error from signal attenua- 
tion. 

These problems can be largely overcome using the kind of 
circuit shown in Figure 9. This amplifier operates in the lin- 
ear mode until the output voltage reaches approximately 3V 
with 30 juA output current from the solar cell sensors. At this 
point the breakdown diodes in the feedback loop begin to 
conduct, drastically reducing the gain. However, a rate sig- 




30 pF 



TL/H/7357-11 

Figure 9. Saturating servo preamplifier with rate feed- 
back 



nal will still be developed because current is being fed back 
into the rate network (R1, R2 and C1) just as it would if the 
amplifier had remained in the linear operating region. In fact, 
the amplifier will not actually saturate until the error current 
reaches 6 mA, which would be the same as having a linear 
amplifier with a ± 600V output swing. 

computing circuits 

In analog computation it is a relatively simple matter to per- 
form such operations as addition, subtraction, integration 
and differentiation by incorporating the proper resistors and 
capacitors in the feedback circuit of an amplifier. Many of 
these circuits are described in reference 5. Multiplication 
and division, however, are a bit more difficult. These opera- 
tions are usually performed by taking the logarithms of the 
quantities, adding or subtracting as required and then taking 
the antilog. 

At first glance, it might appear that obtaining the log of a 
voltage is difficult; but it has been shown 6 that the emitter- 
base voltage of a silicon transistor follows the log of its col- 
lector current over as many as nine decades. This means 
that common transistors can be used to perform the log and 
antilog operations. 

A circuit which performs both multiplication and division in 
this fashion is shown in Figure 10. It gives an output which is 
proportional to the product of two inputs divided by a third, 
and it is about the same complexity as a divider alone. 
The circuit consists of three log converters and an antilog 
generator. Log converters similar to these have been de- 
scribed elsewhere, 7 but a brief description follows. Taking 
amplifier A1 , a logging transistor, Q1 , is inserted in the feed- 
back loop such that its collector current is equal to the input 
voltage divided by the input resistor, R1. Hence, the emitter- 
base voltage of Q1 will vary as the log of the input voltage 
E1. 

A2 is a similar amplifier operating with logging transistor, 
Q2. The emitter-base junctions of Q1 and Q2 are connected 
in series, adding the log voltages. The third log converter 
produces the log of E3. This is series-connected with the 
antilog transistor, Q4; and the combination is hooked in par- 



10 



A 




R13 
10K 



R1I 

10K 




•£0UT 



E,E 2 



30 pF 



A 



03 
'1N457 




*tLM394 



TL/H/7357-12 



Figure 10. Analog multiplier/divider 



allel with the output of the other two log convenors. There- 
fore, the emitter-base of Q4 will see the log of E3 subtracted 
from the sum of the logs of E1 and E2. Since the collector 
current of a transistor varies as the exponent of the emitter- 
base voltage, the collector current of Q4 will be proportional 
to the product of E1 and E2 divided by E3. This current is 
fed to the summing amplifier, A4, giving the desired output. 
This circuit can give 1 -percent accuracy for input voltages 
from 500 mV to 50V. To get this precision at lower input 
voltages, the offset of the amplifiers handling them must be 
individually balanced out. The zener diode, 04, increases 
the the collector-base voltage across the logging transistors 
to improve high current operation. It is not needed, and is in 
fact undesirable, when these transistors are running at cur- 
rents less than 0.3 mA. At currents above 0.3 mA, the lead 
resistances of the transistors can become important (0.25ft 
is 1 -percent at 1 mA) so the transistors should be installed 
with short leads and no sockets. 

An important feature of this circuit is that its operation is 
independent of temperature because the scale factor 
change in the log converter with temperature is compensat- 
ed by an equal change in the scale factor of the antilog 
generator. It is only required that Q1, Q2, Q3 and Q4 be at 
the same temperature. Dual transistors should be used and 
arranged as shown in the figure so that thermal mismatches 



between cans appear as inaccuracies in scale factor (0.3- 
percent/°C) rather than a balance error (8-percent/°C). R12 
is a balance potentiometer which nulls out the offset volt- 
ages of all the logging transistors. It is adjusted by setting all 
input voltages equal to 2V and adjusting for a 2V output 
voltage. 

The logging transistors provide a gain which is dependent 
on their operating level, which complicates frequency com- 
pensation. Resistors (R3, R6 and R7) are put in the amplifier 
output to limit the maximum loop gain, and the compensa- 
tion capacitor is chosen to correspond with this gain. As a 
result, the amplifiers are not especially designed for speed, 
but techniques for optimizing this parameter are given in 
reference 6. 

Finally, clamp diodes D1 through D3, prevent exceeding the 
maximum reverse emitter-base voltage of the logging tran- 
sistors with negative inputs. 

root extractor* 

Taking the root of a number using log converters is a fairly 
simple matter. All that is needed is to take the log of a 
voltage, divide it by, say 1 / 2 for the square root, and then 
'The "extraction" used here doubtless has origin in the dental operation 
most of us would fear less than having to find even a square root without 
tables or other aids. 



11 





TL/H/7357-14 



a. measuring loop gain 



Figure 12. Illustrating loop gain 



10 100 IK 10K 100K 1M 10M 
FREQUENCY -Hz 

TL/H/7357-15 

b. typical response 



take the antilog. A circuit which accomplishes this is shown 
in Figure 1 1. A1 and Q1 form the log converter for the input 
signal. This feeds Q2 which produces a level shift to give 
zero voltage into the R4, R5 divider for a 1V input. This 
divider reduces the log voltage by the ratio for the root de- 
sired and drives the buffer amplifier, A2. A2 has a second 
level shifting diode, Q3, its feedback network which gives 
the output voltage needed to get a 1V output from the anti- 
log generator, consisting of A3 and Q4, with a unity input. 
The offset voltages of the transistors are nulled out by im- 
balancing R6 and R8 to give 1V output for 1 V input, since 
any root of one is one. 

Q2 and Q3 are connected as diodes in order to simplify the 
circuitry. This doesn't introduce problems because both op- 
erate over a very limited current range, and it is really only 
required that they match. R7 is a gain-compensating resis- 
tor which keeps the currents in Q2 and Q3 equal with 
changes in signal level. 

As with the multiplier/divider, the circuit is insensitive to 
temperature as long as all the transistors are at the same 
temperature. Using transistor pairs and matching them as 
shown minimizes the effects of gradients. 
The circuit has 1 -percent accuracy for input voltages be- 
tween 0.5 and 50V. For lower input voltages, A1 and A3 
must have their offsets balanced out individually. 

frequency compensation hints 

The ease of designing with operational amplifiers some- 
times obscures some of the rules which must be followed 
with any feedback amplifier to keep it from oscillating. In 
general, these problems stem from stray capacitance, ex- 
cessive capacitive loading, inadequate supply bypassing or 
improper frequency compensation. 
In frequency compensating an operational amplifier, it is 
best to follow the manufacturer's recommendations. How- 
ever, if operating speed and frequency response is not a 
consideration, a greater stability margin can usually be ob- 
tained by increasing the size of the compensation capaci- 
tors. For example, replacing the 30 pF compensation ca- 
pacitor on the LM101 with a 300 pF capacitor will make it 
ten times less susceptible to oscillation problems in the uni- 
ty-gain connection. Similarly, on the LM709, using 0.05 ju,F, 
1.5 kfi, 2000 pF and 51 to components instead of 5000 pF, 
1.5 kft, 200 pF and 51 fl will give 20 dB more stability mar- 
gin. Capacitor values less than those specified by the manu- 
facturer for a particular gain connection should not be used 
since they will make the amplifier more sensitive to strays 



and capacitive loading, or the circuit can even oscillate with 
worst-case units. 

The basic requirement for frequency compensating a feed- 
back amplifier is to keep the frequency roll-off of the loop 
gain from exceeding 12 dB/octave when it goes through 
unity gain. Figure 12a shows what is meant by loop gain. 
The feedback loop is broken at the output, and the input 
sources are replaced by their equivalent impedance. Then 
the response is measured such that the feedback network 
is included. 

Figure 12b gives typical responses for both uncompensated 
and compensated amplifiers. An uncompensated amplifier 
generally rolls off at 6 dB/octave, then 12 dB/octave and 
even 18 dB/octave as various frequency-limiting effects 
within the amplifier come into play. If a loop with this kind of 
response were closed, it would oscillate. Frequency com- 
pensation causes the gain to roll off at a uniform 6 dB/oc- 
tave right down through unity gain. This allows some margin 
for excess rolloff in the external circuitry. 
Some of the external influences which can affect the stabili- 
ty of an operational amplifier are shown in Figure 13. One is 
the load capacitance which can come from wiring, cables or 
an actual capacitor on the output. This capacitance works 
against the output impedance of the amplifier to attenuate 
high frequencies. If this added rolloff occurs before the loop 
gain goes through zero, it can cause instability. It should be 
remembered that this single rolloff point can give more than 
6 dB/octave rolloff since the output impedance of the ampli- 
fier can be increasing with frequency. 




TL/H/7357-16 

Figure 13. External capacitances that affect stability 



13 



A second source of excess rolloff is stray capacitance on 
the inverting input. This becomes extremely important with 
large feedback resistors as might be used with an FET-input 
amplifier. A relatively simple method of compensating for 
this stray capacitance is shown in Figure 14: a lead capaci- 
tor, C1, put across the feedback resistor. Ideally, the ratio of 
the stray capacitance to the lead capacitor should be equal 
to the closed-loop gain of the amplifier. However, the lead 
capacitor can be made larger as long as the amplifier is 
compensated for unity gain. The only disadvantage of doing 
this is that it will reduce the bandwidth of the amplifier. Os- 
cillations can also result if there is a large resistance on the 
non-inverting input of the amplifier. The differential input im- 
pedance of the amplifier falls off at high frequencies (espe- 
cially with bipolar input transistors) so this resistor can pro- 
duce troublesome rolloff if it is much greater than 1 0K, with 
most amplifiers. This is easily corrected by bypassing the 
resistor to ground. 

When the capacitive load on an integrated amplifier is much 
greater than 100 pF, some consideration must be given to 
its effect on stability. Even though the amplifier does not 
oscillate readily, there may be a worst-case set of condi- 
tions under which it will. However, the amplifier can be stabi- 
lized for any value of capacitive loading using the circuit 
ci 




TL/H/7357-17 

Figure 14. Compensating stray input capacitance 

shown in Figure 15. The capacitive load is isolated from the 
output of the amplifier with R4 which has a value of 50ft to 
10011 for both the LM101 and the LM709. At high frequen- 
cies, the feedback path is through the lead capacitor, C1 , so 
that the lag produced by the load capacitance does not 




ElN"""^^^ 



TL/H/7357-18 

Figure 15. Compensating for very large capacitive loads 



cause instability. To use this circuit, the amplifier must be 
compensated for unity gain, regardless of the closed loop 
dc gain. The value of C1 is not too important, but at a mini- 
mum its capacitive reactance should be one-tenth the re- 
sistance of R2 at the unity-gain crossover frequency of the 
amplifier. 

When an operational amplifier is operated open loop, it 
might appear at first glance that it needs no frequency com- 
pensation. However, this is not always the case because 
the external compensation is sometimes required to stabi- 
lize internal feedback loops. 

The LM101 will not oscillate when operated open loop, al- 
though there may be problems if the capacitance between 
the balance terminal on pin 5 and the output is not held to 
an absolute minimum. Feedback between these two points 
is regenerative if it is not balanced out with a larger feed- 
back capacitance across the compensation terminals. Usu- 
ally a 3 pF compensation capacitor will completely eliminate 
the problem. The LM709 will oscillate when operated open 
loop unless a 1 pF capacitor is connected across the input 
compensation terminals and a 3 pF capacitor is connected 
on the output compensation terminals. 
Problems encountered with supply bypassing are insidious 
in that they will hardly ever show up in a Nyquist plot. This 
problem has not really been thoroughly investigated, proba- 
bly because one sure cure is known: bypass the positive 
and negative supply terminals of each amplifier to ground 
with at least a 0.01 ju.F capacitor. 

For example, a LM101 can take over 1 mH inductance in 
either supply lead without oscillation. This should not sug- 
gest that they should be run without bypass capacitors. It 
has been established that 100 LM101's on a single printed 
circuit board with common supply busses will oscillate if the 
supplies are not bypassed about every fifth device. This 
happens even though the inputs and outputs are completely 
isolated. 

The LM709, on the other hand, will oscillate under many 
load conditions with as little as 18 inches of wire between 
the negative supply lead and a bypass capacitor. Therefore, 
it is almost essential to have a set of bypass capacitors for 
every device. 

Operational amplifiers are specified for power supply rejec- 
tion at frequencies less than the first break frequency of the 
open loop gain. At higher frequencies, the rejection can be 
reduced depending on how the amplifier is frequency com- 
pensated. For both the LM101 and LM709, the rejection of 
high frequency signals on the positive supply is excellent. 
However, the situation is different for the negative supplies. 
These two amplifiers have compensation capacitors from 
the output down to a signal point which is referred to the 
negative supply, causing the high frequency rejection for the 
negative supply to be much reduced. It is therefore impor- 
tant to have sufficient bypassing on the negative supply to 
remove transients if they can cause trouble appearing on 
the output. One fairly large (22 ju,F) tantalum capacitor on 
the negative power lead for each printed-circuit card is usu- 
ally enough to solve potential problems. 
When high-current buffers are used in conjunction with op- 
erational amplifiers, supply bypassing and decoupling are 
even more important since they can feed a considerable 
amount of signal back into the supply lines. For reference, 
bypass capacitors of at least 0.1 ju.F are required for a 
50 mA buffer. 

When emitter followers are used to drive long cables, addi- 
tional precautions are required. An emitter follower by it- 



14 



self— which is not contained in a feedback loop — will fre- 
quently oscillate when connected to a long length of cable. 
When an emitter follower is connected to the output of an 
operational amplifier, it can produce oscillations that will 
persist no matter how the loop gain is compensated. An 
analysis of why this happens is not very enlightening, so 
suffice it to say that these oscillations can usually be elimi- 
nated by putting a ferrite bead 8 between the emitter follower 
and the cable. 

Considering the loop gain of an amplifier is a valuable tool in 
understanding the influence of various factors on the stabili- 
ty of feedback amplifiers. But it is not too helpful in deter- 
mining if the amplifier is indeed stable. The reason is that 
most problems in a well-designed system are caused by 
secondary effects — which occur only under certain condi- 
tions of output voltage, load current, capacitive loading, 
temperature, etc. Making frequency-phase plots under all 
these conditions would require unreasonable amounts of 
time, so it is invariably not done. 

A better check on stability is the small-signal transient re- 
sponse. It can be shown mathematically that the transient 
response of a network has a one-for-one correspondence 
with the frequency domain response, t The advantage of 
transient response tests is that they are displayed instanta- 
neously on an oscilloscope, so it is reasonable to test a 
circuit under a wide range of conditions. 
Exact methods of analysis using transient response will not 
be presented here. This is not because these methods are 
difficult, although they are. Instead, it is because it is very 
easy to determine which conditions are unfavorable from 
the overshoot and ringing on the step response. The stabili- 
ty margin can be determined much more easily by how 
much greater the aggravating conditions can be made be- 
fore the circuit oscillates than by analysis of the response 
under given conditions. A little practice with this technique 
can quickly yield much better results than classical methods 
even for the inexperienced engineer. 

summary 

A number of circuits using operational amplifiers have been 
proposed to show their versatility in circuit design. These 
have ranged from low frequency oscillators through circuits 
for complex analog computation. Because of the low cost of 



monolithic amplifiers, it is almost foolish to design dc ampli- 
fiers without integrated circuits. Moreover, the price makes it 
practical to take advantage of operational-amplifier perform- 
ance in a variety of circuits where they are not normally 
used. 

Many of the potential oscillation problems that can be en- 
countered in both discrete and integrated operational ampli- 
fiers were described, and some conservative solutions to 
these problems were presented. The areas discussed in- 
cluded stray capacitance, capacitive loading and supply by- 
passing. Finally, a simplified method of quickly testing the 
stability of amplifier circuits over a wide range of operating 
conditions was suggested. 

The frequency-domain characteristics can be determined from the impulse 
response of a network and this is directly relatable to the step response 
through the convolution integral. 

references 

1. R. J. Widlar, "Monolithic Op Amp with Simplified Frequen- 
cy Compensation", EEE, Vol. 15, No. 7, pp. 58-63, July, 
1967. 

2. R. J. Widlar, "A Unique Circuit Design for a High Perform- 
ance Operational Amplifier Especially Suited to Monolith- 
ic Construction", Proc. of NEC, Vol. XXI, pp. 85-89, Octo- 
ber, 1965. 

3. R. J. Widlar, "A Fast Integrated Voltage Follower with 
Low Input Current", National Semiconductor AN-5, 
March, 1968. 

4. R. J. Widlar, "The Operation and Use of a Fast Integrated 
Circuit Comparator", Fairchild Semiconductor APP- 11 6, 
February, 1966. 

5. "Handbook of Operational Amplifier Applications", Burr- 
Brown Research Corporation, Tucson, Arizona. 

6. J. F. Gibbons and H. S. Horn, "A Circuit with Logarithmic 
Transfer Response over Nine Decades", IEEE Trans, on 
Circuit Theory, Vol. CT-11, pp. 378-384, September, 
1964. 

7. R. J. Widlar and J. N. Giles, "Avoid Over-Integration", 
Electronic Design, Vol. 14, No. 3, pp. 56-62, Feb. 1. 1966. 

8. Leslie Solomon, "Ferrite Beads", Electronics World, pp. 
42-43, October, 1966. 



15 



Application of the LH0002 
Current Amplifier 



INTRODUCTION 

The LH0002 Current Amplifier integrated building block pro- 
vides a wide band unity gain amplifier capable of providing 
peak currents of up to ± 200 mA into a 50ft load. 
The circuit uses thick film technology to integrate 2 NPN 
and 2 PNP complementary matched silicon transistors with 
4 cermet resistors on a single alumina ceramic substrate. A 
circuit schematic is shown in Figure 1. The negative thermal 
feedback provided by the close proximity of the compo- 
nents on a single substrate eliminates any thermal runaway 
problem that could occur if this circuit were constructed us- 
ing discrete components. 

A typical circuit features a dynamic input impedance of 
200 kft, an output impedance of 6ft, DC to 50 MHz band- 
width, and an output voltage swing that approaches supply 
voltage. A complete list of the guaranteed and typical values 
for the electrical characteristics under the stated conditions 
is given in Table I. These features make the LH0002 ideal 
for integration with an operational amplifier inside a closed 
loop configuration to increase its current output. The sym- 
metrical class AB output portion of the circuit also provides 
a constant low output impedance for both the positive and 
negative slopes of output pulses. 

CIRCUIT OPERATION 

The majority of circuit applications will use symmetrical pow- 
er supplies, with equal positive voltage being applied to pins 
1 and 2, and equal negative voltage applied to pins 6 and 7. 



National Semiconductor 
Application Note 13 



a 



INPUT 8- 




TL/K/7315-1 



FIGURE 1. Circuit Schematic 



TABLE I. Electrical characteristics, specification applies for Ta = 2S°C 
with + 12.0V on pins 1 and 2; - 12.0V on pins 6 and 7. 



Parameters 


Conditions 


Min 


Typ 


Max 


Units 


Voltage Gain 


R s = 10 kft, R L = 1.0 kft 
V| N = 3.0 V pp , f = 1.0 kHz 
T A = 55°Cto125°C 


0.95 


0.97 






Input Impedance 


R s = 200kft,V, N = 1.0V rms , 
f = 1 .0 kHz, R L = 1 .0 kft 


180 


200 


— 


kft 


Output Impedance 


V| N = 10V rms ,f = 1.0 kHz 
R L = 50ft, R s = 10 kft 


— 


6 


10 


ft 


Output Voltage Swing 


R L = 1.0 kft, f = 1.0 kHz 


±10 


±11 


— 


V 


DC Input Offset Voltage 


R s = 10 kft, R L = 1-0 kft 
T A = -SS-Cto^-C 


— 


±40 


±100 


mV 


DC Input Offset Current 


R S = 10 kft, R L = 1.0 kft 
T A = -55°Cto125°C 


— 


±6.0 


±10 


fiA 


Harmonic Distortion 


V| N = 5.0V rms ,f = 1.0 kHz 


— 


0.1 


— 


% 


Bandwidth 


V| N = 1.0 V rms ,R L = 50ft 
R S = 100ft 


30 


50 


— 


MHz 


Positive Supply Current 


R s = 10 kft, R L = 1 kft 


— 


+ 6.0 


+ 10.0 


mA 


Negative Supply Current 


R s = 10 kft, R L = 1 kft 


— 


-6.0 


-10.0 


mA 



16 



The reason that pin 2 and pin 6 are not connected internally 
to pin 1 and pin 7, respectively, is to increase the versatility 
of circuit operation by allowing a decreased voltage to be 
applied to pins 2 and 6 to minimize the power dissipation in 
Q3 and Q4. The larger voltage applied to the input stage 
also provides increased current drive as required to the out- 
put stage. 

The operation of the circuit can be understood by consider- 
ing that the input pin 8 is at V|n- The emitter of Q1 will be 
approximately 0.6V more positive than V t N at 25°C, and the 
converse is true for Q2. This 0.6V will provide a forward bias 
on Q3 to cancel out the Q1 base to emitter drop which in 
turn would provide Vin at the output if all junctions, resistors, 
power supplies, etc., were electrically identical. The greatest 
error is introduced because the forward drops in the base- 
emitter junctions for the NPN and PNP devices are slightly 
different. For example, the Vbe of the NPN will be typically 
0.6V and the Vbe of the PNP will be typically 0.64V under 
the same conditions of lc = 2.4 mA at Vce = 12.0V at 
25°C. These are the approximate input stage circuit condi- 
tions for Q1 and Q2 for plus and minus 1 2V supplies. Fortu- 
nately, this error in both input and output offset voltage is 
almost always negligible when it is used inside the closed 
loop of a high gain operational amplifier. 
A plot of input impedance vs frequency is shown in Figure 2. 
Inspection of this plot shows that the input impedance can 
be closely approximated to that of a simple first order linear 
network with a 45° phase lag at 0.6 MHz and a 90° phase 
lag at approximately one decade higher in frequency. This 
information is very useful for designers who have to inte- 
grate circuits which have large source impedances over a 
wide frequency range. The output impedance of the amplifi- 
er is very low, 6ft typically, and in conjunction with a voltage 
bandwidth of approximately 50 MHz can be considered to 
be insignificant for most applications for this type of device. 
A plot of the voltage bandwidth is shown in Figure 3. Inspec- 
tion of this plot shows that phase information as well as gain 
information was included to assist users of this device. For 
example, at 10 MHz, less than an 8° phase lag would be 
subtracted from the phase margin of an operational amplifi- 
er when it is integrated with this device. The open loop gain 
of the operational amplifier would be decreased by less than 
10% at 10 MHz and therefore can be considered to be in- 
significant for most applications. 



-100 

-to 

-80 f 

cs 

3 

-40 uj 

< 

a. 
-20 



0.1 0.2 0.5 1 2 S 10 

FREQUENCY (MHz) 

TL/K/7315-2 

FIGURE 2. Input Impedance vs Frequency 





INPUT IMPEDANCE (MAGMTUOC ANO PHASE) 






._. 


«,-10Kitat.T»-2PC 






e 














/'phase 


LU 100 

z 
< 
a 

UJ 

I 10 
















































''^sJ 


NAG 


N 


TUDE 




















3 
a. 
S 1 




























































1.0 








1 1 

VOLTAGE GAIN 


-40 


0.8 














-32 














OR 


FREQUENCY RESPONSE 








-?4 




V| N - 1 .OV rms. R L = 50 ohms. V, = ± 1 2.0V 






0.4 














-16 














0.2 










_PHASI 




-8 














0.1 


















1.0 2.0 S.0 10.0 20.0 50.0 100 
FREQUENCY (MHz) 

FIGURE 3. Frequency Response 



TL/K/7315-3 



APPLICATIONS 

Figure 4 shows the LH0002 integrated with the LM101 in a 
booster follower configuration. The configuration is stable 
without the requirement for any external compensation; 
however, it would behoove the designer to be conservative 
and bypass both the negative and positive power supplies 
with at least a 0.01 ju.f capacitor to cancel out any power 
supply lead inductance. A 100ft damping resistor, located 
right at the input of the LH0002, might also be required be- 
tween the operational amplifier and the booster amplifier. 
The physical layout will determine the requirement for this 
type of oscillation suppression. Current limiting can be add- 
ed by incorporating series resistors from pins 2 and 6 to 
their respective power supplies. The exact value would be a 
function of power supply voltage and required operating 
temperature. 

A breadboard of this configuration was assembled to empiri- 
cally check the increase in offset voltage due to the addition 
of the LH0002. The offset voltage was measured with and 
without an LH0002 inside the loop with a voltage gain of 
100, at -55°C, 25°C and 125°C. The additional offset volt- 
age was less than 0.3% for all three temperature conditions 
even though the offset voltage of the LH0002 is much high- 
er than that of the LM101. The high open loop gain of the 
LM101 divides out this source of circuit error. The integra- 
tion of this device also allows higher closed loop circuit gain 
without excessive cross-over distortion than would be ob- 
tainable with the simple booster amplifier shown in Figure 5. 
Figure 6 shows the LH0002 being used as a level shifter 
with a high pass filter on the input in order to reference the 
output to zero quiescent volts. The purpose of the 10 kft 
resistor is to provide current bias to the circuit's input tran- 
sistors to reduce the output offset voltage. Figure 3, Input 
Impedance vs Frequency, provides a useful design aid in 
order to determine the value of the capacitor for the particu- 
lar application. The 10 kfi resistor, of course, has to be 
considered as being in parallel with the circuit's input imped- 
ance. 

For a pulse input signal, the output impedance of the circuit 
remains low for both the positive and negative portions of 
the output pulse. This circuit provides both fast rise and fall 
times for pulse signals, even with capacitive loading. The 
LH0002 data sheet shows typical rise and fall times for both 
positive and negative pulses into a 50ft load. 



17 



CO 



INPUT' 



-vw-U 



V S = ±5VT0 ±15V 



OUTPUT 




V,N© 



FIGURE 4. LM101-LH0002 Booster Amplifier Integration 




VOUT 



TL/K/7315-7 

FIGURE 6. Level Shifter 

Figure 7 shows the LH0002 being used to drive a pulse- 
transformer. The low output offset voltage allows the pulse 
transformer to be directly coupled to the amplifier without 
using a coupling capacitor to prevent saturation. The pulse 
transformer can be used to change the amplitude and im- 



LH0002 ^S ^ 



LH0002 ^ > a O Vqut 



TL/K/7315-8 

FIGURE 7. Driver for a Pulse-Transformer 




«v 



TL/K/7315-6 

FIGURE 5. Simple Booster Amplifier 

pedance level of the pulse, the polarity of the pulses, or, 
with the aid of a center-tapped winding, positive and nega- 
tive pulses simultaneously. 

The LH0002 can also be used to drive long transmission 
lines. Figure 8 shows a circuit configuration to match the 
output impedance of the amplifier to the load and coaxial 
cable for proper line termination to minimize reflections. A 
capacitor can be added to empirically adjust the time re- 
sponse of the waveform. 

Select capacitor to adjust time response of pulse. 




"^3 



I 

- son LOAD 



\ 



FIGURE 8. Transmission Line Driver 



SUMMARY 

The multitude of different applications suggested in this arti- 
cle shows the versatility of the LH0002. The applications 
specially covered were for a differential input-output opera- 
tional amplifier, booster amplifier, level shifter, driver for a 
pulse-transformer, and transmission line driver. 



18 



An Applications Guide for 
Op Amps 



National Semiconductor 
Application Note 20 




INTRODUCTION 

The general utility of the operational amplifier is derived 
from the fact that it is intended for use in a feedback loop 
whose feedback properties determine the feed-forward 
characteristics of the amplifier and loop combination. To suit 
it for this usage, the ideal operational amplifier would have 
infinite input impedance, zero output impedance, infinite 
gain and an open-loop 3 dB point at infinite frequency rolling 
off at 6 dB per octave. Unfortunately, the unit cost-in quan- 
tity-would also be infinite. 

Intensive development of the operational amplifier, particu- 
larly in integrated form, has yielded circuits which are quite 
good engineering approximations of the ideal for finite cost. 
Quantity prices for the best contemporary integrated amplifi- 
ers are low compared with transistor prices of five years 
ago. The low cost and high quality of these amplifiers allows 
the implementation of equipment and systems functions im- 
practical with discrete components. An example is the low 
frequency function generator which may use 15 to 20 opera- 
tional amplifiers in generation, wave shaping, triggering and 
phase-locking. 

The availability of the low-cost integrated amplifier makes it 
mandatory that systems and equipments engineers be fa- 
miliar with operational amplifier applications. This paper will 
present amplifier usages ranging from the simple unity-gain 
buffer to relatively complex generator and wave shaping cir- 
cuits. The general theory of operational amplifiers is not 
within the scope of this paper and many excellent refer- 
ences are available in the literature. 1 . 2 .3. 4 The approach will 
be shaded toward the practical, amplifier parameters will be 
discussed as they affect circuit performance, and applica- 
tion restrictions will be outlined. 

The applications discussed will be arranged in order of in- 
creasing complexity in five categories: simple amplifiers, op- 
erational circuits, transducer amplifiers, wave shapers and 
generators, and power supplies. The integrated amplifiers 
shown in the figures are for the most part internally compen- 



sated so frequency stabilization components are not shown; 
however, other amplifiers may be used to achieve greater 
operating speed in many circuits as will be shown in the text. 
Amplifier parameter definitions are contained in Appendix I. 

THE INVERTING AMPLIFIER 

The basic operational amplifier circuit is shown in Figure 1. 
This circuit gives closed-loop gain of R2/R1 when this ratio 
is small compared with the amplifier open-loop gain and, as 
the name implies, is an inverting circuit. The input imped- 
ance is equal to R1. The closed-loop bandwidth is equal to 
the unity-gain frequency divided by one plus the closed-loop 
gain. 

The only cautions to be observed are that R3 should be 
chosen to be equal to the parallel combination of R1 and R2 
to minimize the offset voltage error due to bias current and 
that there will be an offset voltage at the amplifier output 
equal to closed-loop gain times the offset voltage at the 
amplifier input. 




R2 
v OUT = ST V IN 



>R3 R1 

< R3 = R1 | R2 

I For minimum error due 

^T to input bias current 

TL/H/6822-1 

FIGURE 1. Inverting Amplifier 

Offset voltage at the input of an operational amplifier is 
comprised of two components, these components are iden- 
tified in specifying the amplifier as input offset voltage and 
input bias current. The input offset voltage is fixed for a 
particular amplifier, however the contribution due to input 



19 



bias current is dependent on the circuit configuration used. 
For minimum offset voltage at the amplifier input without 
circuit adjustment the source resistance for both inputs 
should be equal. In this case the maximum offset voltage 
would be the algebraic sum of amplifier offset voltage and 
the voltage drop across the source resistance due to offset 
current. Amplifier offset voltage is the predominant error 
term for low source resistances and offset current causes 
the main error for high source resistances. 
In high source resistance applications, offset voltage at the 
amplifier output may be adjusted by adjusting the value of 
R3 and using the variation in voltage drop across it as an 
input offset voltage trim. 

Offset voltage at the amplifier output is not as important in 
AC coupled applications. Here the only consideration is that 
any offset voltage at the output reduces the peak to peak 
linear output swing of the amplifier. 
The gain-frequency characteristic of the amplifier and its 
feedback network must be such that oscillation does not 
occur. To meet this condition, the phase shift through ampli- 
fier and feedback network must never exceed 180° for any 
frequency where the gain of the amplifier and its feedback 
network is greater than unity. In practical applications, the 
phase shift should not approach 1 80° since this is the situa- 
tion of conditional stability. Obviously the most critical case 
occurs when the attenuation of the feedback network is 
zero. 

Amplifiers which are not internally compensated may be 
used to achieve increased performance in circuits where 
feedback network attenuation is high. As an example, the 
LM101 may be operated at unity gain in the inverting amplifi- 
er circuit with a 15 pF compensating capacitor, since the 
feedback network has an attenuation of 6 dB, while it re- 
quires 30 pF in the non-inverting unity gain connection 
where the feedback network has zero attenuation. Since 
amplifier slew rate is dependent on compensation, the 
LM101 slew rate in the inverting unity gain connection will 
be twice that for the non-inverting connection and the in- 
verting gain of ten connection will yield eleven times the 
slew rate of the non-inverting unity gain connection. The 
compensation trade-off for a particular connection is stabili- 
ty versus bandwidth, larger values of compensation capaci- 
tor yield greater stability and lower bandwidth and vice 
versa. 

The preceding discussion of offset voltage, bias current and 
stability is applicable to most amplifier applications and will 
be referenced in later sections. A more complete treatment 
is contained in Reference 4. 



THE NON-INVERTING AMPLIFIER 

Figure 2 shows a high input impedance non-inverting circuit. 
This circuit gives a closed-loop gain equal to the ratio of the 
sum of R1 and R2 to R1 and a closed-loop 3 dB bandwidth 
equal to the amplifier unity-gain frequency divided by the 
closed-loop gain. 

The primary differences between this connection and the 
inverting circuit are that the output is not inverted and that 
the input impedance is very high and is equal to the differen- 
tial input impedance multiplied by loop gain. (Open loop 
gain/Closed loop gain.) In DC coupled applications, input 
impedance is not as important as input current and its volt- 
age drop across the source resistance. 
Applications cautions are the same for this amplifier as for 
the inverting amplifier with one exception. The amplifier out- 
put will go into saturation if the input is allowed to float. This 
may be important if the amplifier must be switched from 
source to source. The compensation trade off discussed for 
the inverting amplifier is also valid for this connection. 




R2 _ R1 

VOUT - ' 



R2. 



: V| N 



R1 
R1 || R2 = RsoURCE 
For minimum error due 
to input bias current 

TL/H/6822-2 

FIGURE 2. Non-Inverting Amplifier 

THE UNITY-GAIN BUFFER 

The unity-gain buffer is shown in Figure 3. The circuit gives 
the highest input impedance of any operational amplifier cir- 
cuit. Input impedance is equal to the differential input imped- 
ance multiplied by the open-loop gain, in parallel with com- 
mon mode input impedance. The gain error of this circuit is 
equal to the reciprocal of the amplifier open-loop gain or to 
the common mode rejection, whichever is less. 



'VoUT 

VOUT = V IN 

R1 = Rsource 

For minimum error due 

to input bias current 

TL/H/6822-3 

FIGURE 3. Unity Gain Buffer 




20 



Input impedance is a misleading concept in a DC coupled 
unity-gain buffer. Bias current for the amplifier will be sup- 
plied by the source resistance and will cause an error at the 
amplifier input due to its voltage drop across the source 
resistance. Since this is the case, a low bias current amplifi- 
er such as the LH102 6 should be chosen as a unity-gain 
buffer when working from high source resistances. Bias cur- 
rent compensation techniques are discussed in Reference 
5. 

The cautions to be observed in applying this circuit are 
three: the amplifier must be compensated for unity gain op- 
eration, the output swing of the amplifier may be limited by 
the amplifier common mode range, and some amplifiers ex- 
hibit a latch-up mode when the amplifier common mode 
range is exceeded. The LM107 may be used in this circuit 
with none of these problems; or, for faster operation, the 
LM102 may be chosen. 



R1 




R5 = R1 || R2 || R3 || R4 
For minimum offset error due 
to input bias current 



TL/H/6822-4 



FIGURE 4. Summing Amplifier 



SUMMING AMPLIFIER 

The summing amplifier, a special case of the inverting am- 
plifier, is shown in Figure 4. The circuit gives an inverted 
output which is equal to the weighted algebraic sum of all 
three inputs. The gain of any input of this circuit is equal to 
the ratio of the appropriate input resistor to the feedback 
resistor, R4. Amplifier bandwidth may be calculated as in 
the inverting amplifier shown in Figure 1 by assuming the 
input resistor to be the parallel combination of R1, R2, and 
R3. Application cautions are the same as for the inverting 
amplifier. If an uncompensated amplifier is used, compensa- 
tion is calculated on the basis of this bandwidth as is dis- 
cussed in the section describing the simple inverting amplifi- 
er. 

The advantage of this circuit is that there is no interaction 
between inputs and operations such as summing and 
weighted averaging are implemented very easily. 

THE DIFFERENCE AMPLIFIER 

The difference amplifier is the complement of the summing 
amplifier and allows the subtraction of two voltages or, as a 
special case, the cancellation of a signal common to the 
two inputs. This circuit is shown in Figure 5 and is useful as 
a computational amplifier, in making a differential to single- 
ended conversion or in rejecting a common mode signal. 




R1_+_R2\R4 _R2 
R3 + R4/ R1 2 R1 1 
For R1 = R3 and R2 = R4 



R2 
V UT= R -j-(V 2 



Vi) 



R1 || R2 = R3 || R4 
For minimum offset error 
due to input bias current 



TL/H/6822-5 



FIGURE 5. Difference Amplifier 

Circuit bandwidth may be calculated in the same manner as 
for the inverting amplifier, but input impedance is somewhat 
more complicated. Input impedance for the two inputs is not 
necessarily equal; inverting input impedance is the same as 
for the inverting amplifier of Figure 1 and the non-inverting 
input impedance is the sum of R3 and R4. Gain for either 
input is the ratio of R1 to R2 for the special case of a differ- 
ential input single-ended output where R1 = R3 and R2 = 
R4. The general expression for gain is given in the figure. 
Compensation should be chosen on the basis of amplifier 
bandwidth. 

Care must be exercised in applying this circuit since input 
impedances are not equal for minimum bias current error. 

DIFFERENTIATOR 

The differentiator is shown in Figure 6 and, as the name 
implies, is used to perform the mathematical operation of 
differentiation. The form shown is not the practical form, it is 
a true differentiator and is extremely susceptible to high fre- 
quency noise since AC gain increases at the rate of 6 dB 
per octave. In addition, the feedback network of the differ- 
entiator, R1C1, is an RC low pass filter which contributes 
90° phase shift to the loop and may cause stability problems 
even with an amplifier which is compensated for unity gain. 




V 0U T= -R1C1-(V, N ) 

R1 = R2 

For minimum offset error 
^T due to input bias current 

TL/H/6822-6 

FIGURE 6. Differentiator 



21 



',«-A/VSr— 1 |— oW * 

LMIOI^ # v out 



2irR2C1 
1 



< 30 pF 



h 2irR1C1 2ttR2C2 _ 

f c < f h < f U nltygain TL/H/6822-7 

FIGURE 7. Practical Differentiator 

A practical differentiator is shown in Figure 7. Here both the 
stability and noise problems are corrected by addition of two 
additional components, R1 and C2. R2 and C2 form a 6 dB 
per octave high frequency roll-off in the feedback network 
and R1C1 form a 6 dB per octave roll-off network in the 
input network for a total high frequency roll-off of 12 dB per 
octave to reduce the effect of high frequency input and am- 
plifier noise. In addition R1C1 and R2C2 form lead networks 
in the feedback loop which, if placed below the amplifier 
unity gain frequency, provide 90° phase lead to compensate 
the 90° phase lag of R2C1 and prevent loop instability. A 
gain frequency plot is shown in Figure 8 for clarity. 




I 1<M 10W 1000f 19000) 

RELATIVE FREQUENCY 

TL/H/6822-8 

FIGURE 8. Differentiator Frequency Response 

INTEGRATOR 

The integrator is shown in Figure 9 and performs the mathe- 
matical operation of integration. This circuit is essentially 

r- — — — — — — —1 S,„ 




2irR1C1 
R1 = R2 

For minimum offset error 
due to input bias current 

FIGURE 9. Integrator 



TL/H/6822-9 



a low-pass filter with a frequency response decreasing at 
6 dB per octave. An amplitude-frequency plot is shown in 
Figure 10. 






I 10f 1001 10001 100001 

RELATIVE FREQUENCY 

TL/H/6822-10 

FIGURE 10. Integrator Frequency Response 

The circuit must be provided with an external method of 
establishing initial conditions. This is shown in the figure as 
Si . When Si is in position 1 , the amplifier is connected in 
unity-gain and capacitor C1 is discharged, setting an initial 
condition of zero volts. When Si is in position 2, the amplifi- 
er is connected as an integrator and its output will change in 
accordance with a constant times the time integral of the 
input voltage. 

The cautions to be observed with this circuit are two: the 
amplifier used should generally be stabilized for unity-gain 
operation and R2 must equal R1 for minimum error due to 
bias current. 

SIMPLE LOW-PASS FILTER 

The simple low-pass filter is shown in Figure 1 1. This circuit 
has a 6 dB per octave roll-off after a closed-loop 3 dB point 
defined by f c . Gain below this corner frequency is defined by 
the ratio of R3 to R1. The circuit may be considered as an 
AC integrator at frequencies well above f c ; however, the 
time domain response is that of a single RC rather than an 
integral. 




R1 TL/H/6822-11 

FIGURE 11. Simple Low Pass Filter 

R2 should be chosen equal to the parallel combination of 
R1 and R3 to minimize errors due to bias current. The ampli- 
fier should be compensated for unity-gain or an internally 
compensated amplifier can be used. 



22 





f c 


52 = 100 

R1 


















It 











f lOf INf 10001 100001 

RELATIVE FREQUENCY 

TL/H/6822-12 

FIGURE 12. Low Pass Filter Response 

A gain frequency plot of circuit response is shown in Figure 
12 to illustrate the difference between this circuit and the 
true integrator. 

THE CURRENT-TO-VOLTAGE CONVERTER 

Current may be measured in two ways with an operational 
amplifier. The current may be converted into a voltage with 
a resistor and then amplified or the current may be injected 
directly into a summing node. Converting into voltage is un- 
desirable for two reasons: first, an impedance is inserted 
into the measuring line causing an error; second, amplifier 
offset voltage is also amplified with a subsequent loss of 
accuracy. The use of a current-to-voltage transducer avoids 
both of these problems. 

The current-to-voltage transducer is shown in Figure 13. 
The input current is fed directly into the summing node and 
the amplifier output voltage changes to extract the same 
current from the summing node through R1. The scale fac- 
tor of this circuit is R1 volts per amp. The only conversion 
error in this circuit is Ibjas which is summed algebraically with 
'in- 

R1 




VOUT = l|N R1 



Tl/H/6822-13 

FIGURE 13. Current to Voltage Converter 

This basic circuit is useful for many applications other than 
current measurement. It is shown as a photocell amplifier in 
the following section. 

The only design constraints are that scale factors must be 
chosen to minimize errors due to bias current and since 
voltage gain and source impedance are often indeterminate 
(as with photocells) the amplifier must be compensated for 
unity-gain operation. Valuable techniques for bias current 
compensation are contained in Reference 5. 




> 
Z 

IS) 

O 



TL/H/6822-14 

FIGURE 14. Amplifier for Photoconductive Cell 

PHOTOCELL AMPLIFIERS 

Amplifiers for photoconductive, photodiode and photovolta- 
ic cells are shown in Figures 14, 15 and 16 respectively. 
All photogenerators display some voltage dependence of 
both speed and linearity. It is obvious that the current 
rhough a photoconductive cell will not display strict propor- 
tionality to incident light if the cell terminal voltage is allowed 
to vary with cell conductance. Somewhat less obvious is the 
fact that photodiode leakage and photovoltaic cell internal 
losses are also functions of terminal voltage. The current-to- 
voltage converter neatly sidesteps gross linearity problems 
by fixing a constant terminal voltage, zero in the case of 
photovoltaic cells and a fixed bias voltage in the case of 
photoconductors or photodiodes. 




Vout = R1 Id 



TL/H/6822-15 



FIGURE 15. Photodiode Amplifier 

Photodetector speed is optimized by operating into a fixed 
low load impedance. Currently available photovoltaic detec- 
tors show response times in the microsecond range at zero 
load impedance and photoconductors, even though slow, 
are materially faster at low load resistances. 

R1 




v OUT = 'CELL R1 

TL/H/6822-16 

FIGURE 16. Photovoltaic Cell Amplifier 



23 



The feedback resistance, R1, is dependent on cell sensitivi- 
ty and should be chosen for either maximum dynamic range 
or for a desired scale factor. R2 is elective: in the case of 
photovoltaic cells or of photodiodes, it is not required in the 
case of photoconductive cells, it should be chosen to mini- 
mize bias current error over the operating range. 

PRECISION CURRENT SOURCE 

The precision current source is shown in Figures 17 and 18. 
The configurations shown will sink or source conventional 
current respectively. 



The amplifiers used must be compensated for unity-gain 
and additional compensation may be required depending on 
load reactance and external transistor parameters. 




TL/H/6822-17 

FIGURE 17. Precision Current Sink 

Caution must be exercised in applying these circuits. The 
voltage compliance of the source extends from BVqer of 
the external transistor to approximately 1 volt more negative 
than Vin- The compliance of the current sink is the same in 
the positive direction. 

The impedance of these current generators is essentially 
infinite for small currents and they are accurate so long as 
Vin is much greater than Vos and lo ' s much greater than 
'bias- 

The source and sink illustrated in Figures 17 and 18 use an 
FET to drive a bipolar output transistor. It is possible to use 
a Darlington connection in place of the FET-bipolar combi- 
nation in cases where the output current is high and the 
base current of the Darlington input would not cause a sig- 
nificant error. 








TL/H/6822-19 

FIGURE 19a. Positive Voltage Reference 

ADJUSTABLE VOLTAGE REFERENCES 

Adjustable voltage reference circuits are shown in Figures 
19 and 20. The two circuits shown have different areas of 
applicability. The basic difference between the two is that 
Figure 19 illustrates a voltage source which provides a volt- 
age greater than the reference diode while Figure 20 illus- 
trates a voltage source which provides a voltage lower than 
the reference diode. The figures show both positive and 
negative voltage sources. 




TL/H/6822-20 

FIGURE 19b. Negative Voltage Reference 

High precision extended temperature applications of the cir- 
cuit of Figure 19 require that the range of adjustment of 
Vout be restricted. When this is done, R1 may be chosen to 
provide optimum zener current for minimum zener T.C. 
Since lz is not a function of V+ , reference T.C. will be inde- 
pendent of V+. 



TL/H/6822-18 

FIGURE 18. Precision Current Source 



24 




V OUT 



TL/H/6822-21 

FIGURE 20a. Positive Voltage Reference 




TL/H/6822-22 

FIGURE 20b. Negative Voltage Reference 

The circuit of Figure 20 is suited for high precision extended 
temperature service if V+ is reasonably constant since lz is 
dependent on V+. R1, R2, R3, and R4 are chosen to pro- 
vide the proper lz for minimum T.C. and to minimize errors 
due to l b ias- 

The circuits shown should both be compensated for unity- 
gain operation or, if large capacitive loads are expected, 
should be overcompensated. Output noise may be reduced 
in both circuits by bypassing the amplifier input. 
The circuits shown employ a single power supply, this re- 
quires that common mode range be considered in choosing 
an amplifier for these applications. If the common mode 
range requirements are in excess of the capability of the 
amplifier, two power supplies may be used. The LH101 may 
be used with a single power supply since the common mode 
range is from V+ to within approximately 2 volts of V~. 

THE RESET STABILIZED AMPLIFIER 

The reset stabilized amplifier is a form of chopper-stabilized 
amplifier and is shown in Figure 21. As shown, the amplifier 
is operated closed-loop with a gain of one. 




TL/H/6822-23 

FIGURE 21. Reset Stabilized Amplifier 

The connection is useful in eliminating errors due to offset 
voltage and bias current. The output of this circuit is a pulse 
whose amplitude is equal to Vin. Operation may be under- 
stood by considering the two conditions corresponding to 
the position of S-|. When S-| is in position 2, the amplifier is 
connected in the unity gain connection and the voltage at 
the output will be equal to the sum of the input offset volt- 
age and the drop across R2 due to input bias current. The 
voltage at the inverting input will be equal to input offset 
voltage. Capacitor C1 will charge to the sum of input offset 
voltage and Vin through R1. When C1 is charged, no cur- 
rent flows through the source resistance and R1 so there is 
no error due to input resistance. Si is then changed to posi- 
tion 1. The voltage stored on C1 is inserted between the 
output and inverting input of the amplifier and the output of 
the amplifier changes by Vin to maintain the amplifier input 
at the input offset voltage. The output then changes from 
(Vos + 'bias R2 ) to (V| N + lbias R2 ) as S 1 is changed from 
position 2 to position 1. Amplifier bias current is supplied 
through R2 from the output of the amplifier or from C2 when 
Si is in position 2 and position 1 respectively. R3 serves to 
reduce the offset at the amplifier output if the amplifier must 
have maximum linear range or if it is desired to DC couple 
the amplifier. 

An additional advantage of this connection is that input re- 
sistance approaches infinity as the capacitor C1 ap- 
proaches full charge, eliminating errors due to loading of the 
source resistance. The time spent in position 2 should be 
long with respect to the charging time of C1 for maximum 
accuracy. 

The amplifier used must be compensated for unity gain op- 
eration and it may be necessary to overcompensate be- 
cause of the phase shift across R2 due to C1 and the ampli- 
fier input capacity. Since this connection is usually used at 
very low switching speeds, slew rate is not normally a practi- 
cal consideration and overcompensation does not reduce 
accuracy. 



25 







v, 



v- v ? 

FIGURE 22. Analog Multiplier 



TL/H/6822-24 



THE ANALOG MULTIPLIER 

A simple embodiment of the analog multiplier is shown in 
Figure 22. This circuit circumvents many of the problems 
associated with the log-antilog circuit and provides three 
quadrant analog multiplication which is relatively tempera- 
ture insensitive and which is not subject to the bias current 
errors which plague most multipliers. 
Circuit operation may be understood by considering A2 as a 
controlled gain amplifier, amplifying V2, whose gain is de- 
pendent on the ratio of the resistance of PC2 to R5 and by 
considering A1 as a control amplifier which establishes the 
resistance of PC2 as a function of V-|. In this way it is seen 
that Vout is a function of both V1 and V2. 
A1, the control amplifier, provides drive for the lamp, L1. 
When an input voltage, V1 , is present, L1 is driven by A1 
until the current to the summing junction from the negative 
supply through PC1 is equal to the current to the summing 
junction from V1 through R1. Since the negative supply volt- 
age is fixed, this forces the resistance of PC1 to a value 
proportional to R1 and to the ratio of V1 to V - . L1 also 
illuminates PC2 and, if the photoconductors are matched, 
causes PC2 to have a resistance equal to PC1 . 
A2, the controlled gain amplifier, acts as an inverting amplifi- 
er whose gain is equal to the ratio of the resistance of PC2 
to R5. If R5 is chosen equal to the product of R1 and V~, 
then Vout becomes simply the product of V-j and V2. R5 
may be scaled in powers of ten to provide any required 
output scale factor. 

PC1 and PC2 should be matched for best tracking over tem- 
perature since the T.C. of resistance is related to resistance 
match for cells of the same geometry. Small mismatches 
may be compensated by varying the value of R5 as a scale 
factor adjustment. The photoconductive cells should re- 
ceive equal illumination from L1 , a convenient method is to 



mount the cells in holes in an aluminum block and to mount 
the lamp midway between them. This mounting method pro- 
vides controlled spacing and also provides a thermal bridge 
between the two cells to reduce differences in cell tempera- 
ture. This technique may be extended to the use of FET's or 
other devices to meet special resistance or environment re- 
quirements. 

The circuit as shown gives an inverting output whose magni- 
tude is equal to one-tenth the product of the two analog 
inputs. Input V1 is restricted to positive values, but V2 may 
assume both positive and negative values. This circuit is 
restricted to low frequency operation by the lamp time con- 
stant. 

R2 and R4 are chosen to minimize errors due to input offset 
current as outlined in the section describing the photocell 
amplifier. R3 is included to reduce in-rush current when first 
turning on the lamp, L1 . 

THE FULL-WAVE RECTIFIER 
AND AVERAGING FILTER 

The circuit shown in Figure 23 is the heart of an average 
reading, rms calibrated AC voltmeter. As shown, it is a recti- 
fier and averaging filter. Deletion of C2 removes the averag- 
ing function and provides a precision full-wave rectifier, and 
deletion of C1 provides an absolute value generator. 
Circuit operation may be understood by following the signal 
path for negative and then for positive inputs. For negative 
signals, the output of amplifier A1 is clamped to + 0.7V by 
D1 and disconnected from the summing point of A2 by D2. 
A2 then functions as a simple unity-gain inverter with input 
resistor, R1, and feedback resistor, R2, giving a positive go- 
ing output. 

For positive inputs, A1 operates as a normal amplifier con- 
nected to the A2 summing point through resistor, R5. Ampli- 
fier A1 then acts as a simple unity-gain inverter with input 



26 




ro 

o 



TL/H/6822-25 



FIGURE 23. Full-Wave Rectifier and Averaging Filter 



resistor, R3, and feedback resistor, R5. A1 gain accuracy is 
not affected by D2 since it is inside the feedback loop. Posi- 
tive current enters the A2 summing point through resistor, 
R1, and negative current is drawn from the A2 summing 
point through resistor, R5. Since the voltages across R1 and 
R5 are equal and opposite, and R5 is one-half the value of 
R1 , the net input current at the A2 summing point is equal to 
and opposite from the current through R1 and amplifier A2 
operates as a summing inverter with unity gain, again giving 
a positive output. 

The circuit becomes an averaging filter when C2 is connect- 
ed across R2. Operation of A2 then is similar to the Simple 
Low Pass Filter previously described. The time constant 
R2C2 should be chosen to be much larger than the maxi- 
mum period of the input voltage which is to be averaged. 
Capacitor C1 may be deleted if the circuit is to be used as 
an absolute value generator. When this is done, the circuit 
output will be the positive absolute value of the input volt- 
age. 

The amplifiers chosen must be compensated for unity-gain 
operation and R6 and R7 must be chosen to minimize out- 
put errors due to input offset current. 

SINE WAVE OSCILLATOR 

An amplitude-stabilized sine-wave oscillator is shown in Fig- 
ure 24. This circuit provides high purity sine-wave output 
down to low frequencies with minimum circuit complexity. 
An important advantage of this circuit is that the traditional 
tungsten filament lamp amplitude regulator is eliminated 
along with its time constant and linearity problems. 
In addition, the reliability problems associated with a lamp 
are eliminated. 

The Wien Bridge oscillator is widely used and takes advan- 
tage of the fact that the phase of the voltage across the 
parallel branch of a series and a parallel RC network con- 
nected in series, is the same as the phase of the applied 
voltage across the two networks at one particular frequency 
and that the phase lags with increasing frequency and leads 



with decreasing frequency. When this network — the Wien 
Bridge — is used as a positive feedback element around an 
amplifier, oscillation occurs at the frequency at which the 
phase shift is zero. Additional negative feedback is provided 
to set loop gain to unity at the oscillation frequency, to stabi- 
lize the frequency of oscillation, and to reduce harmonic 
distortion. 




V OUT = 16 5 v PP 
10 Hz 



TL/H/6822-26 

FIGURE 24. Wien Bridge Sine Wave Oscillator 

The circuit presented here differs from the classic usage 
only in the form of the negative feedback stabilization 
scheme. Circuit operation is as follows: negative peaks in 
excess of -8.25V cause D1 and D2 to conduct, charging 



27 



C4. The charge stored in C4 provides bias to Q1, which 
determines amplifier gain. C3 is a low frequency roll-off ca- 
pacitor in the feedback network and prevents offset voltage 
and offset current errors from being multiplied by amplifier 
gain. 

Distortion is determined by amplifier open-loop gain and by 
the response time of the negative feedback loop filter, R5 
and C4. A trade-off is necessary in determining amplitude 
stabilization time constant and oscillator distortion. R4 is 
chosen to adjust the negative feedback loop so that the 
FET is operated at a small negative gate bias. The circuit 
shown provides optimum values for a general purpose oscil- 
lator. 

TRIANGLE-WAVE GENERATOR 

A constant amplitude triangular-wave generator is shown in 
Figure 25. This circuit provides a variable frequency triangu- 
lar wave whose amplitude is independent of frequency. 



THRESH010 DETECTOR 




TL/H/6822-27 

FIGURE 25. Triangular-Wave Generator 

The generator embodies an integrator as a ramp generator 
and a threshold detector with hysterisis as a reset circuit. 
The integrator has been described in a previous section and 
requires no further explanation. The threshold detector is 
similar to a Schmitt Trigger in that it is a latch circuit with a 
large dead zone. This function is implemented by using pos- 
itive feedback around an operational amplifier. When the 
amplifier output is in either the positive or negative saturated 
state, the positive feedback network provides a voltage at 
the non-inverting input which is determined by the attenua- 
tion of the feed-back loop and the saturation voltage of the 
amplifier. To cause the amplifier to change states, the volt- 
age at the input of the amplifier must be caused to change 
polarity by an amount in excess of the amplifier input offset 
voltage. When this is done the amplifier saturates in the 
opposite direction and remains in that state until the voltage 
at its input again reverses. The complete circuit operation 
may be understood by examining the operation with the out- 
put of the threshold detector in the positive state. The de- 
tector positive saturation voltage is applied to the integrator 
summing junction through the combination R3 and R4 caus- 
ing a current I + to flow. 



The integrator then generates a negative-going ramp with a 
rate of I + /C1 volts per second until its output equals the 
negative trip point of the threshold detector. The threshold 
detector then changes to the negative output state and sup- 
plies a negative current, I - , at the integrator summing point. 
The integrator now generates a positive-going ramp with a 
rate of l~/C1 volts per second until its output equals the 
positive trip point of the threshold detector where the detec- 
tor again changes output state and the cycle repeats. 
Triangular-wave frequency is determined by R3, R4 and C1 
and the positive and negative saturation voltages of the am- 
plifier A1 . Amplitude is determined by the ratio of R5 to the 
combination of R1 and R2 and the threshold detector satu- 
ration voltages. Positive and negative ramp rates are equal 
and positive and negative peaks are equal if the detector 
has equal positive and negative saturation voltages. The 
output waveform may be offset with respect to ground if the 
inverting input of the threshold detector, A1 , is offset with 
respect to ground. 

The generator may be made independent of temperature 
and supply voltage if the detector is clamped with matched 
zener diodes as shown in Figure 26. 
The integrator should be compensated for unity-gain and 
the detector may be compensated if power supply imped- 
ance causes oscillation during its transition time. The cur- 
rent into the integrator should be large with respect to Ibias 
for maximum symmetry, and offset voltage should be small 
with respect to Vqut peak. 



(MATCHED ZENERS) 



^ TO INTEGRATOR INPUT 



FROM INTEGRATOR 
OUTPUT 



TL/H/6822-28 

FIGURE 26. Threshold Detector with Regulated Output 

TRACKING REGULATED POWER SUPPLY 

A tracking regulated power supply is shown in Figure 27. 
This supply is very suitable for powering an operational am- 
plifier system since positive and negative voltages track, 
eliminating common mode signals originating in the supply 
voltage. In addition, only one voltage reference and a mini- 
mum number of passive components are required. 




28 



•40V UNREGULATED 




*V 0UT <REG) 



Output voltage is variable from ± 5V to 
±35V. 

' -40V UNREGULATED Negative output tracks positive output to 

within the ratio of R6 to R7. 

TL/H/6822-29 

FIGURE 27. Tracking Power Supply 

Power supply operation may be understood by considering 
first the positive regulator. The positive regulator compares 
the voltage at the wiper of R4 to the voltage reference, D2. 
The difference between these two voltages is the input volt- 
age for the amplifier and since R3, R4, and R5 form a nega- 
tive feedback loop, the amplifier output voltage changes in 
such a way as to minimize this difference. The voltage refer- 
ence current is supplied from the amplifier output to in- 
crease power supply line regulation. This allows the regula- 
tor to operate from supplies with large ripple voltages. Reg- 
ulating the reference current in this way requires a separate 
source of current for supply start-up. Resistor R1 and diode 
D1 provide this start-up current. D1 decouples the reference 
string from the amplifier output during start-up and R1 sup- 
plies the start-up current from the unregulated positive sup- 
ply. After start-up, the low amplifier output impedance re- 
duces reference current variations due to the current 
through R1. 

The negative regulator is simply a unity-gain inverter with 
input resistor, R6, and feedback resistor, R7. 

The amplifiers must be compensated for unity-gain opera- 
tion. 

The power supply may be modulated by injecting current 
into the wiper of R4. In this case, the output voltage varia- 
tions will be equal and opposite at the positive and negative 
outputs. The power supply voltage may be controlled by 
replacing D1, D2, R1 and R2 with a variable voltage refer- 
ence. 



PROGRAMMABLE BENCH POWER SUPPLY 

The complete power supply shown in Figure 28 is a pro- 
grammable positive and negative power supply. The regula- 
tor section of the supply comprises two voltage followers 
whose input is provided by the voltage drop across a refer- 
ence resistor of a precision current source. 



> 

IS) 




I/1SASLO8L0 



50 jif 



TL/H/6822-30 



Wr-O-i 




'WNr-O— -i 

R12 J_ 



FIGURE 28. Low-Power Supply for 
Integrated Circuit Testing 



29 



Programming sensitivity of the positive and negative supply 
is 1V7 1000ft of resistors R6 and R12 respectively. The out- 
put voltage of the positive regulator may be varied from ap- 
proximately + 2V to + 38V with respect to ground and the 
negative regulator output voltage may be varied from -38V 
to 0V with respect to ground. Since LM107 amplifiers are 
used, the supplies are inherently short circuit proof. This 
current limiting feature also serves to protect a test circuit if 
this supply is used in integrated circuit testing. 
Internally compensated amplifiers may be used in this appli- 
cation if the expected capacitive loading is small. If large 
capacitive loads are expected, an externally compensated 
amplifier should be used and the amplifier should be over- 
compensated for additional stability. Power supply noise 
may be reduced by bypassing the amplifier inputs to ground 
with capacitors in the 0.1 to 1.0 ju.F range. 

CONCLUSIONS 

The foregoing circuits are illustrative of the versatility of the 
integrated operational amplifier and provide a guide to a 
number of useful applications. The cautions noted in each 
section will show the more common pitfalls encountered in 
amplifier usage. 

APPENDIX I 

DEFINITION OF TERMS 

Input Offset Voltage: That voltage which must be applied 
between the input terminals through two equal resistances 
to obtain zero output voltage. 

Input Offset Current: The difference in the currents into 
the two input terminals when the output is at zero. 
Input Bias Current: The average of the two input currents. 
Input Voltage Range: The range of voltages on the input 
terminals for which the amplifier operates within specifica- 
tions. 

Common Mode Rejection Ratio: The ratio of the input 
voltage range to the peak-to-peak change in input offset 
voltage over this range. 



Input Resistance: The ratio of the change in input voltage 
to the change in input current on either input with the other 
grounded. 

Supply Current: The current required from the power sup- 
ply to operate the amplifier with no load and the output at 
zero. 

Output Voltage Swing: The peak output voltage swing, re- 
ferred to zero, that can be obtained without clipping. 
Large-Signal Voltage Gain: The ratio of the output voltage 
swing to the change in input voltage required to drive the 
output from zero to this voltage. 

Power Supply Rejection: The ratio of the change in input 
offset voltage to change in power supply voltage producing 
it. 

Slew Rate: The internally-limited rate of change in output 
voltage with a large-amplitude step function applied to the 
input. 

REFERENCES 

1 . D.C. Amplifier Stabilized for Zero and Gain; Williams, Tap- 
ley, and Clark; AIEE Transactions, Vol. 67, 1948. 

2. Active Network Synthesis; K. L. Su, McGraw-Hill Book 
Co., Inc., New York, New York. 

3. Analog Computation; A. S. Jackson, McGraw-Hill Book 
Co., Inc., New York, New York. 

4. A Palimpsest on the Electronic Analog Art; H. M. Paynter, 
Editor. Published by George A. Philbrick Researches, 
Inc., Boston, Mass. 

5. Drift Compensation Techniques for Integrated D.C. Am- 
plifiers; R. J. Widlar, EDN, June 10, 1968. 

6. A Fast Integrated Voltage Follower With Low Input Cur- 
rent; R. J. Widlar, Microelectronics, Vol. 1 No. 7, June 
1968. 



30 



The LM105-An Improved 
Positive Regulator 

Robert J. Widlar 
Apartado Postal 541 
Puerto Vallarta, Jalisco 
Mexico 

introduction 

IC voltage regulators are seeing rapidly increasing usage. 
The LM100, one of the first, has already been widely ac- 
cepted. Designed for versatility, this circuit can be used as a 
linear regulator, a switching regulator, a shunt regulator, or 
even a current regulator. The output voltage can be set be- 
tween 2V and 30V with a pair of external resistors, and it 
works with unregulated input voltages down to 7V. Dissipa- 
tion limitations of the IC package restrict the output current 
to less than 20 mA, but external transistors can be added to 
obtain output currents in excess of 5A. The LM100 and an 
extensive description of its use in many practical circuits are 
described in References 1 -3. 

One complaint about the LM100 has been that it does not 
have good enough regulation for certain applications. In ad- 
dition, it becomes difficult to prove that the load regulation is 
satisfactory under worst-case design conditions. These 
problems prompted development of the LM105, which is 
nearly identical to the LM100 except that a gain stage has 
been added for improved regulation. In the great majority of 
applications, the LM105 is a plug-in replacement for the 
LM100. 

the improved regulator 

The load regulation of the LM100 is about 0.1 %, no load to 
full load, without current limiting. When short circuit protec- 
tion is added, the regulation begins to degrade as the output 
current becomes greater than about half the limiting current. 
This is illustrated in Figure 1. The LM105, on the other hand, 
gives 0.1% regulation up to currents closely approaching 
the short circuit current. As shown in Figure 1b, this is partic- 
ularly significant at high temperatures. 
The current limiting characteristics of a regulator are impor- 
tant for two reasons: First, it is almost mandatory that a 
regulator be short-circuit protected because the output is 
distributed to enough places that the probability of it becom- 
ing shorted is quite high, Secondly, the sharpness of the 
limiting characteristics is not improved by the addition of 
external booster transistors. External transistors can in- 
crease the maximum output current, but they do not im- 
prove the load regulation at currents approaching the short 



National Semiconductor 
Application Note 23 




IS) 
CO 



2 ° 

z 
o 
P -0.2 

< 
> 

° -0.4 

UJ 

a 

< 

> 

£ -.08 

I- 

3 

o 
-1.0 























■>V 






v 
















\ 










LM100 ' 




1 












\ 
















T 


I 












SH 
CU 


i 

0RT CIRCUIT 










RRENT 










L> 




Rsc = 10" 








V 


*b"C 











10 20 30 

LOAD CURRENT (mA) 

a. Ti = 25°C 



o -0.4 

UJ 

cs 

4 

5 -0.6 

o 
> 

= -0.8 

a. 
t- 

° -1.0 



















""■-» 


"N 






_ LM1 


0(1 \ 




1l 


LM105 








I 










Zi 












ZJ 












i SHORT CIRCUIT 








h CURRENT 










^ 




"R SC = 10SZ] 










"V 

1 


i i 






1 





10 20 

LOAD CURRENT (mA) 

b.Tj = 125°C 



TL/H/6906-2 



Figure 1. Comparison between the load regulation of 
the LM100 and LM105 for equal short circuit 
currents 

circuit current. Thus, it can be seen that the LM1 05 provides 
more than ten times better load regulation in practical power 
supply designs. 



31 



Figure 2 shows that the LM105 also provides better line 
regulation than the LM100. These curves give the percent- 
age change in output voltage for an incremental change in 
the unregulated input voltage. They show that the line regu- 
lation is worst for small differences between the input and 
output voltages. The LM105 provides about three times bet- 
ter regulation under worst case conditions. Bypassing the 
internal reference of the regulator makes the ripple rejection 
of the LM105 almost a factor of ten better than the LM100 
over the entire operating range, as shown in the figure. This 
bypass capacitor also eliminates noise generated in the in- 
ternal reference zener of the IC. 













EVou 

no - 


T = 


10V : 










J M 


















































-LM 


105*" 
















































































IM10S RIPPLE R 
















I 


f 


>12 


ft- 

ot 


I 



INPUT-OUTPUT VOLTAGE DIFFERENTIAL (V) 

TL/H/6906-3 

Figure 2. Comparison between the line regulation char- 
acteristics of the LM100 and LM105 

The LM105 has also benefited from the use of new IC com- 
ponents developed after the LM100 was designed. These 
have reduced the internal power consumption so that the 
LM105 can be specified for input voltages up to 50V and 
output voltages to 40V. The minimum preload current re- 
quired by the LM100 is not needed on the LM105. 

circuit description 

The differences between the LM100 and the LM105 can be 
seen by comparing the schematic diagrams in Figures 3 and 
4. Q4 and Q5 have been added to the LM105 to form a 
common-collector, common-base, common-emitter amplifi- 
er, rather than the single common-emitter differential ampli- 
fier of the LM 100. 

In the LM100, generation of the reference voltage starts 
with zener diode, D1 , which is supplied with a fixed current 
from one of the collectors of Q2. This regulated voltage, 
which has a positive temperature coefficient, is buffered by 




UNREGULATEO INPUT 



BOOSTER OUTPUT 



CURRENT LIMIT 



REGULATED OUTPUT 



COMPENSATION/ 
SHUTOOWN 



REFERENCE BYPASS 



GROUND 

TL/H/6906- 



Figure 4. Schematic diagram of the LM105 regulator 

Q4, divided down by R1 and R2 and connected in series 
with a diode-connected transistor, Q7. The negative temper- 
ature coefficient of Q7 cancels out the positive coefficient of 
the voltage across R2, producing a temperature-compen- 
sated 1.8V on the base of Q8. This point is also brought 
outside the circuit so that an external capacitor can be add- 
ed to bypass any noise from the zener diode. 
Transistors Q8 and Q9 make up the error amplifier of the 
circuit. A gain of 2000 is obtained from this single stage by 
using a current source, another collector on Q2, as a collec- 
tor load. The output of the amplifier is buffered by Q1 1 and 
used to drive the series-pass transistor, Q12. The collector 
of Q12 is brought out so that an external PNP transistor, or 
PNP— NPN combination, can be added for increased output 
current. 

Current limiting is provided by Q10. When the voltage 
across an external resistor connected between Pins 1 and 8 
becomes high enough to turn on Q10, it removes the base 
drive from Q1 1 so the regulator exhibits a constant-current 
characteristic. Prebiasing the current limit transistor with a 
portion of the emitter-base voltage of Q12 from R6 and R7 
reduces the current limit sense voltage. This increases the 




TL/H/6906-4 



Figure 3. Schematic diagram of the LM100 regulator 



32 



efficiency of the regulator, especially when foldback current 
limiting is used. With foldback limiting, the voltage dropped 
across the current sense resistor is about four times larger 
than the sense voltage. 

As for the remaining details, the collector of the amplifier, 
Q9, is brought out so that external collector-base capaci- 
tance can be added to frequency-stabilize the circuit when it 
is used as a linear regulator. This terminal can also be 
grounded to shut the regulator off. R9 and R4 are used to 
start up the regulator, while the rest of the circuitry estab- 
lishes the proper operating levels for the current source 
transistor, Q2. 

The reference circuitry of the LM105 is the same, except 
that the current through the reference divider, R2, R3 and 
R4, has been reduced by a factor of two on the LM105 for 
reduced power consumption. In the LM105, Q2 and Q3 form 
an emitter coupled amplifier, with Q3 being the emitter-fol- 
lower input and Q2 the common-base output amplifier. R6 is 
the collector load for this stage, which has a voltage gain of 
about 20. The second stage is a differential amplifier, using 
Q4 and Q5. Q5 actually provides the gain. Since it has a 
current source as a collector load, one of the collectors of 
Q12, the gain is quite high: about 1500. This gives a total 
gain in the error amplifier of about 30,000 which is ten times 
higher than the LM100. 

It is not obvious from the schematic, but the first stage (Q2 
and Q3) and second stage (Q4 and Q5) of the error amplifi- 
er are closely balanced when the circuit is operating. This 
will be true regardless of the absolute value of components 
and over the operating temperature range. The only thing 
affecting balance is component matching, which is good in a 
monolithic integrated circuit, so the error amplifier has good 
drift characteristics over a wide temperature range. 
Frequency compensation is accomplished with an external 
integrating capacitor around the error amplifier, as with the 
LM100. This scheme makes the stability insensitive to load- 
ing conditions — resistive or reactive — while giving good 
transient response. However, an internal capacitor, C1, is 
added to prevent minor-loop oscillations due to the in- 
creased gain. 

Additional differences between the LM100 and LM105 are 
that a field-effect transistor, Q1 8, connected as a current 
source starts the regulator when power is first applied. 
Since this current source is connected to ground, rather 
than the output, the minimum load current before the regula- 
tor drops out of operation with large input-output voltage 
differentials is greatly reduced. This also minimizes power 
dissipation in the integrated circuit when the difference be- 
tween the input and output voltage is at the worst-case val- 
ue. With the LM105 circuit configuration, it was also neces- 
sary to add Q17 to eliminate a latch-up mechanism which 
could exist with lower output-voltage settings. Without Q1 7, 
this could occur when Q3 saturated and cut off the second 
stage amplifiers, Q4 and Q5, causing the output to latch at a 
voltage nearly equal to the unregulated input. 



power limitations 

Although it is desirous to put as much of the regulator as 
possible on the IC chip, there are certain basic limitations. 
For one, it is not a good idea to put the series pass transis- 
tor on the chip. The power that must be dissipated in the 
pass transistor is too much for practical IC packages. Fur- 
ther, IC's must be rated at a lower maximum operating tem- 
perature than power transistors. This means that even with 
a power package, a more massive heat sink would be re- 
quired if the pass transistor was included in the IC. 
Assuming that these problems could be solved, it is still not 
advisable to put the pass transistor on the same chip with 
the reference and control circuitry: changes in the unregu- 
lated input voltage or load current produce gross variations 
in chip temperature. These variations worsen load and line 
regulation due to temperature interaction with the control 
and reference circuitry. 

To elaborate, it is reasonable to neglect the package prob- 
lem since it is potentially solvable. The lower, maximum op- 
erating temperatures of IC's, however, present a more basic 
problem. The control circuitry in an IC regulator runs at fairly 
low currents. As a result, it is more sensitive to leakage 
currents and other phenomena which degrades the per- 
formance of semiconductors at high temperatures. Hence, 
the maximum operating temperature is limited to 150"C in 
military temperature range applications. On the other hand, 
a power transistor operating at high currents may be run at 
temperatures up to 200°C, because even a 1 mA leakage 
current would not affect its operation in a properly designed 
circuit. Even if the pass transistor developed a permanent 
1 mA leakage from channeling, operating under these con- 
ditions of high stress, it would not affect circuit operation. 
These conditions would not trouble the pass transistor, but 
they would most certainly cause complete failure of the con- 
trol circuitry. 

These problems are not eliminated in applications with a 
lower maximum operating temperature. Integrated circuits 
are sold for limited temperature range applications at con- 
siderably lower cost. This is mainly based on a lower maxi- 
mum junction temperature. They may be rated so that they 
do not blow up at higher temperatures, but they are not 
guaranteed to operate within specifications at these temper- 
atures. Therefore, in applications with a lower maximum am- 
bient temperature, it is necessary to purchase an expensive 
full temperature range part in order to take advantage of the 
theoretical maximum operating temperatures of the IC. 
Figure 5 makes the point about dissipation limitations more 
strongly. It gives the maximum short circuit output current 
for an IC regulator in a TO-5 package, assuming a 25°C 
temperature rise between the chip and ambient and a quies- 
cent current of 2 mA. Dual-in-line or flat packages give re- 
sults which are, at best, slightly better, but are usually 
worse. If the short circuit current is not of prime concern, 
Figure 5 can also be used to give the maximum output cur- 
rent as a function of input-output voltage differential, How- 
ever, the increased dissipation due to the quiescent current 
flowing at the maximum input voltage must be taken into 
account. In addition, the input-output differential must be 
measured with the maximum expected input voltages. 



33 



su 












n 


I' 
TO 5 li 


_ 40 

> 










I 














V.INF 


INITE HEAT 
K-SOOmW 


cs 

? 30 










\sw 


o 
















1 20 


NO HEAT SINKS 








167 mW 

I i 


I 








10 


I I 
AT = 25° C 










"o = 


2 mA 











1.0 10 100 

OUTPUT CURRENT (mA) 

TL/H/6906-6 

Figure 5. Dissipation limited short circuit output current 
for an IC regulator in a TO-5 package 

The 25°C temperature rise assumed in arriving at Figure 5 is 
not at all unreasonable. With military temperature range 
parts, this is valid for a maximum junction temperature of 
150°C with a 125°C ambient. For low cost parts, marketed 
for limited temperature range applications, this maximum 
differential appropriately derates the maximum junction tem- 
perature. 

In practical designs, the maximum permissible dissipation 
will always be to the left of the curve shown for an infinite 
heat sink in Figure 5. This curve is realized with the package 
immersed in circulating acetone, freon or mineral oil. Most 
heat sinks are not quite as good. 

To summarize, power transistors can be run with a tempera- 
ture differential, junction to ambient, 3 to 5 times as great as 
an integrated circuit. This means that they can dissipate 
much more power, even with a smaller heat sink. This, cou- 
pled with the fact that low cost, multilead power packages 
are not available and that there can be thermal interactions 
between the control circuitry and the pass transistor, strong- 
ly suggests that the pass transistors be kept separate from 
the integrated circuit. 

using booster transistors 

Figure 6 shows how an external pass transistor is added to 
the LM105. The addition of an external PNP transistor does 
not increase the minimum input output voltage differential. 

■ v OUT = sv 




This would happen if an NPN transistor was used in a com- 
pound emitter follower connection with the NPN output tran- 
sistor of the IC. A single-diffused, wide base transistor like 
the 2N3740 is recommended because it causes fewer oscil- 
lation problems than double-diffused, planar devices. In ad- 
dition, it seems to be less prone to failure under overload 
conditions; and low cost devices are available in power 
packages like the TO-66 or even TO-3. 
When the maximum dissipation in the pass transistor is less 
than about 0.5W, a 2N2905 may be used as a pass transis- 
tor. However, it is generally necessary to carefully observe 
thermal deratings and provide some sort of heat sink. 
In the circuit of Figure 6, the output voltage is determined by 
R1 and R2. The resistor values are selected based on a 
feedback voltage of 1.8V to Pin 6 of the LM105. To keep 
thermal drift of the output voltage within specifications, the 
parallel combination of R1 and R2 should be approximately 
2K. However, this resistance is not critical. Variations of 
±30% will not cause an appreciable degradation of temper- 
ature drift. 

The 1 ju.F output capacitor, C2, is required to suppress oscil- 
lations in the feedback loop involving the external booster 
transistor, Q1, and the output transistor of the LM105. C1 
compensates the internal regulator circuitry to make the sta- 
bility independent for all loading conditions. C3 is not nor- 
mally required if the lead length between the regulator and 
the output filter of the rectifier is short. 
Current limiting is provided by R3. The current limit resistor 
should be selected so that the maximum voltage drop 
across it, at full load current, is equal to the voltage given in 
Figure 7 at the maximum junction temperature of the IC. 
This assures a no load to full load regulation better than 
0.1% under worst-case conditions. 















































■o 


< 


2r 


nA 















































































































































































Figure 6. 0.2A regulator 



20 40 60 80 100 120 140 160 
JUNCTION TEMPERATURE CO 

TL/H/6906-8 

Figure 7. Maximum voltage drop across current limit re- 
sistor at full load for worst case load regula- 
tion of 0.1% 

The short circuit output current is also determined by R3. 
Figure 8 shows the voltage drop across this resistor, when 
the output is shorted, as a function of junction temperature 
in the IC. 

With the type of current limiting used in Figure 6, the dissipa- 
tion under short circuit conditions can be more than three 
times the worst-case full load dissipation. Hence, the heat 



34 



> 




















< 

5 0.5 

o 

> 






































UJ 

£ 0.4 
tn 






































X 

£ 0.3 

Ul 

cc 






































cc 

S 0.2 





















-75 -50 -25 25 50 75 100 125 150 
JUNCTION TEMPERATURE (°C) 

TL/H/6906-9 

Figure 8. Voltage drop across current limit resistor re- 
quired to initiate current limiting 

sink for the pass transistor must be designed to accommo- 
date the increased dissipation if the regulator is to survive 
more than momentarily with a shorted output. It is encourag- 
ing to note, however, that the short circuit current will de- 
crease at higher ambient temperatures. This assists in pro- 
tecting the pass transistor from excessive heating. 

foldback current limiting 

With high current regulators, the heat sink for the pass tran- 
sistor must be made quite large in order to handle the power 
dissipated under worst-case conditions. Making it more than 
three times larger to withstand short circuits is sometimes 
inconvenient in the extreme. This problem can be solved 
with foldback current limiting, which makes the output cur- 
rent under overload conditions decrease below the full load 
current as the output voltage is pulled down. The short cir- 
cuit current can be made but a fraction of the full load cur- 
rent. 

A high current regulator using foldback limiting is shown in 
Figure 9. A second booster transistor, Q1, has been added 
to provide 2A output current without causing excessive dis- 
sipation in the LM105. The resistor across its emitter base 
junction bleeds off any collector base leakage and estab- 
lishes a minimum collector current for Q2 to make the circuit 
easier to stabilize with light loads. The foldback characteris- 
tic is produced with R4 and R5. The voltage across R4 
bucks out the voltage dropped across the current sense 
resistor, R3. Therefore, more voltage must be developed 
across R3 before current limiting is initiated. After the output 
voltage begins to fall, the bucking voltage is reduced, as it is 
proportional to the output voltage. With the output shorted, 



the current is reduced to a value determined by the current 
limit resistor and the current limit sense voltage of the 
LM105. 

16 

















/, 






















LIMITING 


f-i 








1 I 1 






u 








III A A 

NORMAL ' f 


l\ 








/ 






SOURCE | 






/ 




/ / 

4' 


'LOAD 


LINE 


~7 




/' 












u 


s> 






OPERATING POINT 



0.5 



1.0 



1.5 



OUTPUT CURRENT (A) 

TL/H/6906-11 

Figure 10. Limiting characteristics of regulator using 
foldback current limiting 

Figure 10 illustrates the limiting characteristics. The circuit 
regulates for load currents up to 2A. Heavier loads will 
cause the output voltage to drop, reducing the available cur- 
rent. With a short on the output, the current is only 0.5A. 
In design, the value of R3 is determined from 



R3 = — , 
!sc ' 



(1) 



where V| im is the current limit sense voltage of the LM105, 
given in Figure 8, and Isc is the design value of short circuit 
current. R5 is then obtained from 



R 5 



VoUT + V s 



(2) 



'bleed + 'bias 

where Vout is the regulated output voltage, V sense is maxi- 
mum voltage across the current limit resistor for 0.1 % regu- 
lation as indicated in Figure 7, l bteed is the preload current 
on the regulator output provided by R5 and lt,j as is the maxi- 
mum current coming out of Pin 1 of the LM105 under full 
load conditions. I^ias will be equal to 2 mA plus the worst- 
case base drive for the PNP booster transistor, Q2. Ibieed 
should be made about ten times greater than lt,j as . 
Finally, R4 is given by 

D _ *FL ^3 ~ Vsense ,_. 

H 4 j , (3) 

'bleed 

where Ifl is the output current of the regulator at full load. 







61 * 


* M 


qi S \ 








02* 
2N2905. 




— (? 




±C3t 
^1,iF 




R5^ 
360 











LM105 



-f— Vout - 1 

J±C2t 
"P 4-7 nf 



Figure 9. 2A regulator with foldback current limiting 



tSolid tantalum 
tFerroxcube K5-001-00/3B 

TL/H/6906-10 



35 



It is recommended that a ferrite bead be strung on the emit- 
ter of the pass transistor, as shown in Figure 9, to suppress 
oscillations that may show up with certain physical configu- 
rations. It is advisable to also include C4 across the current 
limit resistor. 

In some applications, the power dissipated in Q2 becomes 
too great for a 2N2905 under worst-case conditions. This 
can be true even if a heat sink is used, as it should be in 
almost all applications. When dissipation is a problem, the 
2N2905 can be replaced with a 2N3740. With a 2N3740, the 
ferrite bead and C4 are not needed because this transistor 
has a lower cutoff frequency. 

One of the advantages of foldback limiting is that it sharp- 
ens the limiting characteristics of the IC. In addition, the 
maximum output current is less sensitive to variations in the 
current limit sense voltage of the IC: in this circuit, a 20% 
change in sense voltage will only affect the trip current by 
5%. The temperature sensitivity of the full load current is 
likewise reduced by a factor of four, while the short circuit 
current is not. 

Even though the voltage dropped across the sense resistor 
is larger with foldback limiting, the minimum input-output 
voltage differential of the complete regulator is not in- 
creased above the 3V specified for the LM105 as long as 
this drop is less than 2V. This can be attributed to the low 
sense voltage of the IC by itself. 

Figure 10 shows that foldback limiting can only be used with 
certain kinds of loads. When the load looks predominately 
like a current source, the load line can intersect the foldback 
characteristic at a point where it will prevent the regulator 
from coming up to voltage, even without an overload. Fortu- 
nately, most solid state circuitry presents a load line which 
does not intersect. However, the possibility cannot be ig- 
nored, and the regulator must be designed with some 
knowledge of the load. 

With foldback limiting, power dissipation in the pass transis- 
tor reaches a maximum at some point between full load and 



short circuited output. This is illustrated in Figure 1 1. Howev- 
er, if the maximum dissipation is calculated with the worst- 
case input voltage, as it should be, the power peak is not 
too high. 

25 





























































































































V, N =25V 














l FL = 2.0A- 














I I 















2 4 6 8 10 12 14 16 
OUTPUT VOLTAGE (V) 

TL/H/6906-12 

Figure 11. Power dissipation in series pass transistors 
under overload conditions in regulator using 
foldback current limiting 

high current regulator 

The output current of a regulator using the LM105 as a con- 
trol element can be increased to any desired level by adding 
more booster transistors, increasing the effective current 
gain of the pass transistors. A circuit for a 1 0A regulator is 
shown in Figure 12. A third NPN transistor has been includ- 
ed to get higher current. A low frequency device is used for 
Q3 because it seems to better withstand abuse. However, 
high frequency transistors must be used to drive it. Q2 and 
Q3 are both double-diffused transistors with good frequency 
response. This insures that Q3 will present the dominant lag 
in the feedback loop through the booster transistors, and 
back around the output transistor of the LM105. This is fur- 
ther insured by the addition of C3. 



C3 T 

3.3 nf 

15V 




~ tSolid tantalum 
•Electrolytic 



TL/H/6906-13 



Figure 12. 10A regulator with foldback current limiting 



36 



The circuit, as shown, has a full load capability of 10A. Fold- 
back limiting is used to give a short circuit output current of 
2.5A. The addition of Q3 increases the minimum input-out- 
put voltage differential, by "IV, to 4V. 

dominant failure mechanisms 

By far, the biggest reason for regulator failures is overdissi- 
pation in the series pass transistors. This has been borne 
out by experience with the LM100. Excessive heating in the 
pass transistors causes them to short out, destroying the IC. 
This has happened most frequently when PNP booster tran- 
sistors in a TO-5 can, like the 2N2905, were used. Even with 
a good heat sink, these transistors cannot dissipate much 
more than 1W. The maximum dissipation is less in many 
applications. When a single PNP booster is used and power 
can be a problem, it is best to go to a transistor like the 
2N3740, in a TO-66 power package, using a good heat sink. 
Using a compound PNP/NPN booster does not solve all 
problems. Even when breadboarding with transistors in TO- 
3 power packages, heat sinks must be used. The TO-3 
package is not very good, thermally, without a heat sink. 
Dissipation in the PNP transistor driving the NPN series 
pass transistor cannot be ignored either. Dissipation in the 
driver with worst-case current gain in the pass transistor 
must be taken into account. In certain cases, this could re- 
quire that a PNP transistor in a power package be used to 
drive the NPN pass transistor. In almost all cases, a heat 
sink is required if a PNP driver transistor in a TO-5 package 
is selected. 

With output currents above 3A, it is good practice to replace 
a 2N3055 pass transistor with a 2N3772. The 2N3055 is 
rated for higher currents than 3A, but its current gain falls off 
rapidly. This is especially true at either high temperatures or 
low input-output voltage differentials. A 2N3772 will give 
substantially better performance at high currents, and it 
makes life much easier for the PNP driver. 
The second biggest cause of failures has been the output 
filter capacitors on power inverters providing unregulated 
power to the regulator. If these capacitors are operated with 
excessive ripple across them, and simultaneously near their 
maximum dc voltage rating, they will sputter. That is, they 
short momentarily and clear themselves. When they short, 
the output capacitor of the regulator is discharged back 



through the reverse biased pass transistors or the control 
circuitry, frequently causing destruction. This phenomenon 
is especially prevalent when solid tantalum capacitors are 
used with high-frequency power inverters. The maximum 
ripple allowed on these capacitors decreases linearly with 
frequency. 

The solution to this problem is to use capacitors with con- 
servative voltage ratings. In addition, the maximum ripple 
allowed by the manufacturer at the operating frequency 
should also be observed. 

The problem can be eliminated completely by installing a 
diode between the input and output of the regulator such 
that the capacitor on the output is discharged through this 
diode if the input is shorted. A fast switching diode should 
be used as ordinary rectifier diodes are not always effective. 
Another cause of problems with regulators is severe voltage 
transients on the unregulated input. Even if these transients 
do not cause immediate failure in the regulator, they can 
feed through and destroy the load. If the load shorts out, as 
is frequently the case, the regulator can be destroyed by 
subsequent transients. 

This problem can be solved by specifying all parts of the 
regulator to withstand the transient conditions. However, 
when ultimate reliability is needed, this is not a good solu- 
tion. Especially since the regulator can withstand the tran- 
sient, yet severely overstress the circuitry on its output by 
feeding the transients through. Hence, a more logical re- 
course is to include circuitry which suppresses the tran- 
sients. A method of doing this is shown in Figure 13. A zener 
diode, which can handle large peak currents, clamps the 
input voltage to the regulator while an inductor limits the 
current through the zener during the transient. The size of 
the inductor is determined from 



L = 



AVAt 
I 



(4) 



where AV is the voltage by which the input transient ex- 
ceeds the breakdown voltage of the diode, At is the dura- 
tion of the transient and I is the peak current the zener can 
handle while still clamping the input voltage to the regulator. 
As shown, the suppression circuit will clamp 70V, 4 ms tran- 
sients on the unregulated supply. 




REGULATORS 



•Unitrode TL/H/6906-14 

Figure 13. Suppression circuitry to remove large voltage spikes from unregulated supplies 



37 



conclusions 

The LM105 is an exact replacement for the LM100 in the 
majority of applications, providing about ten times better 
regulation. There are, however, a few differences: 
In switching regulator applications, 2 the size of the resistor 
used to provide positive feedback should be doubled as the 
impedance seen looking back into the reference bypass ter- 
minal is twice that of the LM100 (2 kft versus 1 kH). In 
addition, the minimum output voltage of the LM105 is 4.5V, 
compared with 2V for the LM100. In low voltage regulator 
applications, the effect of this is obvious. However, it also 
imposes some limitations on current regulator and shunt 
regulator designs. 3 Lastly, clamping the compensation ter- 
minal (Pin 7) within a diode drop of ground or the output 
terminal will not guarantee that the regulator is shut off, as it 
will with the LM100. This restricts the LM105 in the overload 
shutoff schemes 3 which can be used with the LM100. 
Dissipation limitations of practical packages dictate that the 
output current of an IC regulator be less than 20 mA. How- 
ever, external booster transistors can be added to get any 
output current desired. Even with satisfactory packages, 
considerably larger heat sinks would be needed if the pass 
transistors were put on the same chip as the reference and 
control circuitry, because an IC must be run at a lower maxi- 
mum temperature than a power transistor. In addition, heat 
dissipated in the pass transistor couples into the low level 
circuitry and degrades performance. All this suggests that 
the pass transistor be kept separate from the IC. 



Overstressing series pass transistors has been the biggest 
cause of failures with IC regulators. This not only applies to 
the transistors within the IC, but also to the external booster 
transistors. Hence, in designing a regulator, it is of utmost 
importance to determine the worst-case power dissipation 
in all the driver and pass transistors. Devices must then be 
selected which can handle the power. Further, adequate 
heat sinks must be provided as even power transistors can- 
not dissipate much power by themselves. 
Normally, the highest power dissipation occurs when the 
output of the regulator is shorted. If this condition requires 
heat sinks which are so large as to be impractical, foldback 
current limiting can be used. With foldback limiting, the pow- 
er dissipated under short circuit conditions can actually be 
made less than the dissipation at full load. 
The LM105 is designed primarily as a positive voltage regu- 
lator. A negative regulator, the LM104, which is a functional 
complement to the LM105, is described in Reference 4. 

references 

1 . R. J. Widlar, "A Versatile, Monolithic Voltage Regulator", 
National Semiconductor AN-1 ', February, 1967. 

2. R. J. Widlar, "Designing Switching Regulators," National 
Semiconductor AN-2, April, 1967. 

3. R. J. Widlar, "New Uses for the LM100 Regulator," Na- 
tional Semiconductor AN-8, June, 1968. 

4. R. J. Widlar, "Designs for Negative Voltage Regulators," 
National Semiconductor AN-21 , October, 1968. 



38 



A Simplified Test Set for Op 
Amp Characterization 



National Semiconductor 
Application Note 24 
M. Yamatake 




INTRODUCTION 

The test set described in this paper allows complete quanti- 
tative characterization of all dc operational amplifier param- 
eters quickly and with a minimum of additional equipment. 
The method used is accurate and is equally suitable for lab- 
oratory or production test— for quantitative readout or for 
limit testing. As embodied here, the test set is conditioned 
for testing the LM709 and LM101 amplifiers; however, sim- 
ple changes discussed in the text will allow testing of any of 
the generally available operational amplifiers. 
Amplifier parameters are tested over the full range of com- 
mon mode and power supply voltages with either of two 
output loads. Test set sensitivity and stability are adequate 
for testing all presently available integrated amplifiers. 
The paper will be divided into two sections, i.e., a functional 
description, and a discussion of circuit operation. Complete 
construction information will be given including a layout for 
the tester circuit boards. 

FUNCTIONAL DESCRIPTION 

The test set operates in one of three basic modes. These 
are: (1) Bias Current Test; (2) Offset Voltage, Offset Current 
Test; and (3) Transfer Function Test. In the first two of these 
tests, the amplifier under test is exercised throughout its full 
common mode range. In all three tests, power supply volt- 
ages for the circuit under test may be set at ±5V, ± 10V, 
± 15V, or ±20V. 



POWER SUPPLY 

Basic waveforms and dc operating voltages for the test set 
are derived from a power supply section comprising a posi- 
tive and a negative rectifier and filter, a test set voltage 
regulator, a test circuit voltage regulator, and a function gen- 
erator. The dc supplies will be discussed in the section deal- 
ing with detailed circuit description. 
The waveform generator provides three output functions, a 
± 1 9V square wave, a - 1 9V to + 1 9V pulse with a 1 % duty 
cycle, and a ± 5V triangular wave. The square wave is the 
basic waveform from which both the pulse and triangular 
wave outputs are derived. 

The square wave generator is an operational amplifier con- 
nected as an astable multivibrator. This amplifier provides 
an output of approximately ±19V at 16 Hz. This square 
wave is used to drive junction FET switches in the test set 
and to generate the pulse and triangular waveforms. 
The pulse generator is a monostable multivibrator driven by 
the output of the square wave generator. This multivibrator 
is allowed to swing from negative saturation to positive satu- 
ration on the positive going edge of the square wave input 
and has a time constant which will provide a duty cycle of 
approximately 1%. The output is approximately -19V to 
+ 19V. 




FIGURE 1. Functional Diagram of Bias Current Test Circuit 



39 



The triangular wave generator is a dc stabilized integrator 
driven by the output of the square wave generator and pro- 
vides a ± 5V output at the square wave frequency, inverted 
with respect to the square wave. 

The purpose of these various outputs from the power supply 
section will be discussed in the functional description. 

BIAS CURRENT TEST 

A functional diagram of the bias current test circuit is shown 
in Figure 1. The output of the triangular wave generator and 
the output of the test circuit, respectively, drive the horizon- 
tal and vertical deflection of an oscilloscope. 
The device under test, (cascaded with the integrator, A7), is 
connected in a differential amplifier configuration by R-j, R2, 
R3, and R4. The inputs of this differential amplifier are driven 
in common from the output of the triangular wave generator 
through attenuator Rg and amplifier k%. The inputs of the 
device under test are connected to the feedback network 
through resistors R5 and Rq, shunted by the switch Ss a and 
Ssb- 

The feedback network provides a closed loop gain of 1 ,000 
and the integrator time constant serves to reduce noise at 
the output of the test circuit as well as allowing the output of 
the device under test to remain near zero volts. 
The bias current test is accomplished by allowing the device 
under test to draw input current to one of its inputs through 
the corresponding input resistor on positive going or nega- 
tive going halves of the triangular wave generator output. 
This is accomplished by closing Ss a or Ssb on alternate 
halves of the triangular wave input. The voltage appearing 
across the input resistor is equal to input current times the 
input resistor. This voltage is multiplied by 1,000 by the 
feedback loop and appears at the integrator output and the 
vertical input of the oscilloscope. The vertical separaton of 
the traces representing the two input currents of the amplifi- 
er under test is equivalent to the total bias current of the 
amplifier under test. 

The bias current over the entire common mode range may 
be examined by setting the output of Ae equal to the amplifi- 
er common mode range. A photograph of the bias current 
oscilloscope display is given as Figure 2. In this figure, the 
total input current of an amplifier is displayed over a ±10V 
common mode range with a sensitivity of 1 00 nA per vertical 
division. 




The bias current display of Figure 2 has the added advan- 
tage that incipient breakdown of the input stage of the de- 
vice under test at the extremes of the common mode range 
is easily detected. 

If either or both the upper or lower trace in the bias current 
display exhibits curvature near the horizontal ends of the 
oscilloscope face, then the bias current of that input of the 
amplifier is shown to be dependent on common mode volt- 
age. The usual causes of this dependency are low break- 
down voltage of the differential input stage or current sink. 

OFFSET VOLTAGE, OFFSET CURRENT TEST 

The offset voltage and offset current tests are performed in 
the same general way as the bias current test. The only 
difference is that the switches S5 a and $$o are closed on 
the same half-cycle of the triangular wave input. 
The synchronous operation of S5 3 and Ssb forces the ampli- 
fier under test to draw its input currents through matched 
high and low input resistors on alternate halves of the input 
triangular wave. The difference between the voltage drop 
across the two values of input resistors is proportional to the 
difference in input current to the two inputs of the amplifier 
under test and may be measured as the vertical spacing 
between the two traces appearing on the face of the oscillo- 
scope. 

Offset voltage is measured as the vertical spacing between 
the trace corresponding to one of the two values of source 
resistance and the zero volt baseline. Switch %§ and Resis- 
tor Rg are a base line chopper whose purpose is to provide 
a baseline reference which is independent of test set and 
oscilloscope drift. S 6 is driven from the pulse output of the 
function generator and has a duty cycle of approximately 
1 % of the triangular wave. 

Figure 3 is a photograph of the various waveforms present- 
ed during this test. Offset voltage and offset current are 
displayed at a sensitivity of 1 mV and 100 nA per division, 
respectively, and both parameters are displayed over a 
common mode range of ± 1 0V. 




TL/H/7190- 

FIGURE 3. Offset Voltage, Offset Current 
and Common Mode Rejection Display 



FIGURE 2. Bias Current and Common 
Mode Rejection Display 



40 




> 
z 

10 



TL/H/7190-4 



FIGURE 4. Functional Diagram of Transfer Function Circuit 



TRANSFER FUNCTION TEST 

A functional diagram of the transfer function test is shown in 
Figure 4. The output of the triangular wave generator and 
the output of the circuit under test, respectively, drive the 
horizontal and vertical inputs of an oscilloscope. 
The device under test is driven by a ±2.5 mV triangular 
wave derived from the ± 5 V output of the triangular wave 
generator through the attenuators Rn, R12. and R-|, R3 and 
through the voltage follower, A7. The output of the device 
under test is fed to the vertical input of an oscilloscope. 
Amplifier A7 performs a dual function in this test. When S7 is 
closed during the bias current test, a voltage is developed 
across C<| equal to the amplifier offset voltage multiplied by 
the gain of the feedback loop. When S7 is opened in the 
transfer function test, the charge stored in C-\ continues to 
provide this offset correction voltage. In addition, A 7 sums 
the triangular wave test signal with the offset correction volt- 
age and applies this sum to the input of the amplifier under 
test through the attenuator R-|, R3. This input sweeps the 
input of the amplifier under test ±2.5 mV around its offset 
voltage. 

Figure 5 is a photograph of the output of the test set during 
the transfer function test. This figure illustrates the function 
of amplifier A7 in adjusting the dc input of the test device so 
that its transfer function is displayed on the center of the 
oscilloscope face. 

The transfer function display is a plot of Vin vs Vout for an 
amplifier. This display provides information about three am- 
plifier parameters: gain, gain linearity, and output swing. 




TL/H/7190-5 

FIGURE 5. Transfer Function Display 

Gain is displayed as the slope, AVout/AVin of the transfer 
function. Gain linearity is indicated change in slope of the 
v OUT /v lN display as a function of output voltage. This dis- 
play is particularly useful in detecting crossover distortion in 
a Class B output stage. Output swing is measured as the 
vertical deflection of the transfer function at the horizontal 
extremes of the display. 



41 



z 
< 



SYSTEM 
-20V 



NOTE: All resistor valves 

in ohms. 

All resistors 1 / 4 W, 5% 

unless specified 

otherwise. 




X. TANTALUM 



TL/H/7190-6 



FIGURE 6. Power Supply and Function Generator 



DETAILED CIRCUIT DESCRIPTION 

POWER SUPPLIES 

As shown in Figure 6, which is a complete schematic of the 
power supply and function generator, two power supplies 
are provided in the test set. One supply provides a fixed 
±20V to power the circuitry in the test set; the other pro- 
vides ± 5V to ± 20V to power the circuit under test. 
The test set power supply regulator accepts + 28V from the 
positive rectifier and filter and provides + 20V through the 
LM100 positive regulator. Amplifier Ai is powered from the 
negative rectifier and filter and operates as a unity gain in- 
verter whose input is + 20V from the positive regulator, and 
whose output is -20V. 

The test circuit power supply is referenced to the + 20V 
output of the positive regulator through the variable divider 



comprising R7, Rs, R9, R10. and R26- The output of this 
divider is + 10V to +2.5V according to the position of S2a 
and is fed to the non-inverting, gain-of-two amplifier, A2. A2 
is powered from + 28V and provides + 20V to + 5V at its 
output. A3 is a unity gain inverter whose input is the output 
of A2 and which is powered from -28V. The complementa- 
ry outputs of amplifiers A2 and A3 provide dc power to the 
circuit under test. 

LM101 amplifiers are used as A2 and A3 to allow operation 
from one ground referenced voltage each and to provide 
protective current limiting for the device under test. 

FUNCTION GENERATOR 

The function generator provides three outputs, a ±19V 
square wave, a - 1 9V to + 1 9V pulse having a 1 % duty 
cycle, and a ± 5V triangular wave. The square wave is the 



42 



basic function from which the pulse and triangular wave are 
derived, the pulse is referenced to the leading edge of the 
square wave, and the triangular wave is the inverted and 
integrated square wave. 

Amplifier A4 is an astable multivibrator generating a square 
wave from positive to negative saturation. The amplitude of 
this square wave is approximately ± 1 9V. The square wave 
frequency is determined by the ratio of Rig to R16 and by 
the time constant, R17C9. The operating frequency is stabi- 
lized against temperature and power regulation effects by 
regulating the feedback signal with the divider R-19, D5 and 
D 6 - 

Amplifier A5 is a monostable multivibrator triggered by the 
positive going output of A 4 . The pulse width of A5 is deter- 
mined by the ratio of R20 to R 2 2 and by the time constant 
R 2iC-ir> The output pulse of A5 is an approximately 1 % duty 
cycle pulse from approximately - 1 9V to +1 9V. 
Amplifier A6 is a dc stabilized integrator driven from the am- 
plitude-regulated output of A4. Its output is a + 5V triangular 
wave. The amplitude of the output of Ag is determined by 
the square wave voltage developed across D5 and Dg and 
the time constant R ac jj C14. DC stabilization is accomplished 
by the feedback network R24, R25, and C15. The ac attenua- 
tion of this feedback network is high enough so that the 
integrator action at the square wave frequency is not de- 
graded. 

Operating frequency of the function generator may be var- 
ied by adjusting the time constants associated with A 4 , A5, 
and A6 in the same ratio. 

TEST CIRCUIT 

A complete schematic diagram of the test circuit is shown in 
Figure 7. The test circuit accepts the outputs of the power 
supplies and function generator and provides horizontal and 
vertical outputs for an X-Y oscilloscope, which is used as 
the measurement system. 

The primary elements of the test circuit are the feedback 
buffer and integrator, comprising amplifier A7 and its feed- 
back network C-|6, R31. R32. and C17, and the differential 
amplifier network, comprising the device under test and the 
feedback network R40, R43, R44, and R52. The remainder of 
the test circuit provides the proper conditioning for the de- 
vice under test and scaling for the oscilloscope, on which 
the test results are displayed. 

The amplifier Ag provides a variable amplitude source of 
common mode signal to exercise the amplifier under test 
over its common mode range. This amplifier is connected as 
a non-inverting gain-of-3.6 amplifier and receives its input 
from the triangular wave generator. Potentiometer R 37 al- 
lows the output of this amplifier to be varied from ±0 volts 
to ± 1 8 volts. The output of this amplifier drives the differen- 
tial input resistors, R43 and R44, for the device under test. 
The resistors R46 and R47 are current sensing resistors 
which sense the input current of the device under test. 
These resistors are switched into the circuit in the proper 
sequence by the field effect transistors Q6 and Q7. Q$ and 
Q7 are driven from the square wave output of the function 
generator by the PNP pair, Q10 and Q-n, and the NPN pair, 
Qs and Q9. Switch sections S-ib and S-| C select the switch- 
ing sequence for Qg and Qg and hence for Q6 and Q7. In 
the bias current test, the FET drivers, Qg and Qg, are 
switched by out of phase signals from Q-irj and Q^. This 
opens the FET switches Q6 and Q7 on alternate half cycles 
of the square wave output of the function generator. During 
the offset voltage, offset current test, the FET drivers are 



operated synchronously from the output of Q1 1 . During the 
transfer function test, Qq and Q7 are switched on continu- 
ously by turning off Qn. R42 and R45 maintain the gates of 
the FET switches at zero gate to source voltage for maxi- 
mum conductance during their on cycle. Since the sources 
of these switches are at the common mode input voltage of 
the device under test, these resistors are connected to the 
output of the common mode driver amplifier, Ag. 
The input for the integrator-feedback buffer, A7, is selected 
by the FET switches Q4 and Q5. During the bias current and 
offset voltage offset current tests, A7 is connected as an 
integrator and receives its input from the output of the de- 
vice under test. The output of A7 drives the feedback resis- 
tor, R40. In this connection, the integrator holds the output 
of the device under test near ground and serves to amplify 
the voltages corresponding to bias current, offset current, 
and offset voltage by a factor of 1 ,000 before presenting 
them to the measurement system. FET switches Q4 and Q5 
are turned on by switch section S^ during these tests. 
FET switches Q4 and Q5 are turned off during the transfer 
function test. This disconnects A7 from the output of the 
device under test and changes it from an integrator to a 
non-inverting unity gain amplifier driven from the triangular 
wave output of the function generator through the attenua- 
tor R33 and R34 and switch section S-| a . In this connection, 
amplifier A7 serves two functions; first, to provide an offset 
voltage correction to the input of the device under test and, 
second, to drive the input of the device under test with a 
± 2.5 mV triangular wave centered about the offset voltage. 
During this test, the common mode driver amplifier is dis- 
abled by switch section S-| a and the vertical input of the 
measurement oscilloscope is transferred from the output of 
the integrator-buffer, A7, to the output of the device under 
test by switch section S^- S2 9 allows supply voltages for 
the device under test to be set at ± 5, ± 1 0, ± 1 5, or ± 20V. 
S2b changes the vertical scale factor for the measurement 
oscilloscope to maintain optimum vertical deflection for the 
particular power supply voltage used. S4 is a momentary 
contact pushbutton switch which is used to change the load 
on the device under test from 10 kft to 2 kft. 
A delay must be provided when switching from the input 
tests to the transfer function tests. The purpose of this delay 
is to disable the integrator function of A7 before driving it 
with the triangular wave. If this is not done, the offset cor- 
rection voltage, stored on C-ig. will be lost. This delay be- 
tween opening FET switch Q4, and switch Q5, is provided by 
the RC filter, R 35 and C 19 . 

Resistor R41 and diodes D7 and Ds are provided to control 
the integrator when no test device is present, or when a 
faulty test device is inserted. R41 provides a dc feedback 
path in the absence of a test device and resets the integra- 
tor to zero. Diodes D7 and Dg clamp the input to the integra- 
tor to approximately ± .7 volts when a faulty device is inserted. 
FET switch Q-| and resistor R 2 g provide a ground reference 
at the beginning of the 50-ohm-source, offset-voltage trace. 
This trace provides a ground reference which is indepen- 
dent of instrument or oscilloscope calibration. The gate of 
Qi is driven by the output of monostable multivibrator A5, 
and shorts the vertical oscilloscope drive signal to ground 
during the time that A5 output is positive. 
Switch S3, R27, and R 2 g provide a 5X scale increase during 
input parameter tests to allow measurement of amplifiers 
with large offset voltage, offset current, or bias current. 
Switch S5 allows amplifier compensation to be changed for 
101 or 709 type amplifiers. 



43 




;.|10K (SCALE! 

fnx v/oiv 

'RESISTORS ON 



ALL RESISTOR VALUES IN OHMS 



NOTE: All resistors 1/4W, 5% unless specified otherwise '2N3819 

matched for on resistance within 200n Select for BV GS > 4 5V 

FIGURE 7. Test Circuit 



CALIBRATION 

Calibration of the test system is relatively simple and re- 
quires only two adjustments. First, the output of the main 
regulator is set up for 20V. Then, the triangular wave gener- 
ator is adjusted to provide ±5V output by selecting R aC |j. 
This sets the horizontal sweep for the X-Y oscilloscope 
used as the measurement system. The oscilloscope is then 
set up for 1 V/division vertical and for a full 10 division hori- 
zontal sweep. 
Scale factors for the three test positions are: 

1. Bias Current Display (Figure 2) 

Ibias total 1 00 nA/div. vertical 

Common Mode Voltage Variable horizontal 

2. Offset Voltage-Offset Current (Figure 3) 

l offset 100 nA/div. vertical 

V ff Se t 1 mV/div. vertical 

Common Mode Voltage Variable horizontal 



3. Transfer Function (Figure 5) 
Vin 
VrjUT 





TL/H/7190-7 


0.5 mV/div. 




5V/div. @ V s 


±20V 


5V/div. @ V s 


±15V 


2V/div. @ V s 


±10V 


1V/div. @ V s 


+ 5V 



Gain 



AVquT 



AV| N 

CONSTRUCTION 

Test set construction is simplified through the use of inte- 
grated circuits and etched circuit layout. 
Figure 8 gives photographs of the completed tester. Figure 
9 shows the parts location for the components on the circuit 
board layout of Figure 10. An attempt should be made to 



44 



adhere to this layout to insure that parasitic coupling be- 
tween elements will not cause oscillations or give calibration 
problems. 

Table I is a listing of special components which are needed 
to fit the physical layout given for the tester. 
TABLE I. Partial Parts List 
Ti Triad F-90X 

St Centralab PA2003 non-shorting 
S 2 Centralab PA201 5 non-shorting 



S3, S4 Grayhill 30-1 Series 30 subminiature 

pushbutton switch 
S 5) S 6 Alcoswitch MST-105D SPDT 

CONCLUSIONS 

A semi-automatic test system has been described which will 
completely test the important operational amplifier parame- 
ters over the full power supply and common mode ranges. 
The system is simple, inexpensive, easily calibrated, and is 
equally suitable for engineering or quality assurance usage. 



IS3 




TL/H/7190-8 



FIGURE 8a. Bottom of Test Set 



45 



C>1 

Z 

< 




TL/H/7190-9 



FIGURE 8b. Front Panel 




TL/H/7190-10 



FIGURE 8c. Jacks 



46 



— {radjust) — 
«o~« — - IbadjostV — 

SCOPE ■ » 



HORIZONTAL" 

TERMINAL 

1V/DIV 




•-♦SlbT.F. L_».S1c 
'-♦■Slclb L "^S1cT.F 



> 

Z 
ro 



Slcl 

V OS. 'oS 



TL/H/7190-11 



FIGURE 9. Component Location, Top View 



47 




TL/H/7190-12 



FIGURE 10. Circuit Board Layout 



48 



IC Op Amp Beats FETs 
on Input Current 

Robert J. Widlar 
Apartado Postal 541 
Puerto Vallarta, Jalisco 
Mexico 

abstract 

A monolithic operational amplifier having input error cur- 
rents in the order of 100 pA over a - 55°C to 125°C temper- 
ature range is described. Instead of FETs, the circuit used 
bipolar transistors with current gains of 5000 so that offset 
voltage and drift are not degraded. A power consumption of 
1 mW at low voltage is also featured. 
A number of novel circuits that make use of the low current 
characteristics of the amplifier are given. Further, special 
design techniques required to take advantage of these low 
currents are explored. Component selection and the treat- 
ment of printed circuit boards is also covered. 

introduction 

A year ago, one of the loudest complaints heard about IC op 
amps was that their input currents were too high. This is no 
longer the case. Today ICs can provide the ultimate in per- 
formance for many applications — even surpassing FET am- 
plifiers. 

FET input stages have long been considered the best way 
to get low input currents in an op amp. Low-picoamp input 
currents can in fact be obtained at room temperature. How- 
ever, this current, which is the leakage current of the gate 
junction, doubles every 10°C, so performance is severely 
degraded at high temperatures. Another disadvantage is 
that it is difficult to match FETs closely. 1 Unless expensive 
selection and trimming techniques are used, typical offset 
voltages of 50 mV and drifts of 50 (j.V/°C must be tolerated. 
Super gain transistors 2 are now challenging FETs. These 
devices are standard bipolar transistors which have been 
diffused for extremely high current gains. Typically, current 
gains of 5000 can be obtained at 1 fiA collector currents. 
This makes it possible to get input currents which are com- 
petitive with FETs. It is also possible to operate these tran- 
sistors at zero collector base voltage, eliminating the leak- 
age currents that plague the FET. Hence they can provide 
lower error currents at elevated temperatures. As a bonus, 
super gain transistors match much better than FETs with 
typical offset voltages of 1 mV and drifts of 3 jnV/°C. 
Figure 1 compares the typical input offset currents of IC op 
amps and FET amplifiers. Although FETs give superior per- 
formance at room temperature, their advantage is rapidly 
lost as temperature increases. Still, they are clearly better 
than early IC amplifiers like the LM709. 3 Improved devices, 
like the LM101A, 4 equal FET performance over a -55°C to 
1 25°C temperature range. Yet they use standard transistors 
in the input stage. Super gain transistors can provide more 
than an order of magnitude improvement over the LM101A. 
The LM108 uses these to equal FET performance over a 
0°C to 70°C temperature range. 

In applications involving 125°C operation, the LM108 is 
about two orders of magnitude better than FETs. In fact, 
unless special precautions are taken, overall circuit perform- 
ance is often limited by leakages in capacitors, diodes, ana- 



National Semiconductor 
Application Note 29 




CO 



IO" 7 













































































/ 


















— 1 — 








j— 




LM101A 






< 


^ 






















































/ 


FFT 














/ 
















/ 














































1 


( 









10" 

-75 -50 -25 25 50 75 100 125 

TEMPERATURE (°C) 

TL/H/6875-1 

Figure 1. Comparing IC op amps with FET-input amplifier 

log switches or printed circuit boards, rather than by the op 
amp itself. 

effects of error current 

In an operational amplifier, the input current produces a volt- 
age drop across the source resistance, causing a dc error. 
This effect can be minimized by operating the amplifier with 
equal resistances on the two inputs. 5 The error is then pro- 
portional to the difference in the two input currents, or the 
offset current. Since the current gains of monolithic transis- 
tors tend to match well, the offset current is typically a factor 
of ten less than the input currents. 



5 o.i 



^fs 




















T A = 25°C 
























W A 


/ 




m 


f ' 






$/ 






















































3S = Vqs + "s 'os — 












1 1 I 



Ik 



1G 



10k 100k 1M 10M 100M 
INPUT RESISTANCE («) 

TL/H/6875-2 

Figure 2. Illustrating the effect of source resistance on 
typical input error voltage 

Naturally, error current has the greatest effect in high im- 
pedance circuitry. Figure 2 illustrates this point. The offset 
voltage of the LM709 is degraded significantly with source 
resistances greater than 10 kn. With the LM101A this is 
extended to source resistances high as 500 kft. The 
LM108, on the other hand, works well with source resistanc- 
es above 10 Mil. 



Reprinted from EEE, December 1969. 



49 



CM 



High source resistances have an even greater effect on the 
drift of an amplifier, as shown in Figure 3. The performance 
of the LM709 is worsened with sources greater than 3 kft. 
The LM101 A holds out to 100 kft sources, while the LM108 
still works well at 3 Mil. 



*- 10 



1.0 



















































-f/ 




m 


-fa 






■ ***£— 


<H 


- */ 



























































10k 100k INI 10M 100M 
INPUT RESISTANCE (ft) 



1G 



TL/H/6875-3 



Figure 3. Degradation of typical drift characteristics 
with high source resistances 

It is difficult to include FET amplifiers in Figure 3 because 
their drift is initially 50 jaVVC, unless they are selected and 
trimmed. Even though their drift may be well controlled (5 
ju.V7°C) over a limited temperature range, trimmed amplifiers 
generally exhibit a much higher drift over a - 55°C to 1 25°C 
temperature range. At any rate, their average drift rate 
would, at best, be like that of the LM101A where 125°C 
operation is involved. 



Applications that require low error currents include amplifi- 
ers for photodiodes or capacitive transducers, as these usu- 
ally operate at megohm impedance levels. Sample-and- 
hold-circuits, timers, integrators and analog memories also 
benefit from low error currents. For example, with the 
LM709, worst case drift rates for these kinds of circuits is in 
the order of 1.5 V/sec. The LM108 improves this to 3 mv7 
sec— worst case over a -55°C to 125°C temperature 
range. Low input currents are also helpful in oscillators and 
active filters to get low frequency operation with reasonable 
capacitor values. The LM1 08 can be used at a frequency of 
1 Hz with capacitors no larger than 0.01 ju.F. In logarithmic 
amplifiers, the dynamic range can be extended by nearly 60 
dB by going from the LM709 to the LM108. In other applica- 
tions, having low error currents often permits an entirely dif- 
ferent design approach which can greatly simplify circuitry. 

the LM108 

Figure 4 shows a simplified schematic of the LM108. Two 
kinds of NPN transistors are used on the IC chip: super gain 
(primary) transistors which have a current gain of 5000 with 
a breakdown voltage of 4V and conventional (secondary) 
transistors which have a current gain of 200 with an 80V 
breakdown. These are differentiated on the schematic by 
drawing the secondaries with a wider base. 
Primary transistors (Qi and Q2) are used for the input stage; 
and they are operated in a cascode connection with Q5 and 
Qq. The bases of Q5 and Q6 are bootstrapped to the emit- 
ters of Q-\ and Q2 through Q 3 and Q 4 , so that the input 
transistors are operated at zero collector-base voltage. 
Hence, circuit performance is not impaired by the low break- 
down of the primaries, as the secondary transistors stand 




OUTPUT 



Figure 4. Sim plified schematic of the LM108 

50 



off the commom mode voltage. This configuration also im- 
proves the commom mode rejection since the input transis- 
tors do not see variations in the commom mode voltage. 
Further, because there is no voltage across their collector- 
base junctions, leakage currents in the input transistors are 
effectively eliminated. 

The second stage is a differential amplifier using high gain 
lateral PNPs (Q 9 and Q-io)- 6 These devices have current 
gains of 150 and a breakdown voltage of 80V. Ri and R2 
are the collector load resistors for the input stage. Q7 and 
Qe are diode connected laterals which compensate for the 
emitter-base voltage of the second stage so that its operat- 
ing current is set at twice that of the input stage by R4. 
The second stage uses an active collector load (Q15 and 
Q16) to obtain high gain. It drives a complementary class-8 
output stage which gives a substantial load driving capabili- 
ty. The dead zone of the output stage is eliminated by bias- 
ing it on the verge of conduction with Q-^ and Qi2- 
Two methods of frequency compensation are available for 
the amplifier. In one a 30 pF capacitor is connected from the 
input to the output of the second stage (between the com- 
pensation terminals). This method is pin-compatible with the 
LM101 or LM101 A. It can also be compensated by connect- 
ing a 1 00 pF capacitor from the output of the second stage 
to ground. This technique has the advantage of improving 
the high frequency power supply rejection by a factor of ten. 
A complete schematic of the LM108 is given in the Appen- 
dix along with a description of the circuit. This includes such 
essential features as overload protection for the inputs and 
outputs. 

performance 

The primary design objective for the LM108 was to obtain 
very low input currents without sacrificing offset voltage or 
drift. A secondary objective was to reduce the power con- 
sumption. Speed was of little concern, as long as it was 
comparable with the LM709. This is logical as it is quite 
difficult to make high-impedance circuits fast; and low power 
circuits are very resistant to being made fast. In other re- 
spects, it was desirable to make the LM1 08 as much like the 
LM101A as possible. 

2.0 

i.s 
5 1.0 
£ 0.5 

Ui 

£ 

3 
U 

1- 0.15 

s 
a. 

- 0.10 

0.05 


-55 -35 -15 5 25 45 65 85 105 125 

TEMPERATURE (°C) 

TL/H/6875-5 

Figure 5. Input currents 

Figure 5 shows the input current characteristics of the 
LM108 over a -55°C to 125°C temperature range. Not only 
are the input currents low, but also they do not change radi- 
cally over temperature. Hence, the device lends itself to rel- 
atively simple temperature compensation schemes, that will 
be described later. 































AS 
















B 








































- 































FSI 


T 






LM 

__j 


08 















There has been considerable discussion about using Dar- 
lington input stages rather than super gain transistors to 
obtain low input currents. 6 ' 7 It is appropriate to make a few 
comments about that here. 

Darlington inputs can give about the same input bias cur- 
rents as super gain transistors — at room temperature. How- 
ever, the bias current varies as the square of the transistor 
current gain. At low temperatures, super gain devices have 
a decided advantage. Additionally, the offset current of su- 
per gain transistors is considerably lower than Darlingtons, 
when measured as a percentage of bias current. Further, 
the offset voltage and offset voltage drift of Darlington tran- 
sistors is both higher and more unpredictable. 
Experience seems to tell the real truth about Darlingtons. 
Quite a few op amps with Darlington input stages have been 
introduced. However, none have become industry stan- 
dards. The reason is that they are more sensitive to varia- 
tions in the manufacturing process. Therefore, satisfactory 
performance specifications can only be obtained by sacrific- 
ing the manufacturing yield. 



r 400 



£ 300 

3 
U 

5 200 

a. 
a. 

** 100 


















Ta = 


-55°C 






— m 






T A = 


25°C 












Ta = 


125°C 
















LMK 


8 











5 10 15 

SUPPLY VOLTAGE <±V) 

Figure 6. Supply current 



TL/H/6875-6 



The supply current of the LM108 is plotted as a function of 
supply voltage in Figure 6. The operating current is about an 
order of magnitude lower than devices like the LM709. Fur- 
thermore, it does not vary radically with supply voltage 
which means that the device performance is maintained at 
low voltages and power consumption is held down at high 
voltages. 




2 4 6 8 

OUTPUT CURRENT (±mA) 

TL/H/6875-7 

Figure 7. Output swing 

The output drive capability of the circuit is illustrated in Fig- 
ure 7. The output swings to within a volt of the supplies, 



51 



CM 



which is especially important when operating at low volt- 
ages. The output falls off rapidly as the current increases 
above a certain level and the short circuit protection goes 
into effect. The useful output drive is limited to about 
±2 mA. It could have been increased by the addition of 
Darlington transistors on the output, but this would have 
restricted the voltage swing at low supply voltages. The am- 
plifier, incidentally, works with common mode signals to 
within a volt of the supplies so it can be used with supply 
voltages as low as ± 2V. 







1 


| | 






Cf = 3 pF 


n» = a p f V 








II 














V 








-C s =iuupi-^7 


*- 








\. 




v2 










>_.« 


£2 














\* 
















-GAIN — — 
-PHASE — - 

| 1 






























ts 




LM1 


M" | 


lif 


-30p 


*' 


> 



40 ^ „, .. 

a 

20 (-UAIN ——J 1 V > ■! 1 45 3 

-PHASE — — "^-^ — 



-20 

1 10 100 Ik 10k 100k 1M 10M 

FREQUENCY (Hz) 

TL/H/6875-8 

Figure 8. Open loop frequency response 

The open loop frequency response, plotted in Figure 8, indi- 
cates that the frequency response is about the same as that 
of the LM709 or the LM101A. Curves are given for the two 
compensation circuits shown in Figure 9. The standard 
compensation is identical to that of the LM101 or LM101A. 
The alternate compensation scheme gives much better re- 
jection of high frequency power supply noise, as will be 
shown later. 




R1 + R2 
C = 30 pF 



TL/H/6875-9 



a. standard compensation circuit 

R1 




TL/H/6875-10 



With unity gain compensation, both methods give a 75-de- 
gree stability margin. However, the shunt compensation has 
a 300 kHz small signal bandwidth as opposed to 1 MHz for 
the other scheme. Because the compensation capacitor is 
not included on the IC chip, it can be tailored to fit the appli- 
cation. When the amplifier is used only at low frequencies, 
the compensation capacitor can be increased to give a 
greater stability margin. This makes the circuit less sensitive 
to capacitive loading, stray capacitances or improper supply 
bypassing. Overcompensating also reduces the high fre- 
quency noise output of the amplifier. 
With closed-loop gains greater than one, the high frequency 
performance can be optimized by making the compensation 
capacitor smaller. If unity-gain compensation is used for an 
amplifier with a gain of ten, the gain error will exceed 1 -per- 
cent at frequencies above 400 Hz. This can be extended to 
4 kHz by reducing the compensation capacitor to 3 pF. The 
formula for determining the minimum capacitor value is giv- 
en in Figure 9a. It should be noted that the capacitor value 
does not really depend on the closed-loop gain. Instead, it 
depends on the high frequency attenuation in the feedback 
networks and, therefore, the values of Ri and R2. When it is 
desirable to optimize performance at high frequencies, the 
standard compensation should be used. With small capaci- 
tor values, the stability margin obtained with shunt compen- 
sation is inadequate for conservative designs. 
The frequency response of an operational amplifier is con- 
siderably different for large output signals than it is for small 
signals. This is indicated in Figure 10. With unity-gain com- 
pensation, the small signal bandwidth of the LM108 is 1 
MHz. Yet full output swing cannot be obtained above 2 kHz. 
This corresponds to a slew rate of 0.3 V/ju,s. Both the full- 
output bandwidth and the slew rate can be increased by 
using smaller compensation capacitors, as is indicated in 
the figure. However, this is only applicable for higher closed 
loop gains. The results plotted in Figure 10 are for standard 
compensations. With unity gain compensation, the same 
curves are obtained for the shunt compensation scheme. 
Classical op amp theory establishes output resistance as an 
important design parameter. This is not true for IC op amps: 
The output resistance of most devices is low enough that it 
can be ignored, because they use class-B output stages. At 
low frequencies, thermal feedback between the output and 







'I 




I II 


1 1 


2B°C 






j Y 






h 




±1BV 






I r 


f 


ipF 










I -S 














V 


= 30pFl 










































LM 


1 08 

L.l .. 















Ik 10k 100k 1M 

FREOUENCYIHz) 

TL/H/6875-11 

Figure 10. Large signal frequency response 



b. alternate compensation circuit 
Figure 9. Compensation circuits 



52 



input stages determines the effective output resisance, and 
this cannot be accounted for by conventional design theo- 
ries. Semiconductor manufacturers take care of this by 
specifying the gain under full load conditions, which com- 
bines output res/stance with gain as far as it affects overall 
circuit performance. This avoids the fictitious problem that 
can be created by an amplifier with infinite gain, which is 
good, that will cause the open loop output resistance to 
appear infinite, which is bad, although none of this affects 
overall performance significantly. 




A v =1,Cf = 30pF 
A v = 1000. Cf '■ pF 
1000, Cf * 30 pF 

T» = 25°C < 
•out * *' ™A 



Ik 10k 100k 1M 10M 
FREO.UENCY (Hz) 

TL/H/6875-12 

Figure 11. Closed loop output impedance 

The closed loop output impedance is, nonetheless, impor- 
tant in some applications. This is plotted for several operat- 
ing conditions in Figure 1 1. It can be seen that the output 
impedance rises to about 500fl at high frequencies. The 
increase occurs because the compensation capacitor rolls 
off the open loop gain. The output resistance can be re- 
duced at the intermediate frequencies, for closed loop gains 
greater than one, by making the capacitor smaller. This is 
made apparent in the figure by comparing the output resist- 
ance with and without frequency compensation for a closed 
loop gain of 1000. 

The output resistance also tends to increase at low frequen- 
cies. Thermal feedback is responsible for this phenomenon. 
The data for Figure 1 1 was taken under large-signal condi- 
tions with ± 1 5V supplies, the output at zero and ± 1 mA 
current swing. Hence, the thermal feedback is accentuated 
more than would be the case for most applications. 
In an op amp, it is desirable that performance be unaffected 
by variations in supply voltage. IC amplifiers are generally 
better than discretes in this respect because it is necessary 
for one single design to cover a wide range of uses. The 
LM108 has a power supply rejection which is typically in 
excess of 100 dB, and it will operate with supply voltages 
from ±2V to ±20V. Therefore, well-regulated supplies are 
unnecessary, for most applications, because a 20-percent 
variation has little effect on performance. 
The story is different for high-frequency noise on the sup- 
plies, as is evident from Figure 12. Above 1 MHz, practically 
all the noise is fed through to the output. The figure also 
demonstrates that shunt compensation is about ten times 
better at rejecting high frequency noise than is standard 
compensation. This difference is even more pronounced 
with larger capacitor values. The shunt compensation has 
the added advantage that it makes the circuit virtually unaf- 
fected by the lack of supply bypassing. 




10k 100k 1M 10M 
FREQUENCY (Hz) 



TL/H/6875-13 

Figure 12. Power supply rejection 

Power supply rejection is defined as the ratio of the change 
in offset voltage to the change in the supply voltage produc- 
ing it. Using this definition, the rejection at low frequencies is 
unaffected by the closed loop gain. However, at high fre- 
quencies, the opposite is true. The high frequency rejection 
is increased by the closed loop gain. Hence, an amplifier 
with a gain of ten will have an order of magnitude better 
rejection than that shown in Figure 12 in the vicinity of 
100 kHz to 1 MHz. 

The overall performance of the LM108 is summarized in 
Table I*. It is apparent from the table and the previous dis- 
cussion that the device is ideally suited for applications that 
require low input currents or reduced power consumption. 
The speed of the amplifier is not spectacular, but this is not 
usually a problem in high-impedance circuitry. Further, the 
reduced high frequency performance makes the amplifier 
easier to use in that less attention need be paid to capaci- 
tive loading, stray capacitances and supply bypassing. 

applications 

Because of its low input current the LM108 opens up many 
new design possibilities. However, extra care must be taken 
in component selection and the assembly of printed circuit 
boards to take full advantage of its performance. Further, 
unusual design techniques must often be applied to get 
around the limitations of some components. 

sample and hold circuits 

The holding accuracy of a sample and hold is directly relat- 
ed to the error currents in the components used. Therefore, 
it is a good circuit to start off with in explaining the problems 




TL/H/6875-14 



Figure 13. Sample and hold circuit 

involved. Figure 13 shows one configuration for a sample 
and hold. During the sample interval, Qi is turned on, charg- 
ing the hold capacitor, Ci, up to the value of the input signal. 



•See Appendix Heading in This Application Note. 



53 



When Q-\ is turned off, C 1 retains this voltage. The output is 
obtained from an op amp that buffers the capacitor so that it 
is not discharged by any loading. In the holding mode, an 
error is generated as the capacitor looses charge to supply 
circuit leakages. The accumulation rate for error is given by 

dV = Je 

dt d ' 
where dV/dt is the time rate of change in output voltage and 
lg is the sum of the input current to the op amp, the leakage 
current of the holding capacitor, board leakages and the 
"off" current of the FET switch. 

When high-temperature operation is involved, the FET leak- 
age can limit circuit performance. This can be minimized by 
using a junction FET, as indicated, because commercial 
junction FETs have lower leakage than their MOS counter- 
parts. However, at 1 25°C even junction devices are a prob- 
lem. Mechanical switches, such as reed relays, are quite 
satisfactory from the standpoint of leakage. However, they 
are often undesirable because they are sensitive to vibra- 
tion, they are too slow or they require excessive drive pow- 
er. If this is the case, the circuit in Figure 14 can be used to 
eliminate the FET leakage. 

v + R1 



'Tlif 



ill »AA/V • 

t=T 2N4067 I .^ 




■ImF 



TL/H/6875-15 
tTeflon, polyethylene or polycarbonate dielectric capacitor 
Worst case drift less than 3 mV/sec 

Figure 14. Sample and hold that eliminates leakage in 
FET switches 

When using P-channel MOS switches, the substrate must 
be connected to a voltage which is always more positive 
than the input signal. The source-to-substrate junction be- 
comes forward biased if this is not done. The troublesome 
leakage current of a MOS device occurs across the sub- 
strate-to-drain junction. In Figure 14, this current is routed to 
the output of the buffer amplifier through Ri so that it does 
not contribute to the error current. 
The main sample switch is Qi, while Q2 isolates the hold 
capacitor from the leakage of Q-|. When the sample pulse is 
applied, both FETs turn on charging C1 to the input voltage. 
Removing the pulse shuts off both FETs, and the output 
leakage of Q1 goes through R1 to the output. The voltage 
drop across R1 is less than 10 mV, so the substrate of Q2 
can be bootstrapped to the output of the LM108. Therefore, 
the voltage across the substrate-drain junction is equal to 
the offset voltage of the amplifier. At this low voltage, the 
leakage of the FET is reduced by about two orders of mag- 
nitude. 

It is necessary to use MOS switches when bootstrapping 
the leakages in this fashion. The gate leakage of a MOS 
device is still negligible at high temperatures; this is not the 
case with junction FETs. If the MOS transistors have protec- 



tive diodes on the gates, special arrangements must be 
made to drive Q2 so the diode does not become forward 
biased. 

In selecting the hold capacitor, low leakage is not the only 
requirement. The capacitor must also be free of dielectric 
polarization phenomena. 8 This rules out such types as pa- 
per, mylar, electrolytic, tantalum or high-K ceramic. For 
small capacitor values, glass or silvered-mica capacitors are 
recommended. For the larger values, ones with teflon, poly- 
ethylene or polycarbonate dielectrics should be used. 
The low input current of the LM108 gives a drift rate, in hold, 
of only 3 mV/sec when a 1 f*,F hold capacitor is used. And 
this number is worst case over the military temperature 
range. Even if this kind of performance is not needed, it may 
still be beneficial to use the LM108 to reduce the size of the 
hold capacitor. High quality capacitors in the larger sizes are 
bulky and expensive. Further, the switches must have a low 
"on" resistance and be driven from a low impedance source 
to charge large capacitors in a short period of time. 
If the sample interval is less than about 100 ju,s, the LM108 
may not be fast enough to work properly. If this is the case, 
it is advisable to substitute the LM102A, 9 which is a voltage 
follower designed for both low input current and high speed. 
It has a 30 V/>s slew rate and will operate with sample 
intervals as short as 1 jms. 

When the hold capacitor is larger than 0.05 ju.F, an isolation 
resistor should be included between the capacitor and the 
input of the amplifier (R2 in Figure 14). This resistor insures 
that the IC will not be damaged by shorting the output or 
abruptly shutting down the supplies when the capacitor is 
charged. This precaution is not peculiar to the LM108 and 
should be observed on any IC op amp. 

integrators 

Integrators are a lot like sample-and-hold circuits and have 
essentially the same design problems. In an integrator, a 
capacitor is used as a storage element; and the error accu- 
mulation rate is again proportional to the input current of the 
op amp. 

Figure 15 shows a circuit that can compensate for the bias 
current of the amplifier. A current is fed into the summing 
node through R^ to supply the bias current. The potentiome- 
ter, R2, is adjusted so that this current exactly equals the 
bias current, reducing the drift rate to zero. 



input— -A/W 




| — T— 100 pF 



TL/H/6875-16 

Figure 15. Integrator with bias current compensation 



54 



The diode is used for two reasons. First, it acts as a regula- 
tor, making the compensation relatively insensitive to varia- 
tions in supply voltage. Secondly, the temperature drift of 
diode voltage is approximately the same as the temperature 
drift of bias current. Therefore, the compensation is more 
effective if the temperature changes. Over a 0°C to 70"C 
temperature range, the compensation will give a factor of 
ten reduction in input current. Even better results are 
achieved if the temperature change is less. 
Normally, it is necessary to reset an integrator to establish 
the initial conditions for integration. Resetting to zero is 
readily accomplished by shorting the integrating capacitor 
with a suitable switch. However, as with the sample and 
hold circuits, semiconductor switches can cause problems 
because of high-temperature leakage. 
A connection that gets rid of switch leakages is shown in 
Figure 16. A negative-going reset pulse turns on Q-| and Q2, 



INPUT— — ^W-H p 




TL/H/6875-17 
*Q1 and Q3 should not have internal gate-protection diodes. 

Figure 16. Low drift integrator with reset 

shorting the integrating capacitor. When the switches turn 
off, the leakage current of Q2 is absorbed by R 2 while Q-| 
isolates the output of Q2 from the summing node. Q1 has 
practically no voltage across its junctions because the sub- 
strate is grounded; hence, leakage currents are negligible. 
The additional circuitry shown in Figure 16 makes the error 
accumulation rate proportional to the offset current, rather 
than the bias current. Hence, the drift is reduced by roughly 
a factor of 1 0. During the integration interval, the bias cur- 
rent of the non-inverting input accumulates an error across 
R4 and C2 just as the bias current on the inverting input 
does across R-| and C1. Therefore, if R4 is matched with R-| 
and C2 is matched with C-[ (within about 5 percent) the out- 
put will drift at a rate proportional to the difference in these 



currents. At the end of the integration interval, Q3 removes 
the compensating error accumulated on C2 as the circuit is 
reset. 

In applications involving large temperature changes, the cir- 
cuit in Figure 16 gives better results than the compensation 
scheme in Figure 15— especially under worst case condi- 
tions. Over a -55°C to 125°C temperature range, the worst 
case drift is reduced from 3 mV/sec to 0.5 mV/sec when a 
1 ju.F integrating capacitor is used. If this reduction in drift is 
not needed, the circuit can be simplified by eliminating R4, 
C2 and Q3 and returning the non-inverting input of the ampli- 
fier directly to ground. 

In fabricating low drift integrators, it is again necessary to 
use high quality components and minimize leakage currents 
in the wiring. The comments made on capacitors in connec- 
tion with the sample-and-hold circuits also apply here. As an 
additional precaution, a resistor should be used to isolate 
the inverting input from the integrating capacitor if it is larger 
than 0.05 \iF. This resistor prevents damage that might oc- 
cur when the supplies are abruptly shut down while the inte- 
grating capacitor is charged. 

Some integrator applications require both speed and low 
error current. The output amplifiers for photomultiplier tubes 
or solid-state radiation dectectors are examples of this. Al- 
though the LM1 08 is relatively slow, there is a way to speed 
it up when it is used as an inverting amplifier. This is shown 
in Figure 17. 

The circuit is arranged so that the high-frequency gain char- 
acteristics are determined by A2, while A-i determines the dc 
and low-frequency characteristics. The non-inverting input 
of A-| is connected to the summing node through R-|. A-| is 
operated as an integrator, going through unity gain at 
500 Hz. Its output drives the non-inverting input of A 2 . The 
inverting input of A2 is also connected to the summing node 
through C3. C3 and R3 are chosen to roll off below 750 Hz. 
Hence, at frequencies above 750 Hz, the feedback path is 
directly around A 2 , with A1 contributing little. Below 500 Hz, 
however, the direct feedback path to A2 rolls off; and the 
gain of A1 is added to that of A2. 

The high gain frequency amplifier, A2, is an LM101A con- 
nected with feed-forward compensation. 10 It has a 10 MHz 
equivalent small-signal bandwidth, a 10V/jlis slew rate and 
a 250 kHz large-signal bandwidth, so these are the high-fre- 
quency characteristics of the complete amplifier. The bias 
current of A2 is isolated from the summing node by C3. 
Hence, it does not contribute to the dc drift of the integrator. 
The inverting input of A^ is the only dc connection to the 
summing junction. Therefore, the error current of the com- 
posite amplifier is equal to the bias current of A-| . 
If A2 is allowed to saturate, A-j will then start towards satura- 
tion. If the output of A1 gets far off zero, recovery from satu- 
ration will be slowed drastically. This can be prevented by 
putting zener clamp diodes across the integrating capacitor. 
A suitable clamping arrangement is shown in Figure 17. D1 
and D2 are included in the clamp circuit along with R5 to 
keep the leakage currents of the zeners from introducing 
errors. 

In addition to increasing speed, this circuit has other advan- 
tages. For one, it has the increased output drive capability 
of the LM101A. Further, thermal feedback is virtually elimi- 
nated because the LM108 does not see load variations. 
Lastly, the open loop gain is nearly infinite at low frequen- 
cies as it is the product of the gains of the two amplifiers. 



55 



CM 



INPUT *W* 




# OUTPUT 



I — yf P 3 

—I— 300 pf I 



TL/H/6875-18 



Figure 17. Fast integrator 




COSINE 

"output 



TL/H/6875-19 



Figure 18. Sine wave oscillator 



sine wave oscillator 

Although it is comparatively easy to build an oscillator that 
aproximates a sine wave, making one that delivers a high- 
purity sinusoid with a stable frequency and amplitude is an- 
other story. Most satisfactory designs are relatively compli- 
cated and require individual trimming and temperature com- 
pensation to make them work. In addition, they generally 
take a long time to stabilize to the final output amplitude. 



A unique solution to most of these problems is shown in 
Figure 18. Ai is connected as a two-pole low-pass active 
filter, and A2 is connected as an integrator. Since the ulti- 
mate phase lag introduced by the amplifiers is 270 degrees, 
the circuit can be made to oscillate if the loop gain is high 
enough at the frequency where the lag is 1 80 degrees. The 
gain is actually made somewhat higher than is required for 
oscillation to insure starting. Therefore, the amplitude builds 
up until it is limited by some nonlinearity in the system. 



56 



Amplitude stabilization is accomplished with zener clamp di- 
odes, Di and D2. This does introduce distortion, but it is 
reduced by the subsequent low pass filters. If D1 and D2 
have equal breakdown voltages, the resulting symmetrical 
clipping will virtually eliminate the even-order harmonics. 
The dominant harmonic is then the third, and this is about 
40 dB down at the output of A-| and about 50 dB down on 
the output of A2. This means that the total harmonic distor- 
tion on the two outputs is 1 percent and 0.3 percent, respec- 
tively. 

The frequency of oscillation and the oscillation threshold 
are determined by R-|, R2, R3, C-|, C2 and C3. Therefore 
precision components with low temperature coefficients 
should be used. If R3 is made lower than shown, the circuit 
will accept looser component tolerances before dropping 
out of oscillation. The start up will also be quicker. However, 
the price paid is that distortion is increased. The value of R4 
is not critical, but it should be made much smaller than R2 
so that the effective resistance at R2 does not drop when 
the clamp diodes conduct. 

The output amplitude is determined by the breakdown volt- 
ages of D1 and D2. Therefore, the clamp level should be 
temperature compensated for stable operation. Diode-con- 
nected (collector shorted to base) NPN transistors with an 
emitter-base breakdown of about 6.3V work well, as the 
positive temperature coefficient of the diode in reverse 
breakdown nearly cancels the negative temperature coeffi- 
cient of the forward-biased diode. Added advantages of us- 
ing transistors are that they have less shunt capacitance 
and sharper breakdowns than conventional zeners. 
The LM108 is particularly useful in this circuit at low fre- 
quencies, since it permits the use of small capacitors. The 
circuit shown oscillates at 1 Hz, but uses capacitors in the 
order of 0.01 u-F. This makes it much easier to find tempera- 
ture-stable precision capacitors. However, some judgment 
must be used as large value resistors with low temperature 
coefficients are not exactly easy to come by.* 
The LM108s are useful in this circuit for output frequencies 
up to 1 kHz. Beyond that, better performance can be real- 
ized by substituting and LM102A for A-\ and an LM101A with 
feed-forward compensation for A2. The improved high-fre- 
quency response of these devices extend the operating fre- 
quency out to 1 00 kHz. 

capacitance multiplier 

Large capacitor values can be eliminated from most sys- 
tems just by raising the impedance levels, if suitable op 
amps are available. However, sometimes it is not possible 
because the impedance levels are already fixed by some 
element of the system like a low impedance transducer. If 
this is the case, a capacitance multiplier can be used to 
increase the effective capacitance of a small capacitor and 
couple it into a low impedance system. 
Previously, IC op amps could not be used effectively as ca- 
pacitance multipliers because the equivalent leakages gen- 
erated due to offset current were significantly greater than 
the leakages of large tantalum capacitors, With the LM108, 
this has changed. The circuit shown in Figure 19 generates 
an equivalent capacitance of 1 00,000 ju,F with a worst case 
leakage of 8 jxA — over a -55°C to 125°C temperature 
range. 

•Large-value resistors are available from Victoreen Instrument, Cleveland, 
Ohio and Pyrofilm Resistor Co., Whippany, New Jersey. 



R2 
10M 




TL/H/6875-20 

Figure 19. Capacitance multiplier 

The performance of the circuit is described by the equations 
given in Figure 19, where C is the effective output capaci- 
tance, l|_ is the leakage current of this capacitance and R s is 
the series resistance of the multiplied capacitance. The se- 
ries resistance is relatively high, so high-Q capacitors can- 
not be realized. Hence, such applications as tuned circuits 
and filters are ruled out. However, the multiplier can still be 
used in timing circuits or servo compensation networks 
where some resistance is usually connected in series with 
the capacitor or the effect of the resistance can be compen- 
sated for. 

One final point is that the leakage current of the multiplied 
capacitance is not a function of the applied voltage. It per- 
sists even with no voltage on the output. Therefore, it can 
generate offset errors in a circuit, rather than the scaling 
errors caused by conventional capacitors. 

instrumentation amplifier 

In many instrumentation applications there is frequently a 
need for an amplifier with a high-impedance differential in- 
put and a single ended output. Obvious uses for this are 
amplifiers for bridge-type signal sources such as strain 
gages, temperature sensors or pressure transducers. Gen- 
eral purpose op amps have satisfactory input characteris- 
tics, but feedback must be added to determine the effective 
gain. And the addition of feedback can drastically reduce 
the input resistance and degrade common mode rejection. 
Figure 20 shows the classical op amp circuit for a differen- 
tial amplifier. This circuit has three main disadvantages. 
First, the input resistance on the inverting input is relatively 
low, being equal to R1. Second, there usually is a large dif- 
ference in the input resistance of the two inputs, as is indi- 
cated by the equations on the schematic. Third, the com- 
mon mode rejection is greatly affected by resistor matching 
and by balancing of the source resistances. A 1 -percent 
deviation in any one of the resistor values reduces the com- 
mon mode rejection to 46 dB for a closed loop gain of 1 , to 
60 dB for a gain of 10 and to 80 dB for a gain of 100. 
Clearly, the only way to get high input impedance is to use 
very large resistors in the feedback network. The op amp 
must operate from a source resistance which is orders of 
magnitude larger than the resistance of the signal source. 
Older IC op amps introduced excessive offset and drift 
when operating from higher resistances and could not be 
used successfully. The LM108, however, is relatively unaf- 
fected by the large resistors, so this approach can some- 
times be employed. 



57 



With large input resistors, the feedback resistors, R3 and 
R4, can get quite large for higher closed loop gains. For 
example, if R-| and R2 are 1 Mil, R3 and R4 must be 
1 00 Mft for a gain of 1 00. It is difficult to accurately match 
resistors that are this high in value, so common mode rejec- 
tion may suffer. Nonetheless, any one of the resistors can 
be trimmed to take out common mode feedthrough caused 
either by resistors mismatches or the amplifier itself. 



R 1N = R1 




R, N = R2 + R4 



TL/H/6875-21 

Figure 20. Feedback connection for a differential ampli- 
fier 

Another problem caused by large feedback resistors is that 
stray capacitance can seriously affect the high frequency 
common mode rejection. With 1 Mfi input resistors, a 1 pF 
mismatch in stray capacitance from either input to ground 
can drop the common mode rejection to 40 dB at 1500 Hz. 
The high frequency rejection can be improved at the ex- 
pense of frequency response by shunting R3 and R4 with 
matched capacitors. 

With high impedance bridges, the feedback resistances be- 
come prohibitively large even for the LM108, so the circuit in 
Figure 20 cannot be used. One possible alternative is 
shown in Figure 21. R2 and R3 are chosen so that their 
equivalent parallel resistance is equal to R-|. Hence, the out- 
put of the amplifier will be zero when the bridge is balanced. 




When the bridge goes off balance, the op amp maintains 
the voltage between its input terminals at zero with current 
fed back from the output through R3. This circuit does not 
act like a true differential amplifier for large imbalances in 
the bridge. The voltage drops across the two sensor resis- 
tors, Si and S2, become unequal as the bridge goes off 
balance, causing some non-linearity in the transfer function. 
However, this is not usually objectionable for small signal 
swings. 



t-\>W 




TL/H/6875-22 

Figure 21. Amplifier for bridge transducers 



TL/H/6875-23 

Figure 22. Differential input instrumentation amplifier 

Figure 22 shows a true differential connection that has few 
of the problems mentioned previously. It has an input resist- 
ance greater than 10 10 n, yet it does not need large resis- 
tors in the feedback circuitry. With the component values 
shown, A1 is connected as a non-inverting amplifier with a 
gain of 1 .01 ; and it feeds into A2 which has an inverting gain 
of 100. Hence, the total gain from the input of A1 to the 
output of A2 is 101, which is equal to the non-inverting gain 
of A2. If all the resistors are matched, the circuit responds 
only to the differential input signal — not the common mode 
voltage. 

This circuit has the same sensitivity to resistor matching as 
the previous circuits, with a 1 percent mismatch between 
two resistors lowering the common mode rejection to 80 dB. 
However, matching is more easily accomplished because of 
the lower resistor values. Further, the high frequency com- 
mon mode rejection is less affected by stray capacitances. 
The high frequency rejection is limited, though, by the re- 
sponse of A1 

logarithmic converter 

A logarithmic amplifier is another circuit that can take ad- 
vantage of the low input current of an op amp to increase 
dynamic range. Most practical log converters make use of 
the logarithmic relationship between the emitter-base volt- 
age of standard double-diffused transistors and their collec- 
tor current. This logarithmic characteristic has been proven 
true for over 9 decades of collector current. The only prob- 
lem involved in using transistors as logging elements is that 
the scale factor has a temperature sensitivity of 0.3 per- 
cent/°C. However, temperature compensating resistors 
have been developed to compensate for this characteristic, 
making possible log converters that are accurate over a 
wide temperature range. 



58 




300 pF 

10 nA < l| N < 1 mA 
Sensitivity is 1 V per decade. 



TL/H/6875-24 
t1 kn (±1%) at 25°C, +3500 ppm/'C. 
Available from Vishay Ultronix, Grand Junc- 
tion, CO, Q81 Series. 



•Determines current for zero crossing on 
output: 10 ft A as shown. 

Figure 23. Temperature compensated one-quadrant logarithmic converter 



Figure 23 gives a circuit that uses these techniques. Qi is 
the logging transistor, while Q2 provides a fixed offset to 
temperature compensate the emitter-base turn on voltage 
of Q1 . Q2 is operated at a fixed collector current of 1 jaA by 
A2, and its emitter-base voltage is subtracted from that of 
Q1 in determining the output voltage of the circuit. The col- 
lector current of Q2 is established by R3 and V + through 
A 2 . 

The collector current of Q1 is proportional to the input cur- 
rent through R s and, therefore, proportional to the input volt- 
age. The emitter-base voltage of Q1 varies as the log of the 
input voltage. The fixed emitter-base voltage of Q2 sub- 
tracts from the voltage on the emitter of Q1 in determining 
the voltage on the top end of the temperature-compensat- 
ing resistor, S-|. 

The signal on the top of S-| will be zero when the input 
current is equal to the current through R3 at any tempera- 
ture. Further, this voltage will vary logarithmically for chang- 
es in input current, although the scale factor will have a 
temperature coefficient of -0.3%/°C. The output of the 
converter is essentially multiplied by the ratio of R1 to S-|. 
Since Si has a positive temperature coefficient of 0.3 per- 
cent/°C, it compensates for the change in scale factor with 
temperature. 

In this circuit, an LM101A with feedforward compensation is 
used for A2 since it is much faster than the LM108 used for 
A-| . Since both amplifiers are cascaded in the overall feed- 
back loop, the reduced phase shift through A2 insures sta- 
bility. 

Certain things must be considered in designing this circuit. 
For one, the sensitivity can be changed by varying R-|. But 
R1 must be made considerably larger than the resistance of 
Si for effective temperature compensation of the scale fac- 
tor. Q1 and Q2 should also be matched devices in the same 
package, and Si should be at the same temperature as 



these transistors. Accuracy for low input currents is deter- 
mined by the error caused by the bias current of A-|. At high 
currents, the behavior of Q1 and Q2 limits accuracy. For 
input currents approaching 1 mA, the 2N2920 develops log- 
ging errors in excess of 1 percent. If larger input currents 
are anticipated, bigger transistors must be used; and R2 
should be reduced to insure that A2 does not saturate. 

transducer amplifiers 

With certain transducers, accuracy depends on the choice 
of the circuit configuration as much as it does on the quality 
of the components. The amplifier for photodiode sensors, 
shown in Figure 24, illustrates this point. Normally, photodi- 
odes are operated with reverse voltage across the junction. 
At high temperatures, the leakage currents can approach 
the signal current. However, photodiodes deliver a short-cir- 
cuit output current, unaffected by leakage currents, which is 
not significantly lower than the output current with reverse 
bias. 




Vout - 'OV/mA 



S ~T~ 100 pF 



TL/H/6875-25 

Figure 24. Amplifier for photodiode sensor 



59 



IOjiF 




T 



TL/H/6875-26 

Figure 25. Amplifier for piezoelectric transducers 

The circuit shown in Figure 24 responds to the short-circuit 
output current of the photodiode. Since the voltage across 
the diode is only the offset voltage of the amplifier, inherent 
leakage is reduced by at least two orders of magnitude. 
Neglecting the offset current of the amplifier, the output cur- 
rent of the sensor is multiplied by Ri plus R2 in determining 
the output voltage. 

Figure 25 shows an amplifier for high-impedance ac trans- 
ducers like a piezoelectric accelerometer. These sensors 
normally require a high-input-resistance amplifier. The 
LM108 can provide input resistances in the range of 10 to 
1 00 Mil, using conventional circuitry. However, convention- 
al designs are sometimes ruled out either because large 
resistors cannot be used or because prohibitively large input 
resistances are needed. 

Using the circuit in Figure 25, input resistances that are or- 
ders of magnitude greater than the values of the dc return 
resistors can be obtained. This is accomplished by boot- 
strapping the resistors to the output. With this arrangement, 
the lower cutoff frequency of a capacitive transducer Is de- 
termined more by the RC product of R1 and C1 than it is by 
resistor values and the equivalent capacitance of the trans- 
ducer. 

resistance multiplication 

When an inverting operational amplifier must have high in- 
put resistance, the resistor values required can get out of 
hand. For example, if a 2 Mil input resistance is needed for 
an amplifier with a gain of 1 00, a 200 Mfl feedback resistor 
is called for. This resistance can, however, be reduced us- 
ing the circuit in Figure 26. A divider with a ratio of 1 00 to 1 
(R3 and R4) is added to the output of the amplifier: Unity- 
gain feedback is applied from the output of the divider, giv- 
ing an overall gain of 100 using only 2 Mfi resistors. 
This circuit does increase the offset voltage somewhat. The 
output offset voltage is given by 



V OUT 



(*£*) 



A V V 



The offset voltage is only multiplied by Ay + 1 in a conven- 
tional inverter. Therefore, the circuit in Figure 26 multiplies 
the offset by 200, instead of 101. This multiplication factor 
can be reduced to 1 1 by increasing R2 to 20 Mil and R3 to 
5.55k. 




wv-l 



TL/H/6875-27 

Figure 26. Inverting amplifier with high input resistance 

Another disadvantage of the circuit is that four resistors de- 
termine the gain, instead of two. Hence, for a given resistor 
tolerance, the worst-case gain deviation is greater, although 
this is probably more than offset by the ease of getting bet- 
ter tolerances in the low resistor values. 

current sources 

Although there are numerous ways to make current sources 
with op amps, most have limitations as far as their applica- 
tion is concerned. Figure 27, however, shows a current 
source which is fairly flexible and has few restrictions as far 
as its use is concerned. It supplies a current that is propor- 
tional to the input voltage and drives a load referred to 
ground or any voltage within the output-swing capability of 
the amplifier. 




'OUT : 



R3V|N 



R1R5 
R3 = R4 + R5 
R1 = R2 



TL/H/6875-28 

Figure 27. Bilateral current source 

With the output grounded, it is relatively obvious that the 
output current will be determined by R5 and the gain setting 
of the op amp, yielding 

1 _ R 3 V IN 

Iout ---r7?V 

When the output is not at zero, it would seem that the cur- 
rent through R2 and R4 would reduce accuracy. Nonethe- 
less, if Ri = R2 and R3 = R4 + R5, the output current will 



60 



be independent of the output voltage. For Ri + R 3 > R 5 , 
the output resistance of the circuit is given by 

Rout-R 5 (^ 

where R is any one of the feedback resistors (R-|, R2, R3 or 
R4) and AR is the incremental change in the resistor value 
from design center. Hence, for the circuit in Figure 27, a 1 
percent deviation in one of the resistor values will drop the 
output resistance to 200 kfl. Such errors can be trimmed 
out by adjusting one of the feedback resistors. In design, it 
is advisable to make the feedback resistors as large as pos- 
sible. Otherwise, resistor tolerances become even more crit- 
ical. 

The circuit must be driven from a source resistance which is 
low by comparison to R-|, since this resistance will imbal- 
ance the circuit and affect both gain and output resistance. 
As shown, the circuit gives a negative output current for a 
positive input voltage. This can be reversed by grounding 
the input and driving the ground end of R2. The magnitude 
of the scale factor will be unchanged as long as R4 > R5. 

voltage comparators 

Jke most op amps, it is possible to use the LM108 as a 
voltage comparator. Figure 28 shows the device used as a 
simple zero-crossing detector. The inputs of the IC are pro- 



OUTPUT 




TL/H/6875-29 

Figure 28. Zero crossing detector 

tected internally by back-to-back diodes connected be- 
tween them, therefore, voltages in excess of 1 V cannot be 
impressed directly across the inputs. This problem is taken 
care of by R1 which limits the current so that input voltages 
in excess of 1 kV can be tolerated. If absolute accuracy is 
required or if R1 is made much larger than 1 Mft, a compen- 
sating resistor of equal value should be inserted in series 
with the other input. 

In Figure 28, the output of the op amp is clamped so that it 
can drive DTL or TTL directly. This is accomplished with a 
clamp diode on pin 8. When the output swings positive, it is 
clamped at the breakdown voltage of the zener. When it 
swings negative, it is clamped at a diode drop below ground. 
If the 5V logic supply is used as a positive supply for the 
amplifier, the zener can be replaced with an ordinary silicon 
diode. The maximum fan out that can be handled by the 
device is one for standard DTL or TTL under worst case 
conditions. 

As might be expected, the LM108 is not very fast when 
used as a comparator. The response time is up in the tens 
of microseconds. An LM103 1 1 is recommended for D-|, rath- 
er than a conventional alloy zener, because it has lower 
capacitance and will not slow the circuit further. The sharp 
breakdown of the LM103 at low currents is also an advan- 
tage as the current through the diode in clamp is only 
10 nA. 



Figure 29 shows a comparator for voltages of opposite po- 
larity. The output changes state when the voltage on the 
junction of R-| and R2 is equal to Vjh- Mathematically, this is 
expressed by 

R 2 (V 1 - V 2 ) 



Vth = V 2 + 



Rt + R 2 




TL/H/6875-30 

Figure 29. Voltage comparator with output buffer 

The LM108 can also be used as a differential comparator, 
going through a transition when two input voltages are 
equal. However, resistors must be inserted in series with the 
inputs to limit current and minimize loading on the signal 
sources when the input-protection diodes conduct. Figure 
29 also shows how a PNP transistor can be added on the 
output to increase the fan out to about 20 with standard DTL 
or TTL. 

power booster 

The LM106, which was designed for low power consump- 
tion, is not able to drive heavy loads. However, a relatively 
simple booster can be added to the output to increase the 
output current to ± 50 mA. This circuit, shown in Figure 30, 
has the added advantage that it swings the output up to the 
supplies, within a fraction of a volt. The increased voltage 
swing is particularly helpful in low voltage circuits. 




TL/H/6875-31 



Figure 30. Power booster 



61 



In Figure 30, the output transistors are driven from the sup- 
ply leads of the op amp. It is important that Ri and R2 be 
made low enough so Q1 and Q2 are not turned on by the 
worst case quiescent current of the amplifier. The output of 
the op amp is loaded heavily to ground with R3 and R4. 
When the output swings about 0.5V positive, the increasing 
positive supply current will turn on Q-i which pulls up the 
load. A similar situation occurs with Q2 for negative output 
swings. 

The bootstrapped shunt compensation shown in the figure 
is the only one that seems to work for all loading conditions. 
This capacitor, C-|, can be made inversely proportional to 
the closed loop gain to optimize frequency response. The 
value given is for a unity-gain follower connection. C2 is also 
required for loop stability. 

The circuit does have a dead zone in the open loop transfer 
characteristic. However, the low frequency gain is high 
enough so that it can be neglected. Around 1 kHz, though, 
the dead zone becomes quite noticeable. 
Current limiting can be incorporated into the circuit by add- 
ing resistors in series with the emitters of Q1 and Q2 be- 
cause the short circuit protection of the LM108 limits the 
maximum voltage drop across R1 and R2. 

board construction 

As indicated previously, certain precautions must be ob- 
served when building circuits that are sensitive to very low 
currents. If proper care is not taken, board leakage currents 
can easily become much larger than the error currents of 
the op amp. To prevent this, it is necessary to thoroughly 
clean printed circuit boards. Even experimental bread- 
boards must be cleaned with trichloroethlene or alcohol to 
remove solder fluxes, and blown dry with compressed air. 
These fluxes may be insulators at low impedance levels — 
like in electric motors — but they certainly are not in high 
impedance circuits. In addition to causing gross errors, their 
presence can make the circuit behave erratically, especially 
as the temperature is changed. 



COMPENSATION 




TL/H/6875-32 

Bottom View 
Figure 31. Printed circuit layout for input guarding with 
TO-5 package 



At elevated temperatures, even the leakage of clean boards 
can be a headache. At 125°C the leakage resistance be- 
tween adjacent runs on a printed circuit board is about 
101 1ft (0.05-inch separation parallel for 1 inch) for high 
quality epoxy-glass boards that have been properly cleaned. 
Therefore, the boards can easily produce error currents in 
the order of 200 pA and much more if they become contam- 
inated. Conservative practice dictates that the boards be 
coated with epoxy or silicone rubber after cleaning to pre- 
vent contamination. Silicone rubber is the easiest to use. 
However, if the better durability of epoxy is needed, care 
must be taken to make sure that it gets thoroughly cured. 
Otherwise, the epoxy will make high temperature leakage 
much worse. 

Care must also be exercised to insure that the circuit board 
is protected from condensed water vapor when operating in 
the vicinity of 0°C. This can usually be accomplished by 
coating the board as mentioned above. 



a. inverting amplifier 



input — ^Ar 




TL/H/6875-33 



b. follower 




TL/H/6875-34 



c. non-inverting amplifier 




TL/H/6875-35 

Figure 32. Connection of input guards 



62 



guarding 

Even with properly cleaned and coated boards, leakage cur- 
rents are on the verge of causing trouble at 125°C. The 
standard pin configuration of most IC op amps has the input 
pins adjacent to pins which are at the supply potentials. 
Therefore, it is advisable to employ guarding to reduce the 
voltage difference between the inputs and adjacent metal 
runs. 

A board layout that includes input guarding is shown in Fig- 
ure 31 for the eight lead TO-5 package. A ten-lead pin circle 
is used, and the leads of the IC are formed so that the holes 
adjacent to the inputs are vacant when it is inserted in the 
board. The guard, which is a conductive ring surrounding 
the inputs, is then connected to a low impedance point that 
is at the same potential as the inputs. The leakage currents 
from the pins at the supply potentials are absorbed by the 
guard. The voltage difference between the guard and the 
inputs can be made approximately equal to the offset volt- 
age, reducing the effective leakage by more than three or- 
ders of magnitude. If the leads of the integrated circuit, or 
other components connected to the input, go through the 
board, it may be necessary to guard both sides. 
Figure 32 shows how the guard is commited on the more- 
common op amp circuits. With an integrator or inverting am- 
plifier, where the inputs are close to ground potential, the 
guard is simply grounded. With the voltage follower, the 
guard is bootstrapped to the output. If it is desirable to put a 
resistor in the inverting input to compensate for the source 
resistance, it is connected as shown in Figure 32b. 



Guarding a non-inverting amplifier is a little more complicat- 
ed. A low impedance point must be created by using rela- 
tively low value feedback resistors to determine the gain (R-| 
and R2 in Figure 32c). The guard is then connected to the 
junction of the feedback resistors. A resistor, R 3 , can be 
connected as shown in the figure to compensate for large 
source resistances. 

With the dual-in-line and flat packages, it is far more difficult 
to guard the inputs, if the standard pin configuration of the 
LM709 or LM101A is used, because the pin spacings on 
these packages are fixed. Therefore, the pin configuration 
of the LM108 was changed, as shown in Figure 33. 

conclusions 

IC op amps are now available that equal the input current 
specifications of FET amplifiers in all but the most restricted 
temperature range applications. At operating temperatures 
above 85°C, the IC is clearly superior as it uses bipolar tran- 
sistors that make it possible to eliminate the leakage cur- 
rents that plague FETs. Additionally, bipolar transistors 
match better than FETs, so low offset voltage and drifts can 
be obtained without expensive adjustments or selection. 
Further, the bipolar devices lend themselves more readily to 
low-cost monolithic construction. 

These amplifiers open up new application areas and vastly 
improve performance in others. For example, in analog 
memories, holding intervals can be extended to minutes, 
even where -55°C to 125°C operation is involved. Instru- 
mentation amplifiers and low frequency waveform genera- 
tors also benefit from the low error currents. 




1} 






COMPENSATION 


2 


12 


COMPENSATION 


GUARD 


3 


11 


V* 




INPUT 


4 


ID 


OUTPUT 




INPUT 


5 


9 


BALANCE 




GUARD 


6 


I 


TL/H/6875 


-37 


V" 


7 



NOTE: Pin 6 connected to bottom of package. 
Top View 




TL/H/6875-39 



NOTE: Pin 7 connected to bottom of package 
Top View 



Figure 33. Comparing connection diagrams of the LM101 A and LM108, showing addition of guarding 



63 



When operating above 85°C, overall performance is fre- 
quently limited by components other than the op amp, un- 
less certain precautions are observed. It is generally neces- 
sary to redesign circuits using semiconductor switches to 
reduce the effect of their leakage currents. Further, high 
quality capacitors must be used, and care must be exer- 
cised in selecting large value resistors. Printed circuit board 
leakages can also be troublesome unless the boards are 
properly treated. And above 100°C, it is almost mandatory 
to employ guarding on the boards to protect the inputs, if 
the full potential of the amplifier is to be realized. 

appendix 

A complete schematic of the LM108 is given in Figure A1. A 
description of the basic circuit is presented along with a 
simplified schematic earlier in the text. The purpose of this 
Appendix is to explain some of the more subtle features of 
the design. 

The current source supplying the input transistors is C^g- It 
is designed to supply a total input stage current of 6 juA at 
25°C. This current drops to 3 ju,A at -55°C but increases to 
only 7.5 juA at 125°C. This temperature characteristic tends 



to compensate for the current gain falloff of the input tran- 
sistors at low temperatures without creating stability prob- 
lems at high temperatures. 

The biasing circuitry for the input current source is nearly 
identical to that in the LM101 A, and a complete description 
is given in Reference 4. However, a brief explanation fol- 
lows. 

A collector FET, 6 Q23, which has a saturation current of 
about 30 /liA, establishes the collector current of Q24. This 
FET provides the initial turn-on current for the circuit and 
insures starting under all conditions. The purpose of R14 is 
to compensate for production and temperature variations in 
the FET current. It is a collector resistor (indicated by the T 
through it) made of the same semiconductor material as the 
FET channel. As the FET current varies, the drop across 
R14 tends to compensate for changes in the emitter base 
voltage of Q24. 

The collector-emitter voltage of Q24 is equal to the emitter 
base voltage of Q24 plus that of Q25. This voltage is deliv- 
ered to Q26 and Q29. Q25 and Q24 are operated at substan- 
tially higher currents than Q26 and Q29. Hence, there is a 



COMPENSATION 



COMPENSATION 




INPUTS 



TL/H/6875-40 



Figure A1. Complete schematic of the LM108 



64 



differential in their emitter base voltages that is dropped 
across R19 to determine the input stage current. R 18 is a 
pinched base resistor, as is indicated by the slash bar 
through it. This resistor, which has a large positive tempera- 
ture coefficient, operates in conjunction with R17 to help 
shape the temperature characteristics of the input stage 
current source. 

The output currents of Q 2 6. Q25. and Q23 are fed to Q 12 , 
which is a controlled-gain lateral PNP.6 it delivers one-half 
of the combined currents to the output stage. Q-| 1 is also 
connected to Q12. with its output current set at approxi- 
mately 15 /xA by R 7 . Since this type of current source 
makes use of the emitter-base voltage differential between 
similar transistors operating at different collector currents, 
the output of Q11 is relatively independent of the current 
delivered to Qi2- 12 This current is used for the input stage 
bootstrapping circuitry. 

Q20 also supplies current to the class-B output stage. Its 
output current is determined by the ratio of R15 to R 12 and 
the current through R 12 . R13 is included so that the biasing 
circuit is not upset when Q 2 o saturates. 
One major departure from the simplified schematic is the 
bootstrapping of the second stage active loads, Q 2 i and 
Q22. to the output. This makes the second stage gain de- 
pendent only on how well Qg and Q 10 match with variations 
in output voltage. Hence, the second stage gain is quite 
high. In fact, the overall gain of the amplifier is typically in 
excess of 10 6 at dc. 

The second stage active loads drive Q14. A high-gain pri- 
mary transistor is used to prevent loading of the second 
stage. Its collector is bootstrapped by Q13 to operate it at 
zero collector-base voltage. The class-B output stage is ac- 
tually driven by the emitter of Q14. 
A dead zone in the output stage is prevented by biasing Qie 
and Q19 on the verge of conduction with Q 15 and Q-| 6 . Rg is 
used to compensate for the transconductance of Q 15 and 
Q16, making the output stage quiescent current relatively 
independent of the output current of Q12. The drop across 
this resistor also reduces quiescent current. 
For positive-going outputs, short circuit protection is provid- 
ed by R10 and Q17. When the voltage drop across R-| turns 
on Q17, it removes base drive from Q-\g. For negative-going 
outputs, current limiting is initiated when the voltage drop 
across R-n becomes large enough for the collector base 
junction of Q-| 7 to become forward biased. When this hap- 
pens, the base of Q19 is clamped so the output current 
cannot increase further. 

Input protection is provided by Q 3 and Q4 which act as 
clamp diodes between the inputs. The collectors of these 
transistors are bootstrapped to the emitter of Q28 through 
R3. This keeps the collector-isolation leakage of the transis- 
tors from showing up on the inputs. R 3 is included so that 
the bootstrapping is not disrupted when Q3 or Q4 saturate 
with an input overload, Current-limiting resistors were not 
connected in series with the inputs, since diffused resistors 
cannot be employed such that they work effectively, without 
causing high temperature leakages. 



TABLE I. Typical Performance of the LM108 Operational 
Amplifier (T A = 25°Cand V s = ±15V) 

Input Offset Voltage 0.7 mV 

Input Offset Current 50 pA 

Input Bias Current 0.8 nA 

Input Resistance 70 Mil 

Input Common Mode Range ± 1 4V 

Common Mode Rejection 1 00 dB 

Offset Voltage Drift 3 jnV/°C 

Offset Current Drift 0.5 pA/°C 

Voltage Gain 300V/mW 

Small Signal Bandwidth 1 .0 MHz 

Slew Rate 0.3V/ jus 

Output Swing ± 1 4V 

Supply Current 300 juA 

Power Supply Rejection 1 00 dB 

Operating Voltage Range ± 2V to ± 20V 

references 

1. R. J. Widlar, "Future Trends in Intregrated Operational 
Amplifiers," EDN, Vol. 13, No 6, pp 24-29, June 1968. 

2. R. J. Widlar, "Super Gain Transistors for IC," IEEE Jour- 
nal of Solid-State Circuits, Vol. SC-4, No. 4, August, 1969. 

3. R. J. Widlar, "A Unique Circuit Design for a High Perform- 
ance Operational Amplifier Especially Suited to Monolith- 
ic Construction," Proc. of NEC, Vol.XXI, pp. 85-89, Octo- 
ber, 1965. 

4. R. J. Widlar, "I.C. Op Amp with Improved Input-Current 
Characteristics," EEE, pp. 38-41, December, 1968. 

5. R. J. Widlar, "Linear IC's: part 6; Compensating for Drift," 
Electronics, Vol. 41, No. 3, pp. 90-93, February, 1968. 

6. R. J. Widlar, "Design Techniques for Monolithic Opera- 
tional Amplifiers," IEEE Journal of Solid-State Circuits, 
Fol. SC-4, No. 4, August 1969. 

7. D. R. Sulllivan and M. A. Maidique, "Characterization and 
Application of a New High Input Impedance Monolithic 
Amplifier," Transitron Electronic Corporation Application 
Brief. 

8. Paul C. Dow, Jr., "An Analysis of Certain Errors in Elec- 
tronic Differential Analyzers, ll-Capacitor Dielectric Ab- 
sorption," IRE Trans, on Electronic Computers, pp. 17- 
22, March, 1958. 

9. R. J. Widlar, "A Fast Integrated Voltage Follower with 
Low Input Current," Myoelectrics, Vol. 1, No. 7, June, 
1968. 

10. R. C. Dobkin, "Feedforward Compensation Speeds Op 
Amp," National Semiconductor LB-2, March, 1969. 

11. R. J. Wildlar, "A New Low Voltage Breakdown Diode," 
National Semiconductor TP-5, April, 1 968. 

12. R. J. Widlar, "Some Circuit Design Techniques for Lin- 
ear Integrated Circuits," IEEE Transactions on Circuit 
Theory, Vol. CT-12, No. 4, pp. 586-590, December, 
1965. 






65 



Log Converters 



National Semiconductor 
Application Note 30 




One of the most predictable non-linear elements commonly 
available is the bipolar transistor. The relationship between 
collector current and emitter base voltage is precisely loga- 
rithmic from currents below one picoamp to currents above 
one milliamp. Using a matched pair of transistors and inte- 
grated circuit operational amplifiers, it is relatively easy to 
construct a linear to logarithmic converter with a dynamic 
range in excess of five decades. 

The circuit in Figure 1 generates a logarithmic output volt- 
age for a linear input current. Transistor Qi is used as the 
non-linear feedback element around an LM108 operational 
amplifier. Negative feedback is applied to the emitter of Qi 
through divider, Ri and R2, and the emitter base junction of 
Q 2 . This forces the collector current of Qi to be exactly 
equal to the current through the input resistor. Transistor Q2 
is used as the feedback element of an LM101A operational 
amplifier. Negative feedback forces the collector current of 
Q 2 to equal the current through R3. For the values shown, 
this current is 10 juA Since the collector current of Q2 re- 
mains constant, the emitter base voltage also remains con- 
stant. Therefore, only the Vbe of Qi varies with a change of 
input current. However, the output voltage is a function of 
the difference in emitter base voltages of Qi and Q 2 : 



Equt = 



R 1 + R 2 
R 2 



(V B E 2 - Ve^)- 



(D 



AV BE 



For matched transistors operating at different collector cur 
rents, the emitter base differential is given by 

kT l c 

— log e — 
q 'c 2 

where k is Boltzmann's constant, T is temperature in de- 
grees Kelvin and q is the charge of an electron. Combining 
these two equations and writing the expression for the out- 
put voltage gives 

, ^llogj E,nR3 



EOUT 



-kT T R-i + R 2 1 
q I R 2 J 



I.Eref r inJ 



(2) 



(3) 



for Ein ^ 0. This shows that the output is proportional to the 
logarithm of the input voltage. The coefficient of the log 
term is directly proportional to absolute temperature. With- 
out compensation, the scale factor will also vary directly 
with temperature. However, by making R 2 directly propor- 
tional to temperature, constant gain is obtained. The tem- 
perature compensation is typically 1 % over a temperature 
range of -25°C to 100°C for the resistor specified. For limit- 
ed temperature range applications, such as 0°C to 50°C, a 
430n sensistor in series with a 570fl resistor may be substi- 
tuted for the 1 k resistor, also with 1 % accuracy. The divider, 
R1 and R 2 , sets the gain while the current through R3 sets 
the zero. With the values given, the scale factor is 1V/dec- 
ade and 



Equt = 



logical + 5] 

I "IN I J 



(4) 



where the absolute value sign indicates that the dimensions 
of the quantity inside are to be ignored. 
Log generator circuits are not limited to inverting operation. 
In fact, a feature of this circuit is the ease with which non-in- 
verting operation is obtained. Supplying the input signal to 
A 2 and the reference current to A1 results in a log output 
that is not inverted from the input. To achieve the same 
100 dB dynamic range in the non-inverting configuration, an 
LM1 08 should be used for A 2 , and an LM1 01 A for A^ . Since 
the LM108 cannot use feedforward compensation, it is fre- 
quency compensated with the standard 30 pF capacitor. 
The only other change is the addition of a clamp diode con- 
nected from the emitter of Qi to ground. This prevents dam- 
age to the logging transistors if the input signal should go 
negative. 




RS 

1.5M 

roi 



cs 

.01 (if 



*1 kO (±1%) at 25°C, +3500 pprWC. 
Available from Vishay Ultronix, Grand Junction, CO, Q81 Series. 
tOffset Voltage Adjust 

FIGURE 1. Log Generator with 100 dB Dynamic Range 



66 



The log output is accurate to 1 % for any current between 
10 nA and 1 mA. This is equivalent to about 3% referred to 
the input. At currents over 500 ju.A the transistors used devi- 
ate from log characteristics due to resistance in the emitter, 
while at low currents, the offset current of the LM108 is the 
major source of error. These errors occur at the ends of the 
dynamic range, and from 40 nA to 400 juA the log converter 
is 1 % accurate referred to the input. Both of the transistors 
are used in the grounded base connection, rather than the 
diode connection, to eliminate errors due to base current. 
Unfortunately, the grounded base connection increases the 
loop gain. More frequency compensation is necessary to 
prevent oscillation, and the log converter is necessarily 
slow. It may take 1 to 5 ms for the output to settle to 1 % of 
its final value. This is especially true at low currents. 
The circuit shown in Figure 2 is two orders of magnitude 
faster than the previous circuit and has a dynamic range of 
80 dB. Operation is the same as the circuit in Figure 1, 
except the configuration optimizes speed rather than dy- 
namic range. Transistor Qi is diode connected to allow the 
use of feedforward compensation^ on an LM101A opera- 
tional amplifier. This compensation extends the bandwidth 
to 10 MHz and increases the slew rate. To prevent errors 
due to the finite hp E of Q-\ and the bias current of the 
LM101A, an LM102 voltage follower buffers the base cur- 
rent and input current. Although the log circuit will operate 
without the LM102, accuracy will degrade at low input cur- 
rents. Amplifier A2 is also compensated for maximum band- 
width. As with the previous log converter, R-\ and R2 control 
the sensitivity; and R3 controls the zero crossing of the 
transfer function. With the values shown the scale factor is 
IV/decade and 



EouT=-[log 10 1^| + 4 ] 



(5) 



Anti-log or exponential generation is simply a matter of rear- 
ranging the circuitry. Figure 3 shows the circuitry of the log 
converter connected to generate an exponential output 
from a linear input. Amplifier A1 in conjunction with transis- 
tor Q1 drives the emitter of Q 2 in proportion to the input 
voltage. The collector current of Q2 varies exponentially 
with the emitter-base voltage. This current is converted to a 
voltage by amplifier A 2 . With the values given 

EOUT = 10" [E|Nl . (6) 

Many non-linear functions such as XY2, X 2 , X 3 , 1 /X, XY, and 
X/Y are easily generated with the use of logs. Multiplication 
becomes addition, division becomes subtraction and pow- 
ers become gain coefficients of log terms. Figure 4 shows a 
circuit whose output is the cube of the input. Actually, any 
power function is available from this circuit by changing the 
values of Rg and R10 in accordance with the expression: 



16.7 R 9 



E0UT=E| N R9 



+ R1 



(7) 



Note that when log and anti-log circuits are used to perform 
an operation with a linear output, no temperature compen- 
sating resistors at all are needed. If the log and anti-log 
transistors are at the same temperature, gain changes with 
temperature cancel. It is a good idea to use a heat sink 
which couples the two transistors to minimize thermal gradi- 
ents. A 1°C temperature difference between the log and 
anti-log transistors results in a 0.3% error. Also, in the log 
converters, a 1°C difference between the log transistors and 
the compensating resistor results in a 0.3% error. 
Either of the circuits in Figures 1 or 2 may be used as divid- 
ers or reciprocal generators. Equation 3 shows the outputs 
of the log generators are actually the ratio of two currents: 



from less than 100 nA to 1 mA. 




+ — — WNr-i 



•1 kn (±1%) at 25°C, +3500 ppm/°C. 
Available from Vlshay Ultronix, 
Grand Junction, CO, Q81 Series. 



FIGURE 2. Fast Log Generator 



TL/H/7275-2 



67 



o 



the input current and the current through R3. When used as 
a log generator, the current through R3 was held constant 
by connecting R3 to a fixed voltage. Hence, the output was 
just the log of the input. If R3 is driven by an input voltage, 
rather than the 1 5V reference, the output of the log genera- 
tor is the log ratio of the input current to the current through 
R3. The anti-log of this voltage is the quotient. Of course, if 
the divisor is constant, the output is the reciprocal. 
A complete one quadrant multiplier/divider is shown in Fig- 
ure 5. It is basically the log generator shown in Figure 1 
driving the anti-log generator shown in Figure 3. The log 
generator output from A1 drives the base of Q3 with a volt- 
age proportional to the log of E1/E2. Transistor Q3 adds a 
voltage proportional to the log of E3 and drives the anti-log 
transistor, 64. The collector current of Q4 is converted to an 



output voltage by A 4 and R7, with the scale factor set by R7 
at E1 E 3 /10E 2 . 

Measurement of transistor current gains over a wide range 
of operating currents is an application particularly suited to 
log multiplier/dividers. Using the circuit in Figure 5, PNP cur- 
rent gains can be measured at currents from 0.4 ju,A to 
1 mA. The collector current is the input signal to A-|, the 
base current is the input signal to Ag, and a fixed voltage to 
R 5 sets the scale factor. Since A2 holds the base at ground, 
a single resistor from the emitter to the positive supply is all 
that is needed to establish the operating current. The output 
is proportional to collector current divided by base current, 
or h FE - 

In addition to their application in performing functional oper- 
ations, log generators can provide a significant increase in 



RE 

iok 



JL SB4 -sr y 




1 kn (±1%) at 25°C, +3500 ppm/°C. 
Available from Vishay Ultronix, 
Grand Junction, CO, Q81 Series. 



FIGURE 3. Anti-Log Generator 



TL/H/7275-3 



08 »F — I— ~ VVV 



•cr^rr 




r^^f 



TL/H/7275-4 



FIGURE 4. Cube Generator 



68 



the dynamic range of signal processing systems. Also, un- 
like a linear system, there is no loss in accuracy or resolu- 
tion when the input signal is small compared to full scale. 
Over most of the dynamic range, the accuracy is a percent- 
of-signal rather than a percent-of-full-scale. For example, 
using log generators, a simple meter can display signals 
with 1 00 dB dynamic range or an oscilloscope can display a 
10 mV and 10V pulse simultaneously. Obviously, without the 
log generator, the low level signals are completely lost. 
To achieve wide dynamic range with high accuracy, the in- 
put operational amplifier necessarily must have low offset 
voltage, bias current and offset current. The LM108 has a 
maximum bias current of 3 nA and offset current of 400 pA 
over a -55°C to 125°C temperature range. By using equal 
source resistors, only the offset current of the LM108 caus- 
es an error. The offset current of the LM108 is as low as 
many FET amplifiers. Further, it has a low and constant tem- 
perature coefficient rather than doubling every 10°C. This 
results in greater accuracy over temperature than can be 
achieved with FET amplifiers. The offset voltage may be 



zeroed, if necessary, to improve accuracy with low input 
voltages. 

The log converters are low level circuits and some care 
should be taken during construction. The input leads should 
be as short as possible and the input circuitry guarded 
against leakage currents. Solder residues can easily con- 
duct leakage currents, therefore circuit boards should be 
cleaned before use. High quality glass or mica capacitors 
should be used on the inputs to minimize leakage currents. 
Also, when the + 1 5V supply is used as a reference, it must 
be well regulated. 

REFERENCES 

1. R. C. Dobkin, "Feedforward Compensation Speeds Op 
Amp", National Semiconductor Corporation, Linear Brief 
2, April, 1969. 

2. R. J. Widlar, "Monolithic Operational Amplifiers— The 
Universal Linear Component", National Semiconductor 
Corporation, AN-4, April, 1 968. 



> 

ii 



CI -J- -±" 2K 5lpF| ^ 

OpF-p- - L-VW- 4 ' 




FIGURE 5. Multiplier/Divider 



TL/H/7275-5 



69 



CO 
I 

z 
< 



Op Amp Circuit Collection 



SECTION 1— BASIC CIRCUITS 

Inverting Amplifier 



v,n— W/V 




National Semiconductor 
Application Note 31 



Non-Inverting Amplifier 

R1 R2 





Difference Amplifier 

R2 



Inverting Summing Amplifier 




VR3 + R4/ D < 2 D< 1 



R1 ' R1 
For R1 = R3 and R2 = R4 

v ut = ^(v 2 -v 1 ) 

R1//R2 = R3//R4 TL/ 

For minimum offset error 
due to input bias current 



Non-Inverting Summing Amplifier 




100K 
100K I 

e 2 * — vvvJ 



*Rs = 1k 

for 1 % accuracy 



v,— **/Vsr-P 

HI 




Vout 



( Vi V 2 V 3 \ 

R5 = R1//R2//R3//R4 
For minimum offset error 
due to input bias current 



TL/H/7057-4 



Inverting Amplifier with High Input Impedance 



R1 
10M 
1% 
INPUT — ^^V 



•Source Impedance 
less than 100k 

TL/H/7057-5 9 ives ,ess than 1 % R 3 

gain error. 




TL/H/7057-6 



Fast Inverting Amplifier with High Input Impedance 

ci 

SpF 




Non-Inverting AC Amplifier 

i 



OUTPUT "±S 




+ ^ R1 + R2 

VoUT = J^j V IN 

R|N = R3 
R3 = R1//R2 

TL/H/7057-8 



i L_|H 



70 



Practical Differentiator 

C2 



o vw o 




2ttR1C1 2ttR2C2 

I C ' Tf! < T ur) ity g3j n 



30 pF 



Integrator 

HI 



> 

CO 



R3 
100 



2 INTEGRATE 
1 RESET 



1 p 2 3 

VouT= -mcTj tl v 'Ndt 



" 2irR1C1 
R1 = R2 



f 




TL/H/7057-9 For rr| i r, i rnurn offset error due — 

to input bias current 



TL/H/7057-10 



R1 
V,n— *+/*- 



Fast Integrator 

C3 



r 



C2 
10 pF 



■ VquT 



CI 
150pF 



Circuit for Operating the LM101 
without a Negative Supply 

R1 R2 

— vw 




TL/H/7057-11 



Current to Voltage Converter 




VQUT = llN R1 



For minimum error due to 
bias current R2 = R1 



TL/H/7057-12 



Circuit for Generating the 
Second Positive Voltage 




R1 
10K 

1% 



CI > t 

lOpF J_ 1 



TL/H/7057-13 



TL/H/7057-14 



71 



Neutralizing Input Capacitance 
to Optimize Response Time 



Double-Ended Limit Detector 




TL/H/7057-15 

Integrator with Bias Current Compensation 



v IN — ^^-H^ 




V UT = 4 -6V for 

V LT <; V, N £ V UT 

Vout = OV for 
Vin < V L t or V| N > V UT 
TL/H/7057-19 




V,n — • 



Multiple Aperture Window Discriminator 

3 



•Adjust for zero integrator drift. 
Current drift typically 0.1, n/A°C 
over -55°Cto125 C 
temperature range. 



TL/H/7057-16 



Voltage Comparator for Driving 
DTL or TTL Integrated Circuits 



OUTPUT 




TL/H/7057-17 



Threshold Detector for Photodiodes 




LM101A ^—OUTPUT 




V 1N >V 4 



V 3 <V IN <V 4 



V 2 <V,n<V 3 



V,n>V, 



TL/H/7057-20 



TL/H/7057-18 



72 



Offset Voltage Adjustment for Inverting Amplifiers Offset Voltage Adjustment for Non-Inverting Amplifiers 



Using Any Type of Feedback Element 

R3 




+ V 



RS 
SOK 



L 200K 

-v 5J 



R2 
00 J 2 



RANGE = ±V 



(S) 



Using Any Type of Feedback Element 

RS 




■OUTPUT 



GAIN = 1 + ■ 



R4 + R2 
TL/H/7057-22 



TL/H/7057-21 



Offset Voltage Adjustment for Voltage Followers 



R2 
1MK 



I 2M 

>4W • 



R3 
IK 

■AAAr 



n 




-»(S) 



TL/H/7057-23 



Offset Voltage Adjustment for Differential Amplifiers 

R2 

— W/S» 




■OUTPUT 



"V 

R2 = R3 + R4 



V,R4/ \R1 + R3/ 



GAIN = p 
R1 



TL/H/7057-24 



Offset Voltage Adjustment for Inverting 
Amplifiers Using 10 kn Source Resistance or Less 

+ v 

R3 

— ws» 




RANGE = ±V I 



TL/H/7057-25 



73 



SECTION 2 — SIGNAL GENERATION 

Low Frequency Sine Wave Generator with Quadrature Output 

C2 
0.02 nf 

1% 



R1 
Z2M 

1% 

-vs/v- 

ci 

0.01 mF" 
IS" 



SINE 
OUTPUT 



I o " 1 Hi 




■^AAr 



COSINE 
OUTPUT 



High Frequency Sine Wave Generator with Quadrature Output 




■ COSINE OUTPUT 



f = 10 kHz 



TL/H/7057-26 



TL/H/7057-27 



74 



Free-Running Multivibrator 

R1 
160K 

vsa» 



ci*. 

0.01 nf ' 




' Equt 



Chosen for oscillation at 100 Hz 

TL/H/7057-28 



Wein Bridge Sine Wave Oscillator 

R3 
750 

— V^ 



> 

CO 




'Eldema 1869 
10V, 14 mA Bulb 



TL/H/7057-29 



Function Generator 

Square Wtvt Output 



CI 

0.1 xF 




R1 ' R2 

I0K 1M 



-WNr 

RS 



TL/H/7057-30 



Pulse Width Modulator 



R1 
INK 



CI 
.47 mF 




toon > 



02 
1.2V 



Vqut 



01 
6.2V 



75 



Bilateral Current Source 



Bilateral Current Source 




Rt 
100K 
0.1S 

■AAAr 



R2 
100K 
0.1% 




I 

t > 49.5K 

[ < 0.1% 'out I 

I ' 



R1 
2M 

1% 



IOUT ; 



R3V| N 



TL/H/7057-32 



R3 

1M 

1% 

-AAAr 




-^AAr 



TL/H/7057-33 



Wein Bridge Oscillator with FET Amplitude Stabilization 




t — r^ir 

> -J— C2 .01 nf 

> — I— .01(iF 



2N290S 



X 



100K 



100K 



R1 = R2 
C1 = C2 




1S0K 



10 uf 



4—- 15 



TL./H/7057-34 



76 



Low Power Supply for Integrated Circuit Testing 



+41V 



03 , 
1N759 
12V 



1 — n — I **\ 

> R3 > R5 > TRIM 

>5.1K >1.2K >F0R 

04 <'* <1% <I C 2=100 

J?LM103 I •IT-"' ^J 



Q1 
2N2605 



02 
2N2605 




R1 I "• 

8.2K I I • O-^AAr— O— -I 




TL/H/7057-35 




<>— v 



OS 
1N759 
12V 




VN/Sr— O— i 



TL/H/7057-91 



Positive Voltage Reference 




TL/H/7057-36 



77 



CO 

z 

< 



Negative Voltage Reference 



Negative Voltage Reference 



i— WSr-4- 




r 



D1 

1N4611 

6.6V 




TL/H/7057-39 













TL/H/7057-38 


Precision Current Sink 






V 

• 


;* 












3 






N 


+ 








2 




LM107 


x H^ 2N3456 












m—4 ^ 










T L2N2219 








R2> 










10K> 




. V| N 

l0 = iT 




R1> 


V|N- 


ov 











Precision Current Source 




TL/H/7057-41 



TL/H/7057-40 



SECTION 3 — SIGNAL PROCESSING 



Differential-Input Instrumentation Amplifier 




inputs ( r-A/Wr-< > , ALAMCE 



R2 R4 

IK INK 

0.1% 0.1% 

*— WN» — f W\r 



■AA/V- 

R3 
IK 




R4 = R5 
R2 R3 

R4 

INK - A V = — 

0.1% HZ 



•— Wv 1 

RS -L 



TL/H/7057-42 



78 



Variable Gain, Differential-Input Instrumentation Amplifier 



INPUTS •>— ^^-0# 
R1 
IK 




> 
CO 



TL/H/7057-43 



R1 = R5 = 10R2 
R2 = R3 



Instrumentation Amplifier with ± 100 Volt Common Mode Range 



R6 
SOK 
0.1% 

-wv- 

C4 




R1* 
SOK 

0.1% 



3pF 



HH 




- INPUTS - 



<: R 



R7* 
SOK 

1% 



R3 = R4 

R1 = R6 = 10R3 



'tMatching determines common 
mode rejection. 



79 



Instrumentation Amplifier with ± 10 Volt Common Mode Range 




R1 = R4 
R2 = R5 
R6 = R7 
t'Matching Determines CMRR 

R6/ 
R2\ 



A V 



>\ R3 ; 



TL/H/7057-45 



High Input Impedance Instrumentation Amplifier 



r-W\rf 



•TMatching determines CMRR 

tMay be deleted to maximize bandwidth 




TL/H/7057-46 



Bridge Amplifier with Low Noise Compensation 



WV— i 




OUTPUT 



'Reduces feed through of 
power supply noise by 20 dB 
and makes supply bypassing 
unnecessary. 

tTrim for best common 
mode rejection 

fGain adjust 



TL/H/7057-47 



80 



Bridge Amplifier 

Rt 

VWr- 



Preclsion Diode 





TL/H/70S7-49 



Precision Clamp 



e iw — WA> t 




H'Eref must have a source im- 
pedance of less than 200ft if 



D2 is used. 



TL/H/7057-50 



Fast Half Wave Rectifier 

C2 
3pF 



M 
20K 



E,n- 







■Eout 



TL/H/7057-51 



Precision AC to DC Converter 



1% 



R2 
2SK 

1% 



R3 
10K 



i f WV • f WrH> 




I M |>^JL-C1 --1M14 [ H5 >^ 

I 15K -jr-150pF I S JK l l j I 

~ ~ C3* 

30 pF 

•Feedforward compensation can be used to make a fast full wave rectifier without a filter. 




TL/H/7057-52 



Low Drift Peak Detector 



03 
IN914 



20K 

-VVNr- 




1M 



n 

1N914 



I fc. ^. ln * 3 



C2 

.01 nF 




30 pF 



TL/H/7057-53 



81 



Absolute Value Amplifier with Polarity Detector 

R1 Rl 

input m VNA^ # A ^V- 




VOUT = - |V| N I X i 



R2 R4 + R3 




■OUTPUT 



r«T. 



TL/H/7057-54 



Sample and Hold 



D 



INPUT 



V m l " 1B 

— lirrpMj^ 

T J_ a* * Pc 

SAMPLE _L 




• OUTPUT 



Polycarbonate-dielectric capacitor 



TL/H/7057-55 



— lir 



Sample and Hold 

R1 
1M 

f-WV-f 



W 



'Worst case drift less than 2.5 mV/sec 
tTeflon, Polyethylene or Polycarbonate 
Dielectric Capacitor 



■ Clt 




• OUTPUT 



TUH/7057-56 



82 



Low Drift Integrator 




> 

Z 
■ 

CO 



•Q1 and Q3 should not have internal gate-protection diodes. 



TL/H/7057-57 
Worst case drift less than 500 /xWsec over -55°C to + 125°C. 



Fastt Summing Amplifier with Low Input Current 

est 



INPUT— —tffr. 



-WSr- 



' In addition to increasing speed, the LM101 A raises high and low frequency 
gain, increases output drive capability and eliminates thermal feedback. 




t Power Bandwidth: 250 kHz 
Small Signal Bandwidth: 3.5 MHz 
Slew Rate: 10V/fis 



t C5 



6 X 10-8 



TL/H/7057-58 



83 



Fast Integrator with Low Input Current 

D1 



input '\M\r- 



R1 
150K 



CI 
0.002 nf 




►J • vw 



1 



tt 



C3- 
0.002 »f ' 



R2 

1M 

-VW- 



., •Hh-.. 

_1_ l_C4 



cs 

10 pF 



150 pF 



£lM 




TL/H/7057-59 



Win- 



f = 



2ttR1C1 
= 60 Hz 
R1 = R2 = R3 
C1 = C2 = C23 



Adjustable Q Notch Filter 



R1 
10M 

-VWr 



R2 
10M 



C3 
S40pF 



T-7 

CR3 
<5M 



CI 
270 pF 





VOUT 



fR4 
■OK 



TL/H/7057-60 



84 



Easily Tuned Notch Filter 

R3 



R1 
4K 
0.1% 

R2 
4K 
0.1% 



R4 = R5 
R1 = R3 
R4 = y, R1 



»0 = 



2irR4VC1C2 



CI 
500 pf •*- 



R4 
2K 

0.1% 



R5 

2K 

0.1% 




-A D 




C2 



Tuned Circuit 




C2 C1 

1.1 ^F 0.33 jrf^ R1 

.100K 



2irVR1R2C1C2 




TL/H/7057-61 



Two-Stage Tuned Circuit 




2WR1R2C1C2 



TL/H/7057-63 



85 



Negative Capacitance Multiplier 




R3 



R S = 



VqS + R2 Iqs 

R3 

R3(R1 + R| N ) 



R| N A v0 



TL/H/7057-65 



(-§)< 



Variable Capacitance Multiplier 




R1 
IK 



R2 

10K 



-s-J X 



*— vw- 



ci 




TL/H/7057-66 



Simulated Inductor 




Capacitance Multiplier 

R2 
10M 



TL/H/70S7-67 




R3 



•L = 



v s + Iqs R1 



R3 



R S = R3 



TL/H/7057-68 



86 



High Pass Active Filter 

R1 
11 OK 

I — VSAr-#— — 



> 

Z 
■ 



C1» 
0.01 uf 



HM 



0.01 *iF 



I M l T 1 

< n 

S 110K 




+ OUTPUT 



TL/H/7057-71 



'Values are for 1 00 Hz cutoff. Use metalized polycarbonate capacitors for good temperature stability. 



Low Pass Active Filter 

cr 



940 pF 




TL/H/7057-72 



'Values are for 1 kHz cutoff. Use silvered mica capacitors for good temperature stability. 



Nonlinear Operational Amplifier with Temperature Compensated Breakpoints 

RS R6 



187.5K 



r sAA ^w- 7 

| R3 

/¥ 700K 

< > — ^oi > 4 WAr- 



S0K 

■AAAr 



2N2MS 
V" ■ -15V 



INPUT. 



R1 
10K 

■AAAr 



2N260S 




•OUTPUT 



TL/H/7057-73 



87 



Current Monitor 



INPUT 
VOLTAGE* 



R2 
100 

IS 




MONITOR 
OUTPUT ■ 

•SK 
'IX 




w _ m R3 , 



TL/H/7057-74 



Saturating Servo Preamplifier with 
Rate Feedback 

n, LM103 „, 



-l—T 

270 S 

CI— 1— O 

50/jF_— 



— 1.6K 



#1^ 



^4 



R3 
100K 

-WAr 




•OUTPUT 



TL/H/7057-75 



Power Booster 



INPUTS 




R2' 
470! 



■OUTPUT 



< 



02 
2N2219 



TL/H/7057-76 



88 



Analog Multiplier 

v + 



F 




VOUT 



TL/H/7057-77 



Long Interval Timer 

RESET 

"*~ D1 02 

IM57 IN4S7 



Fast Zero Crossing Detector 



0K * 



R1 ' 
75K 



R3 
ISM 




INPUT 



OUTPUT 7 



•Low leakage -0.017 jiF per second delay 



TL/H/7057-78 




TL/H/7057-79 



Amplifier for Piezoelectric Transducer 

■ OUTPUT 



10«iF 




Propagation delay approximately 200 ns 
tDTL or TTL fanout of three. 
Minimize stray capacitance 
Pin 8 



Temperature Probe 

PROBE 






T 



TRANSDUCER 



R2 
12K 



/ 93i > | yvv 

I LM107 ^> m 

<>__£*£ 1 1 +^^ 

. ► "3* >R5 ^ 

> 250K > M 3k 



RS 
24.3K 

IX 'Set for 0V at 0°C 

t Adjust for 100mV/°C 



"ST Low frequency cutoff = R1 C1 

TL/H/7057-80 



TL/H/7057-81 



89 



Photodiode Amplifier 




"VouT 



Vout = R1 Id 



TL/H/7057-82 



Photodiode Amplifier 

R1 
SM 

1% 

^r^A» 




TL/H/7067-83 



'Operating photodiode with less than 3 mV 
across it eliminates leakage currents. 



High Input Impedance AC Follower 



INPUT 




TL/H/7057-84 



R S 
INPUT — ^W- 



Temperature Compensated Logarithmic Converter 

V + • 15V 

X* T 1Z1 





«3* 

1.SM 
IS 



t1 kfl ( ± 1 %) at 25*C, + 3500 ppm/'C. 

Available from Vishay Uttronix, 

Grand Junction, CO, Q81 Series. 
'Determines current for zero 

crossing on output 10 jiA 

as shown. 



TL/H/70S7-85 



10 nA < l| N < 1 mA 
Sensitivity is 1V per decade 



90 



Multiplier/Divider 



E. -VNAr-4^ ~\ 300 PF -T- » TT 



RS 
100K 
1% 

£ 3 -VSAr-#- 



— C6 

150 pF 




2K 



H4 
IKK 

1% 



2N2920 



l^r 




TL/H/7057-87 



Cube Generator 



"• r 

iook 1 2 



r-^n 



Wr 

RIO 15.7K 

4.55K 1% 

1% 





HH 



V 




TL/H/7057-88 



92 



Fast Log Generator 



Eref 1SV 




CI 
300 pF 



Hr-HH 



150 pF 

| t1 kn(±1%)at25"i 



> 

Z 
■ 



'C, +3500 ppm/°C. 
Available from Vishay Ultronix, 
Grand Junction, CO, Q81 Series. 



C2 C3 

75 pF IpF 



Eref 15V 

< 1S0K 
IX 



Anti-Log Generator 



2N2920 



R6 
10K 
1% 



20pF-r- >2K _L II 



4 — ' 




HH 



150 pF 




HH 

C3 
150 pf 



t1 kn (± 1 %) at 25"C, + 3500 ppm/'C. 
Available from Vishay Ultronix, 
Grand Junction, CO, Q81 Series. 

TL/H/7057-90 



93 



CM 
CO 



FET Circuit Applications 



National Semiconductor 
Application Note 32 




input O 




OUTPUT 



SAMPLE 'Polycarbonate dielectric 

+15V SAMPLE 



~i_r 

1—1-15' 



15V HOLD 

TL/H/6791-1 

Sample and Hold With Offset Adjustment 

The 2N4339 JFET was selected because of its low Iqss a9 e - Leakages of this level put the burden of circuit perform- 
(<100 pA), very-low Id(OFF) (<50 PA) and low pinchoff volt- ance on clean, solder-resin free, low leakage circuit layout. 



s* 



Hr 



cjy 



-0+15V 



( JX)'""' 3 ™>^o 



OVERRIDE 



OUTPUT 



o 

-15V 
Long Time Comparator 



TL/H/6791 -2 



The 2N4393 is operated as a Miller integrator. The high Yf S 
of the 2N4393 (over 1 2,000 jumhos @ 5 mA) yields a stage 
gain of about 60. Since the equivalent capacitance looking 
into the gate is C times gain and the gate source resistance 
can be as high as 10 Mft, time constants as long as a 
minute can be achieved. 



input O— VW 




Ov+ 



> O OUTPUT 



2N3686 



TL/H/6791 -3 



JFET AC Coupled Integrator 

This circuit utilizes the "ju.-amp" technique to achieve very 
high voltage gain. Using Ci in the circuit as a Miller integra- 
tor, or capacitance multiplier, allows this simple circuit to 
handle very long time constants. 



94 



♦30V 




GO 

ro 



OUTPUT 



TL/H/6791 -4 



Ultra-High Z IN AC Unity Gain Amplifier 



Nothing is left to chance in reducing input capacitance. The 
2N4416, which has low capacitance in the first place, is 
operated as a source follower with bootstrapped gate bias 



resistor and drain. Any input capacitance you get with this 
circuit is due to poor layout techniques. 



SHUNT 
PEAKING COIL 





O OUTPUT 



TL/H/6791 -6 



TL/H/6791 -5 



FET Cascode Video Amplifier 



The FET cascode video amplifier features very low input 
loading and reduction of feedback to almost zero. The 
2N3823 is used because of its low capacitance and high 
Yf S . Bandwidth of this amplifier is limited by Rl and load 
capacitance. 



J FET Pierce Crystal Oscillator 

The JFET Pierce crystal oscillator allows a wide frequency 
range of crystals to be used without circuit modification. 
Since the JFET gate does not load the crystal, good Q is 
maintained thus insuring good frequency stability. 



95 



2M 



SV S1 

-CH— O— 



-Oiv 



7 



^sv 



■Oiov 



-O50V 



«_LO 



X 



-Oioov 



-Q500V 



-O iooov 



s 




S2A 



TL/H/6791-7 



FETVM-FET Voltmeter 



This FETVM replaces the function ot the VTVM while at the 
same time ridding the instrument of the usual line cord. In 
addition, drift rates are far superior to vacuum tube circuits 



allowing a 0.5 volt full scale range which is impractical with 
most vacuum tubes. The low-leakage, low-noise 2N4340 is 
an ideal device for this application. 



'^Hr 




I0K 

-WSr- 



f vyv • 



10K 

-vs/v- 




■O OUTPUT 



TL/H/6791-8 



HI-FI Tone Control Circuit (High Z Input) 

The 2N3684 JFET provides the function of a high input amp-operated feedback type tone control circuit, 

impedance and low noise characteristics to buffer an op 



96 



DIFFERENTIAL 

INSTRUMENT 

INPUT 



o— vw 



(HWV 



DIFFERENTIAL O 
INSTRUMENT 

INPUT O- 







SCALING RESISTORS 



-VW 



TU/H/6791-10 



Differential Analog Switch 



The FM1208 monolithic dual is used in a differential multi- 
plexer application where Rds(ON) should be closely 
matched. Since Rds(ON) for the monolithic dual tracks 
at better than ±1% over wide temperature ranges 



(-25 to + 125°C), this makes it an unusual but ideal choice 
for an accurate multiplexer. This close tracking greatly re- 
duces errors due to common mode signals. 




VW— - O'sv 



004 jjF -i 



820K .0015 uF 



Magnetic-Pickup Phono Preamplifier 



TL/H/6791-11 



This preamplifier provides proper loading to a reluctance 
phono cartridge. It provides approximately 25 dB of gain at 
1 kHz (2.2 mV input for 100 mV output), it features S + N/N 



ratio of better than -70 dB (referenced to 10 mV input at 
1 kHz) and has a dynamic range of 84 dB (referenced to 
1 kHz). The feedback provides for RIAA equalization. 



97 



CM 

CO 




GAIN CONTROL 



TL/H/6791-12 



Variable Attenuator 

The 2N3685 acts as a voltage variable resistor with an 
R DS(ON) of 800a max. The 2N3685 JFET will have linear 
resistance over several decades of resistance providing an 
excellent electronic gain control. 



BIPOLAR 
LOGIC 




TL/H/6791-13 

Negative to Positive Supply Logic Level Shifter 

This simple circuit provides for level shifting from any logic 
function (such as MOS) operating from minus to ground 
supply to any logic level (such as TTL) operating from a plus 
to ground supply. The 2N3970 provides a low rd S (ON) a nd 
fast switching times. 




TL/H/6791-14 



Voltage Controlled Variable Gain Amplifier 



The 2N4391 provides a low Rds(ON) ('ess than 30H). The 
tee attenuator provides for optimum dynamic linear range 
for attenuation and if complete turnoff is desired, attenua- 



tion of greater than 100 dB can be obtained at 10 MHz 
providing proper RF construction techniques are employed. 



<> OVOUT 




v,„0 



Ultra-High Gain Audio Amplifier 



Av = T = 500 TYPICAL 



TL/H/6791-15 



Sometimes called the "JFET" ju, amp," this circuit provides 
a very low power, high gain amplifying function. Since jx of a 
JFET increases as drain current decreases, the lower drain 



current is, the more gain you get. You do sacrifice input 
dynamic range with increasing gain, however. 



98 




10 



OUTPUT 



Level-Shiftlng-lsolation Amplifier 



TL/H/6791-16 



The 2N4341 JFET is used as a level shifter between two op 
amps operated at different power supply voltages. The 



JFET is ideally suited for this type of application because 
Id = Is- 



NIXIE* READOUT TUBE 




Trademark of the 
Burroughs Corp. 

TL/H/6791-17 



FET Nixie* Drivers 



The 2N3684 JFETs are used as Nixie tube drivers. Their V p 
of 2-5 volts ideally matches DTL-TTL logic levels. Diodes 
are used to a +50 volt prebias line to prevent breakdown of 
the JFETs. Since the 2N3684 is in a TO-72 (4 lead TO-18) 
package, none of the circuit voltages appear on the can. 
The JFET is immune to almost all of the failure mechanisms 
found in bipolar transistors used for this application. 




TL/H/6791-18 



Precision Current Sink 

The 2N3069 JFET and 2N2219 bipolar have inherently high 
output impedance. Using R-| as a current sensing resistor to 
provide feedback to the LM101 op amp provides a large 
amount of loop gain for negative feedback to enhance the 
true current sink nature of this circuit. For small current val- 
ues, the 10k resistor and 2N2219 may be eliminated if the 
source of the JFET is connected to R-|. 



99 



CM 

CO 




O+200V 



nxn<l 




TL/H/6791-19 



JFET-Blpolar Cascode Circuit 



The JFET-Bipolar cascode circuit will provide full video out- 
put for the CRT cathode drive. Gain is about 90. The cas- 
code configuration eliminates Miller capacitance problems 
with the 2N4091 JFET, thus allowing direct drive from the 



output o 



video detector. An m derived filter using stray capacitance 
and a variable inductor prevents 4.5 MHz sound frequency 
from being amplified by the video amplifier. 




15V (SAMPLE) 
20V (HOLD) 



_TLT 

Low Drift Sample and Hold 



'Polycarbonate dielectric capacitor 



TL/H/6791-20 



The JFETs, Qi and Cfe, provide complete buffering to C-|, 
the sample and hold capacitor. During sample, Q-) is turned 
on and provides a path, r,j 8 (ON), for charging C n . During 
hold, Qi is turned off thus leaving Qi Id(OFF) ( <50 P A ) 



and Q2 Igss (<100 pA) as the only discharge paths. Q2 
serves a buffering function so feedback to the LM101 and 
output current are supplied from its source. 



100 




PEAK OUTPUT VOITAM 
V, « V, + 1V 




CO 



SIGNAL O 



TL/H/6791-21 

Wein Bridge Sine Wave Oscillator 

The major problem in producing a low distortion, constant 
amplitude sine wave is getting the amplifier loop gain just 
right. By using the 2N3069 JFET as a voltage variable resis- 
tor in the amplifier feedback loop, this can be easily 
achieved. The LM103 zener diode provides the voltage ref- 
erence for the peak sine wave amplitude; this is rectified 
and fed to the gate of the 2N3069, thus varying its channel 
resistance and, hence, loop gain. 



O OUTPUT 



O +15V 



TL/H/6791-22 



JFET Sample and Hold Circuit 



The logic voltage is applied simultaneously to the sample 
and hold JFETs. By matching input impedance and feed- 
back resistance and capacitance, errors due to rd S (ON) of 
the JFETs is minimized. The inherent matched r ds(0 N) and 
matched leakage currents of the FM1109 monolithic dual 
greatly improve circuit performance. 



VinO 




•— OV OU , 



TL/H/6791-23 

High Impedance Low Capacitance Wideband Buffer 

The 2N4416 features low input capacitance which makes 
this compound-series feedback buffer a wide-band unity 
gain amplifier. 




VOUT 



TL/H/6791 -24 

High Impedance Low Capacitance Amplifier 

This compound series-feedback circuit provides high input 
impedance and stable, wide-band gain for general purpose 
video amplifier applications. 



101 



CM 
CO 



0«12V 






•O OUTPUT 



TL/H/6791-25 

Stable Low Frequency Crystal Oscillator 

This Colpitts-Crystal oscillator is ideal for low frequency 
crystal oscillator circuits. Excellent stability is assured be- 
cause the 2N3823 JFET circuit loading does not vary with 
temperature. 



V,nO— !► 




TL/H/6791-26 



to 360° Phase Shifter 



Each stage provides 0° to 180° phase shift. By ganging the 
two stages, 0° to 360° phase shift is achieved. The 2N3070 
JFETs are ideal since they do not load the phase shift net- 
works. 



Io -tOi — r 

I t I .I2N4N0 



S±t>-r> 



on 
m 

INPUT 
CONTROL 



S=PO-> 



I MM 

-N- 



-VW- 



; °— tCh — n 

1 (J— . I 2N4W0 



•to 



-vw- 




DM7M0 

VOLTAGE 

TRANSLATOR 



DTL-TTL Controlled Buffered Analog Switch 



TL/H/6791-27 



This analog switch uses the 2N4860 JFET for its 25 ohm 
roN and low leakage. The LM102 serves as a voltage buffer. 
This circuit can be adapted to a dual trace oscilloscope 



chopper. The DM7800 monolithic I.C. provides adequate 
switch drive controlled DTL-TTL logic levels. 




I.IK 

*-A*W-Ov DD 



20 MHz OSCILLATOR VALUES 
C1 « 700 pF L1 = 1.3 jiH 
C2 = 75 pF L2 = 10T »/,' DIA %" LONG 

V D D = 16V l D = 1 itiA 

20 MHz OSCILLATOR PERFORMANCE 

LOW DISTORTION 20 MHz OSC 

2ND HARMONIC -60 dB 

3RD HARMONIC > -70 dB 



TL/H/6791-28 

Low Distortion Oscillator 



The 2N4416 JFET is capable of oscillating in a circuit where 
harmonic distortion is very low. The JFET local oscillator 



is excellent when a low harmonic content is required for a 
good mixer circuit. 



L 



102 




CO 



AGC RANGE H« 
POWER GAIN 17 it 



JL 11 * .07 pHy CENTER TAP 

~ 12 -. J7 (iHy TAP % UP f ROM GROUND 



200 MHz Cascode Amplifier 



TL/H/6791-29 



This 200 MHz JFET cascode circuit features low crossmo- 
dulation, large-signal handling ability, no neutralization, and 
AQC controlled by biasing the upper cascode JFET. The 



only special requirement of this circuit is that loss of the 
upper unit must be greater than that of the lower unit. 




FET Op Amp 



TL/H/6791-30 



The FM3954 monolithic-dual provides an ideal low-offset, 
low-drift buffer function for the LM101 A op amp. The excel- 
lent matching characteristics of the FM3954 track well over 



its bias current range thus improving common mode rejec- 
tion. 




."LP 



High Toggle Rate High Frequency Analog Switch 



This commutator circuit provides low impedance gate drive 
to the 2N3970 analog switch for both on and off drive condi- 
tions. This circuit also approaches the ideal gate drive con- 
ditions for high frequency signal handling by providing a low 



ac impedance for off drive and high ac impedance for on 
drive to the 2N3970. The LH0005 op amp does the job of 
amplifying megahertz signals. 



103 



CM 

eo 



£nD-D^H* 



DTL 

TTt 

INPUTS 



trCH>^-w- 



DM7800 
VOLTAGE TRANSLATOR 



S±D-i>r-* 



OTL 

TTL 

INPUTS 



i i 

DM7000 
VOLTAGE TRANSLATOR 



2N4UVI Jf-tIS 



4-Channei Commutator 



-O INPUT I 



-O INPUT 2 



-O INPUT 3 



■O INPUT 4 



•O OUTPUT 



TL/H/6791-32 



This 4-channel commutator uses the 2N4091 to achieve low 
channel ON resistance (<30ft) and low OFF current leak- 
age. The DM7800 voltage translator is a monolithic device 



which provides from +10V to -20V gate drive to the 
JFETs while at the same time providing DTL-TTL logic com- 
patability. 



R1 

o.i 

POSITIVE 1% 

INPUT ^ + */>At + 
VOLTAGE 



MONITOR 

OUTPUT 

5V7A 

R1 R3 



R2 
100 

1% 



UT " R2 ' L > i 

1 



© 



2N36S4 



•O TO LOAD 




TL/H/6791-34 



Current Monitor 



R-i senses current flow of a power supply. The JFET is used 
as a buffer because lp = Is. therefore the output monitor 



voltage accurately reflects the power supply current flow. 



104 



TO COMPANION CHANNEL 
FOR STEREO CIRCUIT 



O +1SV 




CO 
ro 



TL/H/6791-35 



Low Cost High Level Preamp and Tone Control Circuit 



This preamp and tone control uses the JFET to its best 
advantage; as a low noise high input impedance device. All 
device parameters are non-critical yet the circuit achieves 
harmonic distortion levels of less than 0.05% with a S/N 



ratio of over 85 dB. The tone controls allow 1 8 dB of cut and 
boost; the amplifier has a 1 volt output for 1 00 mV input at 
maximum level. 




2N2219 



Precision Current Source 

The 2N3069 JFET and 2N2219 bipolar serve as voltage 
devices between the output and the current sensing resis- 
tor, R-). The LM101 provides a large amount of loop gain to 
assure that the circuit acts as a current source. For small 
values of current, the 2N2219 and 10k resistor may be elimi- 
nated with the output appearing at the source of the 
2N3069. 



input O 




0+12V 



TL/H/6791 -37 



Schmitt Trigger 



This Schmitt trigger circuit is "emitter coupled" and provides 
a simple comparator action. The 2N3069 JFET places very 
little loading on the measured input. The 2N3565 bipolar is a 
high hpE transistor so the circuit has fast transition action 
and a distinct hysteresis loop. 



105 



CM 
CO 



y SUPPLY 



^ 



fi 



2N4338 

G s ' Spmho mix. 

OVqut 



LM103 



TL/H/6791-38 



Low Power Regulator Reference 



This simple reference circuit provides a stable voltage refer- power supply rejection exceeds 100 dB. 
ence almost totally free of supply voltage hash. Typical 



VIDEO INPUT 

son 



2N4391 




21*4391 



& 




I OON 6 OFF J_ 



■© 



y\A VIDEO OUTPUT 

' son 



ATTENUATION > 80 dB ® 100 MHz 
INSERTION LOSS « 6 dB 



y 



TL/H/6791-39 



High Frequency Switch 



The 2N4391 provides a low on-resistance of 30 ohms and a and an "ideal" switch, the performance stated above can 
high off-impedance (<0.2 pF) when off. With proper layout be readily achieved. 



106 



Precision IC Comparator 
Runs from + 5V 
Logic Supply 

Robert J. Widlar 
Apartado Postal 541 
Puerto Vallarta, Jalisco 
Mexico 

introduction 

In digital systems, it is sometimes necessary to convert low 
level analog signals into digital information. An example of 
this might be a detector for the illumination level of a photo- 
diode. Another would be a zero crossing detector for a mag- 
netic transducer such as a magnetometer or a shaft-posi- 
tion pickoff. These transducers have low-level outputs, with 
currents in the low microamperes or voltages in the low mil- 
livolts. Therefore, low level circuitry is required to condition 
these signals before they can drive logic circuits. 
A voltage comparator can perform many of these precision 
functions. A comparator is essentially a high-gain op amp 
designed for open loop operation. The function of a compar- 
ator is to produce a logic "one" on the output with a positive 
signal between its two inputs or a logic "zero" with a nega- 
tive signal between the inputs. Threshold detection is ac- 
complished by putting a reference voltage on one input and 
the signal on the other. Clearly, an op amp can be used as a 
comparator, except that its response time is in the tens of 
microseconds which is often too slow for many applications. 
A unique comparator design will be described here along 
with some of its applications in digital systems. Unlike older 
IC comparators or op amps, it will operate from the same 5V 
supply as DTL or TTL logic circuits. It will also operate with 
the single negative supply used with MOS logic. Hence, low 
level functions can be performed without the extra supply 
voltages previously required. 

The versatility of the comparator along with the minimal cir- 
cuit loading and considerable precision recommend it for 
many uses, in digital systems, other than the detection of 
low level signals. It can be used as an oscillator or multivi- 
brator, in digital interface circuitry and even for low voltage 
analog circuitry. Some of these applications will also be dis- 
cussed. 

circuit description 

In order to understand how to use this comparator, it is nec- 
essary to look briefly at the circuit configuration. Figure 1 
shows a simplified schematic of the device. PNP transistors 



National Semiconductor 
Application Note 41 



S 




TL/H/7303-1 

Figure 1. Simplified schematic of the comparator 

buffer the differential input stage to get low input currents 
without sacrificing speed. The PNP's drive a standard NPN 
differential stage, Q3 and Q4. The output of this stage is 
further amplified by the Q 5 — Q 6 pair. This feeds Qg which 
provides additonal gain and drives the output stage. Current 
sources are used to determine the bias currents, so that 
performance is not greatly affected by supply voltages. 



107 



The output transistor is Q-| 1 , and it is protected by Qi o and 
R6 which limit the peak output current. The output lead, 
since it is not connected to any other point in the circuit, can 
either be returned to the positive supply through a pull-up 
resistor or switch loads that are connected to a voltage 
higher than the positive supply voltage. The circuit will oper- 
ate from a single supply if the negative supply lead is con- 
nected to ground. However, if a negative supply is available, 
it can be used to increase the input common mode range. 
Table I summarizes the performance of the comparator 
when operating from a 5V supply. The circuit will work with 

Table I. Important electrical characteristics of the 
LM111 comparator when operating from single, 
5V supply (T A = 25°C) 



Parameter 


Limits 


Units 


Min 


Typ 


Max 


Input Offset Voltage 




0.7 


3 


mV 


Input Offset Current 




4 


10 


nA 


Input Bias Current 




60 


100 


nA 


Voltage Gain 




100 




V/mV 


Response Time 




200 




ns 


Common Mode Range 


0.3 




3.8 


V 


Output Voltage Swing 






50 


V 


Output Current 






50 


mA 


Fan Out (DTL/TTL) 


8 








Supply Current 




3 


5 


mA 



supply voltages up to ±1 5V with a corresponding increase 
in the input voltage range. Other characteristics are essen- 
tially unchanged at the higher voltages. 

low level applications 

A circuit that will detect zero crossing in the output of a 
magnetic transducer within a fraction of a millivolt is shown 
in Figure 2. The magnetic pickup is connected between the 
two inputs of the comparator. The resistive divider, Ri and 
R2, biases the inputs 0.5V above ground, within the com- 




mon mode range of the IC. The output will directly drive DTL 
or TTL. The exact value of the pull up resistor, R5, is deter- 
mined by the speed required from the circuit since it must 
drive any capacitive loading for positive-going output sig- 
nals. An optional offset-balancing circuit using R3 and R4 is 
included in the schematic. 

Figure 3 shows a connection for operating with MOS logic. 
This is a level detector for a photodiode that operates off a 
-10V supply. The output changes state when the diode 
current reaches 1 juA Even at this low current, the error 
contributed by the comparator is less than 1 %. 




TL/H/7303-3 

Figure 3. Level detector for photodiode 

Higher threshold currents can be obtained by reducing R1, 
R2 and R3 proportionally. At the switching point, the voltage 
across the photodiode is nearly zero, so its leakage current 
does not cause an error. The output switches between 
ground and -10V, driving the data inputs of MOS logic di- 
rectly. 

The circuit in Figure 3 can, of course, be adapted to work 
with a 5V supply. At any rate, the accuracy of the circuit will 
depend on the supply-voltage regulation, since the refer- 
ence is derived from the supply. Figure 4 shows a method 




TL/H/7303-2 

Figure 2. Zero crossing detector for magnetic transducer 



TL/H/7303-4 

Figure 4. Precision level detector for photodiode 

of making performance independent of supply voltage. D1 is 
a temperature-compensated reference diode with a 1.23V 
breakdown voltage. It acts as a shunt regulator and delivers 
a stable voltage to the comparator. When the diode current 
is large enough (about 10 ju,A) to make the voltage drop 



108 




across R3 equal to the breakdown voltage of D-|, the output 
will change state. R 2 has been added to make the threshold 
error proportional to the offset current of the comparator, 
rather than the bias current. It can be eliminated if the bias 
current error is not considered significant. 
A zero crossing detector that drives the data input of MOS 
logic is shown in Figure 5. Here, both a positive supply and 

■ V + = 5V 



1 — TO MOS 

LOGIC 



- V = -10V - 

TL/H/7303-5 

Figure 5. Zero crossing detector driving MOS logic 

the -10V supply for MOS circuits are used. Both supplies 
are required for the circuit to work with zero common-mode 
voltage. An alternate balancing scheme is also shown in the 
schematic. It differs from the circuit in Figure 2 in that it 
raises the input-stage current by a factor of three. This in- 
creases the rate at which the input voltage follows rapidly- 
changing signals from 7V/ju.s to 18V/jm.s. This increased 
common-mode slew can be obtained without the balancing 
potentiometer by shorting both balance terminals to the 
positive-supply terminal. Increased input bias current is the 
price that must be paid for the faster operation. 

digital interface circuits 

Figure 6 shows an interface between high-level logic and 
DTL or TTL The input signal, with 0V and 30V logic states is 
attenuated to 0V and 5V by R1 and R2. R3 and R4 set up a 
2.5V threshold level for the comparator so that it switches 
when the input goes through 1 5V. The response time of the 
circuit can be controlled with C-|, if desired, to make it insen- 
sitive to fast noise spikes. Because of the low error currents 
of the LM111, it is possible to get input impedances even 
higher than the 300 kft obtained with the indicated resistor 
values. 



V + = 5V 



The comparator can be strobed, as shown in Figure 6, by 
the addition of Q1 and R5. With a logic one on the base of 
Q-i, approximately 2.5 mA is drawn out of the strobe termi- 
nal of the LM111, making the output high independent of 
the input signal. 



INPUT-^^^ 



240K 




TL/H/7303-6 

Figure 6. Circuit for transmitting data between high-lev- 
el logic and TTL 

Sometimes it is necessary to transmit data between digital 
equipments, yet maintain a high degree of electrical isola- 
tion. Normally, this is done with a transformer. However, 
transformers have problems with low-duty-cycle pulses 
since they do not preseve the dc level. 
The circuit in Figure 7 is a more satisfactory method of ob- 
taining isolation. At the transmitting end, a TTL gate drives a 
gallium-arsenide light-emitting diode. The light output is opti- 
cally coupled to a silicon photodiode, and the comparator 
detects the photodiode output. The optical coupling makes 
possible electrical isolation in the thousands of megohms at 
potentials in the thousands of volts. 
The maximum data rate of this circuit is 1 MHz. At lower 
rates ( ~ 200 kHz) R3 and C1 can be eliminated. 

multivibrators and oscillators 

The free-running multivibrator in Figure 8 is another exam- 
ple of the versatility of the comparator. The inputs are bi- 
ased within the common mode range by R1 and R2. DC 
stability, which insures starting, is provided by negative 
feedback through R3. The negative feedback is reduced at 
high frequencies by C-|. At some frequency, the positive 
feedback through R4 will be greater than the negative feed- 
back; and the circuit will oscillate. For the component values 



V + = 5V 




TL/H/7303-7 



Figure 7. Data transmission system with near-infinite ground isolation 



109 



shown, the circuit delivers a 1 00 kHz square wave output. 
The frequency can be changed by varying C-\ or by adjusting 
Ri through R 4 , while keeping their ratios constant. 
Because of the low input current of the comparator, large 
circuit impedances can be used. Therefore, low frequencies 
can be obtained with relatively-small capacitor values: it is 
no problem to get down to 1 Hz using a 1 jxF capacitor. The 
speed of the comparator also permits operation at frequen- 
cies above 1 00 kHz. 




TL/H/7303-8 
*TTL or DTL Fanout of two. 

Figure 8. Free-running multivibrator 

The frequency of oscillation depends almost entirely on the 
resistance and capacitor values because of the precision of 
the comparator. Further, the frequency changes by only 1 % 
for a 10% change in supply voltage. Waveform symmetry is 
also good, but the symmetry can be varied by changing the 
ratio of Ri to R2. 

A crystal-controlled oscillator that can be used to generate 
the clock in slower digital systems is shown in Figure 9. It is 
similar to the free running multivibrator, except that the posi- 



tive feedback is obtained through a quartz crystal. The cir- 
cuit oscillates when transmission through the crystal is at a 
maximum, so the crystal operates in its series-resonant 

V + = 5V 




TL/H/7303-9 

Figure 9. Crystal-controlled oscillator 

mode. The high input impedance of the comparator and the 
isolating capacitor, C2, minimize loading of the crystal and 
contribute to frequency stability. As shown, the oscillator 
delivers a 1 00 kHz square-wave output. 

frequency doubler 

In a digital system, it is a relatively simple matter to divide by 
any integer. However, multiplying by an integer is quite an- 
other story especially if operation over a wide frequency 
range and waveform symmetry are required. 
A frequency doubler that satisfies the above requirements is 
shown in Figure 10. A comparator is used to shape the in- 



V*-5V 




Frequency Range 
Input— 5 kHz to 50 kHz 
Output— 10 kHz to 100 kHz 

TL/H/7303-10 



Figure 10. Frequency doubler 



110 



put signal and feed it to an integrator. The shaping is re- 
quired because the input to the integrator must swing be- 
tween the supply voltage and ground to preserve symmetry 
in the output waveform. An LM1 08 op amp, that works from 
the 5V logic supply, serves as the integrator. This feeds a 
triangular waveform to a second comparator that detects 
when the waveform goes through a voltage equal to its av- 
erage value. Hence, as shown in Figure 1 1, the output of the 

FIRST COMPARATOR 
OUTPUT 



INTEGRATOR OUTPUT 



SECOND COMPARATOR 
OUTPUT 




CIRCUIT OUTPUT 



"Lnn_nr 



TL/H/7303-11 

Figure 11. Waveforms for the frequency doubler 

second comparator is delayed by half the duration of the 
input pulse. The two comparator outputs can then be com- 
bined through an exclusive-OR gate to produce the double- 
frequency output. 

With the component values shown, the circuit operates at 
frequencies from 5 kHz to 50 kHz. Lower frequency opera- 
tion can be secured by increasing both C2 and C4. 

application hints 

One of the problems encountered in using earlier IC com- 
parators like the LM710 or LM106 was that they were prone 
to erratic operation caused by oscillations. This was a direct 
result of the high speed of the devices, which made it man- 
datory to provide good input-output isolation and low-induc- 
tance bypassing on the supplies. These oscillations could 
be particularly puzzling when they occurred internally, show- 
ing up at the external terminals only as erratic dc character- 
istics. 

In general, the LM1 1 1 is less susceptible to spurious oscilla- 
tions both because of its lower speed (200 ns response time 
vs 40 ns) and because of its better power supply rejection. 
Feedback between the output and the input is a lesser prob- 
lem with a given source resistance. However, the LM111 
can operate with source resistance that are orders of mag- 
nitude higher than the earlier devices, so stray coupling be- 
tween the input and output should be minimized. With 
source resistances between 1 kfl and 10 kfl, the imped- 
ance (both capacitive and resistive) on both inputs should 
be made equal, as this tends to reject the signal fed back. 
Even so, it is difficult to completely eliminate oscillations in 



the linear region with source resistances above 1 kft, be- 
cause the 1 MHz open loop gain of the comparator is about 
80 dB. However, this does not affect the dc characteristics 
and is not a problem unless the input signal dwells within 
200 jmV of the transition level. But if the oscillation does 
cause difficulties, it can be eliminated with a small amount 
of positive feedback around the comparator to give a 1 mV 
hysteresis. 

Stray coupling between the output and the balance termi- 
nals can also cause oscillations, so an attempt should be 
made to keep these leads apart. It is usually advisable to tie 
the balance pins together to minimize the effect of this feed- 
back. If balancing is used, the same result can be accom- 
plished by connecting a 0.1 ju.F capacitor between these 
pins. 

Normally, individual supply bypasses on every device are 
unnecessary, although long leads between the comparator 
and the bypass capacitors are definitely not recommended. 
If large current spikes are injected into the supplies in 
switching the output, bypass capacitors should be included 
at these points. 

When driving the inputs from a low impedance source, a 
limiting resistor should be placed in series with the input 
lead to limit the peak current to something less than 
100 mA. This is especially important when the inputs go 
outside a piece of equipment where they could accidentally 
be connected to high voltage sources. Low impedance 
sources do not cause a problem unless their output voltage 
exceeds the negative supply voltage. However, the supplies 
go to zero when they are turned off, so the isolation is usual- 
ly needed. 

Large capacitors on the input (greater than 0.1 /xF) should 
be treated as a low source impedance and isolated with a 
resistor. A charged capacitor can hold the inputs outside the 
supply voltage if the supplies are abruptly shut off. 
Precautions should be taken to insure that the power sup- 
plies for this or any other IC never become reversed — even 
under transient conditions. With reverse voltages greater 
than 1 V, the IC can conduct excessive current, fuzing inter- 
nal aluminum interconnects. This usually takes more than 
0.5A. If there is a possibility of reversal, clamp diodes with 
an adequate peak current rating should be installed across 
the supply bus. 

No attempt should be made to operate the circuit with the 
ground terminal at a voltage exceeding either supply volt- 
age. Further, the 50V output-voltage rating applies to the 
potential between the output and the V~ terminal. There- 
fore, if the comparator is operated from a negative supply, 
the maximum output voltage must be reduced by an amount 
equal to the voltage on the V - terminal. 



111 



The output circuitry is protected for shorts across the load. It 
will not, for example, withstand a short to a voltage more 
negative than the ground terminal. Additionally, with a sus- 
tained short, power dissipation can become excessive if the 
voltage across the output transistor exceeds about 1 0V. 
The input terminals can exceed the positive supply voltage 
without causing damage. However, the 30V maximum rating 
between the inputs and the V - terminal must be observed. 
As mentioned earlier, the inputs should not be driven more 
negative than the V~ terminal. 

conclusions 

A versatile voltage comparator that can perform many of the 
precision functions required in digital systems has been pro- 
duced. Unlike older comparators, the IC can operate from 
the same supply voltage as the digital circuits. The compar- 
ator is particularly useful in circuits requiring considerable 
sensitivity and accuracy, such as threshold detectors for low 
level sensors, data transmission circuits or stable oscillators 
and multivibrators. 



The comparator can also be used in many analog systems. 
It operates from standard ± 1 5V op amp supplies, and its dc 
accuracy equals some of the best op amps. It is also an 
order of magnitude faster than op amps used as compara- 
tors. 

The new comparator is considerably more flexible than old- 
er devices. Not only will it drive RTL, DTL and TTL logic; but 
also it can interface with MOS logic or deliver ± 1 5V to FET 
analog switches. The output can switch 50V, 50 mA loads, 
making it useful as a driver for relays, lamps or light-emitting 
diodes. Further, a unique output stage enables it to drive 
loads referred to either supply or to ground and provide 
ground isolation between the comparator inputs and the 
load. 

The LM111 is a plug-in replacement for comparators like 
the LM710 and LM106 in applications where speed is not of 
prime concern. Compared to its predecessors in other re- 
spects, it has many improved electrical specifications, more 
design flexibility and fewer application problems. 



112 



IC Provides On-Card 
Regulation for 
Logic Circuits 

Robert J. Widlar 
Apartado Postal 541 
Puerto Valiarta, Jalisco 
Mexico 



National Semiconductor 
Application Note 42 



39 



introduction 

Because of the relatively high current requirements of digital 
systems, there are a number of problems associated with 
using one centrally-located regulator. Heavy power busses 
must be used to distribute the regulated voltage. With low 
voltages and currents of many amperes, voltage drops in 
connectors and conductors can cause an appreciable per- 
centage change in the voltage delivered to the load. This is 
aggravated further with TTL logic, as it draws transient cur- 
rents many times the steady-state current when it switches. 
These problems have created a considerable interest in on- 
card regulation, that is, to provide local regulation for the 
subsystems of the computer. Rough preregulation can be 
used, and the power distributed without excessive concern 
for line drops. The local regulators then smooth out the volt- 
age variations due to line drops and absorb transients. 
A monolithic regulator is now available to perform this func- 
tion. It is quite simple to use in that it requires no external 
components. The integrated circuit has three active leads — 
input, output and ground — and can be supplied in standard 
transistor power packages. Output currents in excess of 1A 
can be obtained. Further, no adjustments are required to set 
up the output voltage, and overload protection is provided 
that makes it virtually impossible to destroy the regulator. 
The simplicity of the regulator, coupled with low-cost fabri- 
cation and improved reliability of monolithic circuits, now 
makes on-card regulation quite attractive. 

design concepts 

A useful on-card regulator should include everything within 
one package — including the power-control element, or pass 
transistor. The author has previously advanced arguments 
against including the pass transistor in an integrated circuit 
regulator. 1 First, there are no standard multi-lead power 
packages. Second, integrated circuits necessarily have a 
lower maximum operating temperature because they con- 
tain low-level circuitry. This means that an IC regulator 
needs a more massive heat sink. Third, the gross variations 
in chip temperature due to dissipation in the pass transistors 
worsen load and line regulation. However, for a logic-card 
regulator, these arguments can be answered effectively. 



For one, if the series pass transistor is put on the chip, the 
integrated circuit need only have three terminals. Hence, an 
ordinary transistor power package can be used. The practi- 
cality of this approach depends on eliminating the adjust- 
ments usually required to set up the output voltage and limit- 
ing current for the particular application, as external adjust- 
ments require extra pins. A new solid-state reference, to be 
described later, has sufficiently-tight manufacturing toler- 
ances that output voltages do not always have to be individ- 
ually trimmed. Further, thermal overload protection can pro- 
tect an IC regulator for virtually any set of operating condi- 
tions, making current — limit adjustments unnecessary. 
Thermal protection limits the maximum junction temperature 
and protects the regulator regardless of input voltage, type 
of overload or degree of heat sinking. With an external pass 
transistor, there is no convenient way to sense junction tem- 
perature so it is much more difficult to provide thermal limit- 
ing. Thermal protection is, in itself, a very good reason for 
putting the pass transistor on the chip. 
When a regulator is protected by current limiting alone, it is 
necessary to limit the output current to a value substantially 
lower than is dictated by dissipation under normal operating 
conditions to prevent excessive heating when a fault oc- 
curs. Thermal limiting provides virtually absolute protection 
for any overload condition. Hence, the maximum output cur- 
rent under normal operating conditions can be increased. 
This tends to make up for the fact that an IC has a lower 
maximum junction temperature than discrete transistors. 
Additionally, the 5V regulator works with relatively low volt- 
age across the integrated circuit. Because of the low volt- 
age, the internal circuitry can be operated at comparatively 
high currents without causing excessive dissipation. Both 
the low voltage and the larger internal currents permit high- 
er junction temperatures. This can also reduce the heat 
sinking required — especially for commercial-temperature- 
range parts. 

Lastly, the variations in chip temperature caused by dissipa- 
tion in the pass transistor do not cause serious problems for 
a logic-card regulator. The tolerance in output voltage is 



113 



loose enough that it is relatively easy to design an internal 
reference that is much more stable than required, even for 
temperature variations as large as 1 50°C. 

circuit description 

The internal voltage reference for this logic-card regulator is 
probably the most significant departure from standard de- 
sign techniques. Temperature-compensated zener diodes 
are normally used for the reference. However, these have 
breakdown voltages between 7V and 9V which puts a lower 
limit on the input voltage to the regulator. For low voltage 
operation, a different kind of reference is needed. 
The reference in the LM109 does not use a zener diode. 
Instead, it is developed from the highly-predictable emitter- 
base voltage of the transistors. In its simplest form, the ref- 
erence developed is equal to the energy-band-gap voltage 
of the semiconductor material. For silicon, this is 1.205V, so 
the reference need not impose minimum input voltage limi- 
tations on the regulator. An added advantage of this refer- 
ence is that the output voltage is well determined in a pro- 
duction environment so that individual adjustment of the 
regulators is frequently unnecessary. 
A simplified version of this reference is shown in Figure 1. 
In this circuit, Q-\ is operated at a relatively high current 



Vref = V B E* r§ aV bi 




GROUND 



TL/H/6931-1 

Figure 1. The low voltage reference in one of its simpler 
forms. 

density. The current density of Q2 is about ten times lower, 
and the emitter-base voltage differential (AVbe) between 
the two devices appears across R3. If the transistors have 
high current gains, the voltage across R2 will also be pro- 
portional to AVbe- Q3 is a gain stage that will regulate the 
output at a voltage equal to its emitter base voltage plus the 
drop across R2. The emitter base voltage of Q3 has a nega- 
tive temperature coefficient while the AVbe component 



across R2 has a positive temperature coefficient. It will be 
shown that the output voltage will be temperature compen- 
sated when the sum of the two voltages is equal to the 
energy-band-gap voltage. 

Conditions for temperature compensation can be derived 
starting with the equation for the emitter-base voltage of a 
transistor which is 2 



VBE = V g „(,-^) + V BE „(I) 



nkT 
+ — iog e 



<T j 

— + — log e — , 
T q Ico 



(D 



AVbe 



log e 7- . 
J 2 



(2) 



where V g o is the extrapolated energy-band-gap voltage for 
the semiconductor material at absolute zero, q is the charge 
of an electron, n is a constant which depends on how the 
transistor is made (approximately 1.5 for double-diffused, 
NPN transistors), k is Boltzmann's constant, T is absolute 
temperature, Irj is collector current and Vbeo is the emitter- 
base voltage at Tq and Ico- 

The emitter-base voltage differential between two transis- 
tors operated at different current densities is given by 3 
kT 

q 

where J is current density. 

Referring to Equation (1 ), the last two terms are quite small 
and are made even smaller by making lc vary as absolute 
temperature. At any rate, they can be ignored for now be- 
cause they are of the same order as errors caused by non- 
theoretical behavior of the transistors that must be deter- 
mined empirically. 

If the reference is composed of Vbe plus a voltage propor- 
tional to AVbe. the output voltage is obtained by adding (1) 
in its simplified form to (2): 

V 90 ( 1 - i) +V BEo( ? 5:)+ ! ? loge £ (3) 



Vref 



To/ 



J 2 



(4) 



Differentiating with respect to temperature yields 

!V[- = _>k + Vbeo + k ,,,,,, Jl 
3T To To q J2 

For zero temperature drift, this quantity should equal zero, 
giving 

Jl 



kT 
V g o = Vbeo + — 'og e , ■ 
a q J 2 



(5) 



The first term on the right is the initial emitter-base voltage 
while the second is the component proportional to emitter- 
base voltage differential. Hence, if the sum of the two are 
equal to the energy-band-gap voltage of the semiconductor, 
the reference will be temperature-compensated. 



114 



A simplified schematic for a 5V regulator is given in Figure 2. 
The circuitry produces an output voltage that is approxi- 
mately four times the basic reference voltage. The emitter- 
base voltage of Q3, Q4, Q5 and Qs provide the negative- 
temperature-coefficient component of the output voltage. 
The voltage dropped across R 3 provides the positive-tem- 
perature-coefficient component. Qq is operated at a consid- 
erably higher current density than 07, producing a voltage 
drop across R4 that is proportional to the emitter-base volt- 
age differential of the two transistors. Assuming large cur- 
rent gain in the transistors, the voltage drop across R3 will 
be proportional to this differential, so a temperature-com- 
pensated-output voltage can be obtained. 




TL/H/6931-2 

Figure 2. Schematic showing essential details of the 5V 
regulator. 

In this circuit, Qg is the gain stage providing regulation. Its 
effective gain is increased by using a vertical PNP, Qg, as a 
buffer driving the active collector load represented by the 
current source. Qg drives a modified Darlington output stage 
(Q1 and Q2) which acts as the series pass element. With 
this circuit, the minimum input voltage is not limited by the 
voltage needed to supply the reference. Instead, it is deter- 
mined by the output voltage and the saturation voltage of 
the Darlington output stage. 

Figure 3 shows a complete schematic of the LM109, 5V 
regulator. The AVbe component of the output voltage is de- 
veloped across Rs by the collector current of Q7. The emit- 
ter-base voltage differential is produced by operating Q4 
and Q5 at high current densities while operating Qq and Q7 
at much lower current levels. The extra transistors improve 
tolerances by making the emitter-base voltage differential 
larger. R3 serves to compensate the transconductance 4 of 



Q5, so that the AVbe component is not affected by changes 
in the regular output voltage or the absolute value of com- 
ponents. 

The voltage gain for the regulating loop is provided by Q10, 
with Qg buffering its input and Q-n its output. The emitter 
base voltage of Qg and Q10 is added to that of Q12 and Q13 
and the drop across Rs to give a temperature-compensat- 
ed, 5V output. An emitter-base-junction capacitor, C-\, fre- 
quency compensates the circuit so that it is stable even 
without a bypass capacitor on the output. 
The active collector load for the error amplifier is Q17. It is a 
multiple-collector lateral PNP 4 . The output current is essen- 
tially equal to the collector current of Q2, with current being 
supplied to the zener diode controlling the thermal shut- 
down, D2, by an auxiliary collector. Q1 is a collector FET 4 
that, along with R1, insures starting of the regulator under 
worst-case conditions. 

The output current of the regulator is limited when the volt- 
age across R14 becomes large enough to turn on Q14. This 
insures that the output current cannot get high enough to 
cause the pass transistor to go into secondary breakdown 
or damage the aluminum conductors on the chip. Further, 
when the voltage across the pass transistor exceeds 7V, 
current through R15 and D3 reduces the limiting current, 




TL/H/6931 -3 

Figure 3. Detailed schematic of the regulator. 



115 



again to minimize the chance of secondary breakdown. The 
performance of this protection circuitry is illustrated in Fig- 
ure 4. 




10 15 20 25 30 35 



INPUT VOLTAGE (V) 

TL/H/6931-4 

Figure 4. Current-limiting characteristics. 

Even though the current is limited, excessive dissipation can 
cause the chip to overheat. In fact, the dominant failure 
mechanism of solid state regulators is excessive heating of 
the semiconductors, particularly the pass transistor. Ther- 
mal protection attacks the problem directly by putting a tem- 
perature regulator on the IC chip. Normally, this regulator is 
biased below its activation threshold; so it does not affect 
circuit operation. However, if the chip approaches its maxi- 
mum operating temperature, for any reason, the tempera- 
ture regulator turns on and reduces internal dissipation to 
prevent any further increase in chip temperature. 
The thermal protection circuitry develops its reference volt- 
age with a conventional zener diode, D2. Q16 is a buffer that 
feeds a voltage divider, delivering about 300 mV to the base 
of Q15 at 175°C. The emitter-base voltage, Q15, is the actual 
temperature sensor because, with a constant voltage ap- 
plied across the junction, the collector current rises rapidly 
with increasing temperature. 

Although some form of thermal protection can be incorpo- 
rated in a discrete regulator, IC's have a distinct advantage: 
the temperature sensing device detects increases in junc- 
tion temperature within milliseconds. Schemes that sense 
case or heat-sink temperature take several seconds, or 
longer. With the longer response times, the pass transistor 
usually blows out before thermal limiting comes into effect. 
Another protective feature of the regulator is the crowbar 
clamp on the output. If the output voltage tries to rise for 
some reason, D4 will break down and limit the voltage to a 
safe value. If this rise is caused by failure of the pass tran- 
sistor such that the current is not limited, the aluminum con- 
ductors on the chip will fuse, disconnecting the load. Al- 
though this destroys the regulator, it does protect the load 
from damage. The regulator is also designed so that it is not 
damaged in the event the unregulated input is shorted to 



ground when there is a large capacitor on the output. Fur- 
ther, if the input voltage tries to reverse, D1 will clamp this 
for currents up to 1 A. 

The internal frequency compensation of the regulator per- 
mits it to operate with or without a bypass capacitor on the 
output. However, an output capacitor does improve the tran- 
sient response and reduce the high frequency output imped- 
ance. A plot of the output impedance in Figure 5 shows that 
it remains low out to 1 kHz even without a capacitor. The 
ripple rejection also remains high out to 10 kHz, as shown in 
Figure 6. The irregularities in this curve around 1 00 Hz are 
caused by thermal feedback from the pass transistor to the 
reference circuitry. Although an output capacitor is not re- 
quired, it is necessary to bypass the input of the regulator 
with at least a 0.22 ju,F capacitor to prevent oscillations un- 
der all conditions. 



8 10 









= V IN 


= 10V = 








-T» = 


25° C- 
































































I, =20 mA 
















II L = 500mA 












| 







10" 3 

10 100 Ik 10k 100k 1M 

FREQUENCY (Hz) 

TL/H/6931-5 

Figure 5. Plot of output impedance as a function of fre- 
quency. 



100 















T, = -55°C 


l, = 2 


i°c\ 










T| = 150°C 
















. Ii =20 










V|N = 1 


OV 








AV |N = 


3V„ 









20 

10 100 Ik 10k 100k 1M 

FREQUENCY (Hz) 

TL/H/6931-6 

Figure 6. Ripple rejection of the regulator. 

Figure 7 is a photomicrograph of the regulator chip. It can 
be seen that the pass transistors, which must handle more 
than 1 A, occupy most of the chip area. The output transistor 
is actually broken into segments. Uniform current distribu- 
tion is insured by also breaking the current limit resistor into 



116 



segments and using them to equalize the currents. The over- 
all electrical performance of this IC is summarized in Table I. 




TL/H/6931-7 

Figure 7. Photomicrograph of the regulator shows that 
high current pass transistor (right) takes more 
area than control circuitry (left). 

TABLE I. Typical Characteristics of the 
Logic-Card Regulator: T A = 25°C 



Parameter 


Conditions 


Typ 


Output Voltage 




5.0V 


Output Current 




1.5A 


Output Resistance 




0.03H 


Line Regulation 


7.0V <; V| N <: 35V 


0.005 %/V 


Temperature Drift 


-55°C^T A ^ 125°C 


0.02%/°C 


Minimum Input Voltage 


'OUT = 1A 


6.5V 


Output Noise Voltage 


10Hz^f <i 100 kHz 


40jliV 


Thermal Resistance 
Junction to Case 


LM109H(TO-5) 
LM109K(TO-3) 


15°C/W 
3°C/W 



applications 

Because it was designed for virtually foolproof operation 
and because it has a singular purpose, the LM109 does not 
require a lot of application information, as do most other 
linear circuits. Only one precaution must be observed: it is 
necessary to bypass the unregulated supply with a 0.22 ju,F 
capacitor, as shown in Figure 8, to prevent oscillations that 



INPUT ■ 



C1. 
0.22 mF' 



LM109 



■ OUTPUT 



Figure 8. Fixed 5V regulator. 

can cause erratic operation. This, of course, is only neces- 
sary if the regulator is located on appreciable distance from 
the filter capacitors on the output of the dc supply. 
Although the LM109 is designed as a fixed 5V regulator, it is 
also possible to use it as an adjustable regulator for higher 



output voltages. One circuit for doing this is shown in 
Figure 9. 



OUTPUT 



ifciniiT 


. 1 






2 












I R1 


C1- 




3 


> 300 

> 1% 


0.22 mF~ 








< R2 
S 1% 



TL/H/6931-9 

Figure 9. Using the LM109 as an adjustable-output regu- 
lator. 

The regulated output voltage is impressed across R-), devel- 
oping a reference current. The quiescent current of the reg- 
ulator, coming out of the ground terminal, is added to this. 
These combined currents produce a voltage drop across R2 
which raises the output voltage. Hence, any voltage above 
5V can be obtained as long as the voltage across the inte- 
grated circuit is kept within ratings. 
The LM1 09 was designed so that its quiescent current is not 
greatly affected by variations in input voltage, load or tem- 
perature. However, it is not completely insensitive, as 
shown in Figures 10 and / /, so the changes do affect regu- 
lation somewhat. This tendency is minimized by making the 
reference current though R1 larger than the quiescent cur- 
rent. Even so, it is difficult to get the regulation tighter than a 
couple percent. 

6.0 



5.5 













1 1 
l L = 200 mA 






25° 






"Tl 


= -55°C 




v 




























T| 


= 15 


0°C 

















5.0 



5 10 15 20 25 

INPUT VOLTAGE (V) 

TL/H/6931-10 

Figure 10. Variation of quiescent current with input volt- 
age at various temperatures. 

6.0 















v 


N=1 


ov 




















* 


^ 


*H 






s " 


= 












i 


= 1 


A^ 













































5.0 



-75-50-25 25 50 75 100 125 150 

JUNCTION TEMPERATURE (°C) 

TL/H/6931-11 

Figure 11. Variation of quiescent current with tempera- 
ture for various load currents. 



117 



The LM109 can also be used as a current regulator as is 
shown in Figure 12. The regulated output voltage is im- 
pressed across R-i, which determines the output current. 
The quiescent current is added to the current through R-j, 
and this puts a lower limit of about 10 mA on the available 
output current. 



^ 



i^-r 



1 



TL/H/6931-12 



Figure 12. Current regulator. 



The increased failure resistance brought about by thermal 
overload protection make the LM109 attractive as the pass 
transistor in other regulator circuits. A precision regulator 
that employs the IC thusly is shown in Figure 13. An opera- 
tional amplifier compares the output voltage with the output 
voltage of a reference zener. The op amp controls the 
LM109 by driving the ground terminal through an FET. 



X>-v n „T=iov 




'Solid tantalum 



TL/H/6931-13 



Figure 13. High stability regulator. 

The load and line regulation of this circuit is better than 
0.001%. Noise, drift and long term stability are determined 



by the reference zener, D-i . Noise can be reduced by insert- 
ing 100 kft, 1 % resistors in series with both inputs of the op 
amp and bypassing the non-inverting input to ground. A 
1 00 pF capacitor should also be included between the out- 
put and the inverting input to prevent frequency instability. 
Temperature drift can be reduced by adjusting R4, which 
determines the zener current, for minimum drift. For best 
performance, remote sensing directly to the load terminals, 
as shown in the diagram, should be used. 

conclusions 

The LM109 performs a complete regulation function on a 
single silicon chip, requiring no external components. It 
makes use of some unique advantages of monolithic con- 
struction to achieve performance advantages that cannot 
be obtained in discrete-component circuits. Further, the low 
cost of the device suggests its use in applications where 
single-point regulation could not be justified previously. 
Thermal overload protection significantly improves the reli- 
ability of an IC regulator. It even protects the regulator for 
unforseen fault conditions that may occur in field operation. 
Although this can be accomplished easily in a monolithic 
regulator, it is usually not completely effective in a discrete 
or hybrid device. 

The internal reference developed for the LM109 also ad- 
vances the state of the art for regulators. Not only does it 
provide a low voltage, temperature-compensated reference 
for the first time, but also it can be expected to have better 
long term stability than conventional zeners. Noise is inher- 
ently much lower, and it can be manufactured to tighter tol- 
erances. 

reference 

1. R.J. Widlar, "Designing Positive Voltage Regulators," 
EEE, Vol. 17, No. 6, pp. 90-97, June 1969. 

2. J.S. Brugler, "Silicon Transistor Biasing for Linear Collec- 
tor Current Temperature Dependence, " IEEE Journal of 
Solid State Circuits, pp. 57-58, June, 1967. 

3. R.J. Widlar, "Some Circuit Design Techniques for Linear 
Integrated Circuits," IEEE Trans, on Circuit Theory, Vol. 
XII, pp. 586-590, December, 1965. 

4. R.J. Widlar, "Design of Monolithic Linear Circuits, " Hand- 
book of Semiconductor Electronics, Chapter X, pp. 
10.1-10.32, L.P. Hunter, ed., McGraw-Hill Inc., New 
York, 1970. 



118 



The Phase Locked Loop IC 
as a Communication 
System Building Block 



National Semiconductor 
Application Note 46 
Thomas B. Mills 




INTRODUCTION 

The phase locked loop has been found to be a useful ele- 
ment in many types of communication systems. It is used in 
two fundamentally different ways: (1) as a demodulator, 
where it is used to follow phase or frequency modulation 
and (2) to track a carrier or synchronizing signal which may 
vary in frequency with time. 

When operating as a demodulator, the phase locked loop 
may be thought of as a matched filter operating as a coher- 
ent detector. When used to track a carrier, it may be thought 
of as a narrow-band filter for removing noise from a signal. 
Recently, a phase locked loop has been built on a monolith- 
ic integrated circuit, incorporating the basic elements neces- 
sary for operation: a double balanced phase detector and a 
highly linear voltage controlled oscillator, the frequency of 
which can be varied with either a resistor or capacitor. 

BASIC PHASE LOCK LOOP OPERATION 

Figure 1 shows the basic blocks of a phase locked loop. 
The input signal ej is a sinusoid of arbitrary frequency, while 
the VCO output signal, e , is a sinsuoid of the same fre- 
quency as the input but of arbitrary phase. If 

ei = V§E|8in[« t + «i(t)] (1) 

e = ^Eo cos [o) t + 2 (t)] (2) 

the output of the multiplier (phase detector) is 
ed = ej • e 

= 2EjE sin [w t + 6^(\)\ • cos [w t + 6 2 (t)] 

= EjE sin [0i(t) - 2 (t)] + E|E sin [2 a> t + fl^t) + 

2 (t)] (3) 

the low pass filter of the loop removes the ac components 

of the multiplier output; the dc term is seen to be a function 

of the phase angle between the VCO and the input signal. 



INPUT- 



PHASE 




e " fc 


FILTER 
FfS) 


«f 


DETECTOR 






-t 








L 


VOLTAGE CONTROLLED 
OSCILLATOR 





TL/H/7363-1 

FIGURE 1. Basic Phase Locked Loop 

The output of the VCO is related to its input control voltage 
by 

2 (t) = K e f (4) 

for ef = 0, Let 2 = ad, then 

e 2 (t) = S e f (t) dt (5) 



It can be seen that the action of the VCO is that of an 
integrator in the feedback loop when the phase locked loop 
is considered in servo theory. 

A better understanding of the operation of the loop may be 
obtained by considering that initially, the loop is not in lock, 
but that the frequency of the input signal ej and VCO e are 
very close in frequency. Under these conditions &a will be a 
beat note, the frequency of which is equal to the frequency 
difference of e and 6j. This signal is also applied to the 
VCO input, since it is low enough to pass through the filter. 
The instantaneous frequency of the VCO is therefore 
changing and at some point in time, if the VCO frequency 
equals the input frequency, lock will result. At this instant, ef 
will assume a level sufficient to hold the VCO frequency in 
lock with the input frequency. If the tuning of the VCO is 
changed (such as by varying the value of the tuning capaci- 
tor) the frequency output of the VCO will attempt to change; 
however, this will result in an instantaneous change in 
phase angle between ej and e , resulting in a change in the 
dc level of e^ which will act to maintain frequency lock: no 
average frequency change will result. 
Similarly, if ej changes frequency, an instantaneous change 
will result in a phase change between e, and e and hence a 
dc level change in e^. This level shift will change the fre- 
quency of the VCO to maintain lock. 
The amount of phase error resulting from a given frequency 
shift can be found by knowing the "dc" loop gain of the 
system. Considering the phase detector to have a transfer 
function: 

Ed-Kp^ -B 2 ) 
and the voltage controlled oscillator to have a transfer func- 
tion: 

e 2 = K e f (6) 

or taking the Laplace transform 

K e f 
s 

the phase of the VCO output will be proportional to the inte 
gral of the control voltage. 
Combining these equations: 



2 (s) = 



(7) 



2 (8) _ K K d F(s) 
^(s) s + K K D F(s) 

01 (s) - 2 (s) s 



01 (s) 



s + K K D F(s) 



(8) 



(9) 



119 



Application of the final value theorem of Laplace transforms 
yields 



t i m oo «i(s)-Ms) = s , i m 



S2 1(S ) 



s + K K D F(s) 



(10) 



With a step change in phase of the input A0-|, the Laplace 
transform of the input is 



01 (s) 



A01 



which gives e (s) = 0i(s) - 02(s) 



lim 



,»e(t) 



lim 



sA0 1 



= 



(11) 



o s + K K D F(s) 

the loop will eventually track out any change of input phase, 
and there will be no phase error in the steady state solution. 
If the input is a step in frequency, of magnitude Aw, the 
change in input phase will be a ramp: 

01 (s) = Aco/s2 
substitution of this value 0, into (10) results in 



lim 9 , )= lim 



Ao 



Act) 



(12) 



°s + K K D F(s) K K D F(o) 

this result shows the resulting phase error is dependent on 
the magnitude of the frequency step and the "dc" loop gain 
K Kd, which is also called the velocity error coefficient K v . It 
should be noted that the dimensions of K Kq are 1/sec. 
This can also be seen by considering Kq = volts/radian, 
while K = radians/sec/volt. The product is 

volts 



radian 



radians/sec 
volt 



1 
sec 



this can be thought of as the "dc" loop gain. (Note that 
additional dc gain between the phase detector and the volt- 
age controlled oscillator will increase the loop gain and 
hence reduce the steady state phase error resulting from a 
change in frequency of the input). 

THE LOOP FILTER 

In working with phase locked loops, it is necessary to con- 
sider not only the "dc" performance described above, but 
the "ac" or transient performance which is governed by the 
components of the loop filter placed between the phase 
detector and the voltage controlled oscillator. In fact, it is 
this loop filter that makes the phase locked loop so power- 
ful: only a resistor and capacitor are all that is needed to 
produce an arbitrarily narrow bandwidth at any selected 
center frequency. 

The simplest filter is a single capacitor, Figure 2, and is used 
for wide bandwith applications, such as where wideband 



data modulation must be followed. The transfer function of 
the filter is simply: 



6f 



1 



ed 1 + sRi Ci 
substitution into (8) results in 

«2(s) K K D /ri 



01 (s) s2 + s/t 1 + «oK d /ti 
ti = Ri Ci 



(13) 



(14) 



In terms of servo theory, the damping factor and natural 
frequencies are 



_ [K K D ]l/2 
2l(RiCiK K D )J 



(15) 
(16) 



PHASE 
DETECTOR 



E 



R1 

■AAAr 



T-, = R1C1 



VOLTAGE CONTROLLED 
OSCILLATOR 



^ 



BODE PLOT 



6 dB/OCT 




-12 dB/OCT 



TL/H/7363-3 

FIGURE 2. Phase Locked Loop with Simple Filter 

From this it can be seen that large time constants for Ri Ci 
or high loop gain will reduce the damping factor and hence 
decrease stability. Therefore, if a narrow bandwidth is de- 
sired, the damping factor will become very small and insta- 
bility will result. It is not possible to adjust bandwidth, loop 
gain, and damping independently with this simple filter. 



120 



With the addition of a damping resistor R2 as shown in Fig- 
ure 3, it is possible to choose bandwidth, damping factor 
and loop gain independently; the transfer function of this 
filter is 



6d 



1 + ST 2 



1 + ST-\ 

the loop transfer function becomes: 
g 2 (s) _ 

Z (S) 

K K d (st 2 + 1)(t 1 + r 2 ) 

S2 + S(1 + KoK d T 2 )/T<l + KoKp/Ti 

the loop natural frequency is 



while the damping factor becomes 
1 



4[; 



Lt! K K D 

s <anTz 
2 



ictor becomes 
] V2 [l +r 2 K K D ] 



(17) 



(18) 



(19) 



(20) 



(21) 



PHASE 
DETECTOR 



E 



R1 

■AMr 



VOLTAGE CONTROLLED 
OSCILLATOR 



T 



t, = R1C1 



t 2 = R2C1 



TL/H/7363-4 




-12 XdB/OCf^ 
dB/0CTi\ \ 



TL/H/7363-5 

FIGURE 3. Phase Locked Loop with 
Damping Resistor Added 

In practice, for a fixed loop gain K Kd, the natural frequency 
of the loop may be chosen and will be dependent mainly on 
r-i, since 7- 2 < t-\ in most cases. Then, according to (21), 
damping may be determined by r 2 and for all practical pur- 
poses, will be an independent adjustment. These equations 
are plotted in Figures 4 and 5 and may be used for design 
purposes. 



10* 



10 3 



10 1 





































/RAD\ 

Bad 
ASEcV 






























^ Jf " 






























■ <l 


i 5? 






































































, 


' >if * 




















1 in 3 * 




















































o 2 - 

































10- 4 10" 3 10- 2 10° 1 10 

ti + T2 (sec) 

TL/H/7363-I 

FIGURE 4. Filter Time Constant vs Natural Frequency 
10* 



10 3 



10 2 



















"DAMPING """■- 








' RATIO 






















\LIIIH 


























37 




s 




















^■.707 























































10- 4 tir 3 10- 3 

T2 



10- 1 



FIGURE 5. Damping Time Constant vs 
Natural Frequency 

DESIGN CONSIDERATIONS 

Considering the above discussion, there are really two pri- 
mary considerations in designing a phase locked loop. The 
use to which the loop is to be put will affect the design 
criterion of the loop components. The two primary factors to 
consider are: 

1 . Loop gain. As pointed out previously, this affects the 
phase error between the input signal and the voltage con- 
trolled oscillator for a given frequency shift of the input 
signal. It also determines the "hold in range" of the loop 
providing no components of the loop go into limiting or 
saturation. This is because the loop will remain in lock as 
long as the phase difference between the input and the 
VCO is less than ±90°. The higher the loop gain, the 
further the input can change in frequency before the 90° 
phase error is reached. The hold in range is 

Aw H = ±K K D (22) 

(providing saturation or limiting does not occur). 

2. Natural Frequency. The bandwidth of the loop is deter- 
mined by the filter components R-|, R 2 and C1, and the 
loop gain. Since the loop gain is normally selected by the 
criterion in 1. above, the filter components are used to 
select the bandwidth. The selection of loop bandwidth 
may be governed by several things: noise bandwidth, 
modulation rates if the loop is to be used as an FM de- 



121 



modulator, pull-in time and hold-in range. There are two 
conflicting requirements that will have an affect on loop 
bandwidth: 

(a) Loop bandwidth must be as narrow as possible to 
minimize output phase jitter due to external noise. 

(b) The loop bandwidth should be made as large as pos- 
sible to minimize transient error due to signal modula- 
tion, output jitter due to internal oscillator (VCO) noise, 
and to obtain best tracking and acquisition properties. 

These two principles are in direct opposition and, depending 
on what it is that the loop is to accomplish, an optimum 
solution will lie somewhere between the two extremes. 
If the phase locked loop is to be used to demodulate fre- 
quency modulation, the design should proceed with the cri- 
terion of b above. It is necessary to provide sufficient loop 
bandwidth to accommodate the expected modulation. It 
must be remembered that at all times, the loop must remain 
in lock, (peak phase error less than 90°), even under ex- 
tremes of modulation, such as peaks or step changes in 
frequency. 

For the case of sinusoidal frequency modulation, the peak 
phase error as a function of frequency deviation and damp- 
ing factor is shown in Figure 6. 



1.6 

1.4 

1.2 

1.0 

0.8 

0.6 

0.4 

0.2 


0.1 0.2 0.3 0.50.71.0 









1 1 1 II 










T 










° V 1 








































/ 






















I 
















I 


= 0.5 JJI 










































j; =n 7fi7 
























































i!rr='i.Q\ 
















3-fflll s ^ 
















44-t- 2.0 


























Trim 6,0 










Mini 1 









2 3 5 7 10 



0.7 

0.5 

"i 

< 0.3 

i -' 
-0.1 

-0.3 





| 1 












~y»-{ = 0.3 












Oi-t = 0-5 










"VtVf =0j707 




































r i 




t- 


5.0 






J £ = 2.b\^ 










£ = 1.0 









































3 4 5 

6>„t 



TL/H/7363-9 



FIGURE 7. Transient Phase Error e (t) Due to a 

Step In Frequency Aw. (Steady-State Velocity 

Error, Aw/K v , Neglected) 



1.4 
1.2 

3 

5 0.8 

< 

0.6 

0.4 

0.2 







U = '0.3J^. 














L/{= os 










£ =0.707, 
















































= I.Oj 
































^=2.0 
























































= S.( 





































1 2 3 4 5 

0).t 



TL/H/7363-10 



FIGURE 8. Transient Phase Error e (t) Due to a Ramp in 

Frequency Aw. (Steady-State Acceleration Error, 
Aw/w n 2, Included. Velocity Error, Awt/K v , Neglected) 



FIGURE 6. Steady-State Peak Phase Error Due to 
Sinusoidal FM (High-Gain, Second-Order Loop) 

It can be seen that the maximum phase error occurs when 
the modulating frequency w m equals the loop natural fre- 
quency w n ; if the loop has been designed with a damping 
factor of 0.707, the peak phase error (in radians) will be 0.71 
Aw/w n (Aw = frequency deviation). From this plot, it is 
possible to choose w n for a given deviation and modulation 
frequency. 

If the loop is to demodulate frequency shift keying (FSK), it 
must follow step changes in frequency. The filter compo- 
nents must then be chosen in accordance with the transient 
phase error shown in Figure 7. It must be remembered that 
the loop filter must be wide enough so the loop will not lose 
lock when a step change in frequency occurs: the greater 
the frequency step, the wider the loop filter must be to main- 
tain lock. 

There is some frequency-step limit below which the loop 
does not skip cycles, but remains in lock, called the "pull- 
out frequency" w po . Viterbi has analyzed this and his results 
are shown in Figure 8, which plots normalized pull out fre- 
quency for various damping factors for high gain second 
order loops. Peak phase errors for other types of input sig- 
nals are shown in Figures 8 and 9. 



0.9 



0.3 
0.1 
-0.1 
-0.3 
-0.5 







1 












































































































1 












|L{'= 2.0 — 




























?l 








X = 5.05 

1 




="J = U.7D 


) 




="{-0.51 






1 




L i- 


-V.i 







2 3 4 5 

OJ.t 



TL/H/7363-11 



FIGURE 9. Phase Error e (t) Due to a Step in Phase A0 

In designing loops to track a carrier or synchronizing signal, 
it is desirable to make the loop bandwidth narrow so that 
phase error due to external noise will be small. However, it 
is necessary to make the loop bandwidth wide enough so 
that any frequency jitter on the input signal will be followed. 



122 



NOISE PERFORMANCE 

Since one of the main uses of phase locked loops is to 
demodulate or track signals in noise, it is helpful to look at 
how noise affects the operation of the phase locked loop. 
The phase locked loop, as mentioned earlier, may be 
thought of as a filter with a fixed, adjustable bandwidth. We 
have seen how to calculate the loop natural frequency w n 
(15), (19), and the damping factor £ (16), (20). Without going 
through a derivation, the loop noise bandwidth B|_ may be 
shown to be 



Bi = 



H(jo>)|2 df 



"?[ 



£ + 



Hz 



(23) 



for a high gain, second order loop. This equation is plotted 
in Figure 10. It should be noted that the dimensions of noise 
bandwidth are cycles per second while the dimensions of 
co n are radians per second. 









b l 




I 








to „ 






















I 




























V, 





























0.5 



0.5 1.0 1.5 2.0 2.5 3.0 3.5 

DAMPING FACTOR -{ 

TL/H/7363-12 

FIGURE 10. Loop-Noise Bandwidth 
(For High-Gain, Second-Order Loop) 

Noise threshold is a difficult thing to analyze in a phase 
locked loop, since we are talking about a statistical quantity. 
Noise will show up in the input signal as both amplitude and 
phase modulation. It can be shown that near optimum per- 
formance of a phase locked loop can be obtained if a limiter 
is used ahead of the phase detector, or if the phase detec- 
tor is allowed to operate in limiting. With the use of a limiter, 
amplitude modulation of the input signal by noise is re- 
moved, and the noise appears as phase modulation. As the 
input signal to noise ratio decreases, the phase jitter of the 
input signal due to noise increases, and the probability of 
losing lock due to instantaneous phase excersions will in- 
crease. In practice it is nearly impossible to acquire lock if 
the signal to noise ratio in the loop (SNR)l = dB. In gen- 
eral, (SNR)l of +6 dB is needed for acquisition. If modula- 
tion or transient phase error is present, a higher signal to 
noise ratio is needed to acquire and hold lock. 
A computer simulation performed by Sanneman and Row- 
botham has shown the probability of skipping cycles for vari- 
ous loop signal to noise ratios for high gain, second order 
loops. Their data is shown in Figure 1 1. 



u 

z 500 


































° 200 

P 100 


































1 50 




































a 20 


































I 10 


































z 5 






















































a 



















0.5 1.0 1.5 2.0 

LOOP SIGNAL-TO-NOISE RATIO 

TL/H/7363-13 

FIGURE 11. Unlock Behavior of High-Gain, 
Second-Order Loop, £ = 0.707 

When designing the loop filter components, enough band- 
width in the loop must be allowed for instantaneous phase 
change due to input noise. In the previous section, the filter 
was selected on the basis that the peak error due to modu- 
lation would be less than 90° (so the loop would not loose 
lock). However, if noise is present, the peak phase error will 
increase due to the noise. So if the loop is not to lose lock 
on these noise peaks the peak allowable error due to modu- 
lation must be reduced to something less, on the order of 
40° to 50°. 

LOCKING 

Initially, a loop is unlocked and the VCO is running at some 

frequency. If a signal is applied to the input, locking may or 

may not occur depending on several things. 

If the signal is within the bandwidth of the loop filter, locking 

will occur without a beat note being generated or any cycles 

being skipped. This frequency is given by 

K Kq T2 _ _ . 
Aw L = ~ 2 £ o> n (24) 

If the frequency of the input signal is further away from the 
VCO frequency, locking may still occur, with a beat note 
being generated. The greatest frequency that can be pulled 
in is called the "pull in frequency" and is found from the 
approximation 



Atop 



= V2(2£ Wn K K D -G)n) (25) 

for moderate and high gain loops 



which works well 

(o) n /K K D < 0.4). 

An approximate expression for pull in time (the time required 

to achieve lock from some frequency offset Aa>) is given by: 

Tp ~TT~3 

2£o>n 

A MONOLITHIC PHASE LOCKED LOOP 

A complete phase locked loop has been built on a monolith- 
ic integrated circuit. It features a very linear voltage con- 
trolled oscillator and a double balanced phase detector. 



123 






A simplified schematic of this voltage controlled oscillator is 
shown in Figure 12. Q2 is a voltage controlled current 
source whose collector current is a linear function of the 
control voltage ef. Initially Q5 is OFF and the collector cur- 
rent of Q2 passes through D2 and changes C in a linear 
fashion. The voltage across C is therefore a ramp, and con- 
tinues to increase until Q7 is turned ON; this turns OFF Qs, 
causing Qg and 0-n to turn ON. This in turn turns ON Q5. 
With Q5 ON, the anode of D1 is clamped close to - V<x and 
D2 stops conducting, since its cathode is more positive than 
its anode. 



All of the current supplied by Q2 is diverted through D-| and 
Q3, which sets up an equal current in Q4. This current Is 
supplied by the charged capacitor C (which now discharges 
linearly), causing the voltage across it to decrease. This 
continues until a lower trip point is reached and Q7 turns 
OFF and the cycle repeats. Due to the matching of 63 and 
Q4, the charge current of C is equal to the discharge current 
and therefore the duty cycle is very nearly 50%. Figure 13 
shows the wave forms at (1) and (2). 
Figure 14 shows the double balanced phase detector and 
amplifier used in the microcircuit. Transistors Q1 through Q4 
are switched with the output of the VCO, while the input 



Q SQUARE WAVE 




TL/H/7363-14 



FIGURE 12. Simplified Voltage Controlled Oscillator 



CAPACITOR 
CHARGING 



PIN 1 
VOLTAGE 



+1.1V 
OV 




PIN 2 
VOLTAGE 




-0.6V 



CAPACITOR 
DISCHARGING 




TL/H/7363-15 



FIGURE 13. VCO Waveforms 



124 



signal is applied to the bases of Q5 and Q6- The output 
current in resistors R3 and R4 is then proportional to the 
difference in phase between the VCO output and the input; 
the ac component of this current will be at twice the fre- 
quency of the VCO due to the full wave switching action 
transistors Q1 through Q 4 . The waveforms of Figure 15 illus- 
trate how the phase detector works. Diodes D1 and D2 
serve to limit the peak to peak amplitude of the collector 
voltage. The output of the phase detector is further ampli- 
fied by Q 10 and Qn, and is taken as a voltage at pin 7. 



Rs serves as the resistive portion of the loop filter, and addi- 
tional resistance and capacitance may be added here to fix 
the loop bandwidth. For use as an FM demodulator, the 
voltage at pin 7 will be the demodulated output; since the dc 
level here is fairly high, a reference voltage has been provid- 
ed so that an operational amplifier with differential input can 
be used for additional gain and level shifting. 

The complete microcircuit, called the LM565, is shown in 
Figure 16. 



> 
■ 



'o \4 ,h -t 




20- 




l~T~v Q u- 



16 J- 

r 



'R2 



-03 



I 



3=3 



-Vcc 



FIGURE 14. Phase Detector and Amplifier 



TL/H/7363-16 



VCO 
OUTPUT 



<t» = 90" 



4> = 0° 



<J> = 180° 



I 




ERROR VOLTAGE 
ZERO 



ERROR VOLTAGE 
POSITIVE 



ERROR VOLTAGE 
NEGATIVE 



TL/H/7363-17 

FIGURE 15. Phase Detector Waveforms, Showing Limit Cases for Phase Shift between Input and VCO Signals 



125 



to 



I— VW 



> e 

-o— 



SO- 






-o- 



o cc < 

S£5 



-o- 






urm 



\y 



■AWr 



^ 



■Wr 



v/" 



-VW- 



-WSr- 



25 
-VSAr- 






S3 



— nr 



r 




-VS/Nr 






3k. 



IMWr4 



l 4 it 



MVSAr-O 



= S 



\s/- 







= s 



<>-^WV • 



IH^VW f 



YJ 



■A/S/Nr 




■VW- 



■VW- 



m 



-wv- 




■^WSr 



T^i 



H 



tj 



XI 




y^\ 






8 

> 

-0- 



126 



USING THE LM565 

Some of the important operating characteristics of the 
LM565 are shown in the table below (Vqc = ±6V, Ta = 
25°C). 



Phase Detector 




Input Impedance 


5kft 


Input Level for Limiting 


10 mV 


Output Resistance 


3.6 kfl 


Output Common Mode Voltage 


4.5V 


Offset Voltage (Between pins 6 and 7) 


100mV 


Sensitivity Kp 


.68V/rad 


Voltage Controlled Oscillator 




Stability 




Temperature 


200 ppm/°C 


Supply Voltage 


200 ppm/% 


Square Wave Output Pin 4 


5.4 V pp 


Triangle Wave Output Pin 9 


2.4 V pp 


Maximum Operating Frequency 


500 kHz 


Sensitivity K 4.1 f rad/sec/V 


(f : osc, freq. in Hz) 


Closed Loop Performance 




Loop Gain K Kd 


2.8 f /sec 


Demod. Output, ±10% Deviation 


300 mV 


(A 0.001 fxF capacitor is needed between 


pins 7 and 


8 to stop parasitic oscillations). 





To best illustrate how the LM565 is used, several applica- 
tions are covered in detail, and should provide insight into 
the selection of external components for use with the 
LM565. 

IRIG CHANNEL DEMODULATOR 

In the field of missile telemetry, it is necessary to send many 
channels of relatively narrow band data via a radio link. It 
has been found convenient to frequency modulate this infor- 



mation on a set of subcarriers with center frequencies in the 
range of 400 Hz to 200 kHz. Standardization of these fre- 
quencies was undertaken by the Inter-Range Instrumenta- 
tion Group (IRIG) and has resulted in several sets of subcar- 
rier channels, some based on deviations that are a fixed 
percentage of center frequency and other sets that have a 
constant deviation regardless of center frequency. IRIG 
channel 13 has been selected as an example to demon- 
strate the usefulness of the LM565 as an FM demodulator. 



IRIG Channel 
Center Frequency 
Max Deviation 
Frequency Response 
Deviation Ratio 



13 

14.5 kHz 

± 7.5% 

220 Hz 

5 



Since with a deviation of +10%, the LM565 will produce 
approximately 300 mV peak to peak output, with a deviation 
of 7.5% we can expect an output of 225 mV. It is desirable 
to amplify and level shift this signal to ground so that plus 
and minus output votages can be obtained for frequency 
shifts above and below center frequency. 
An LM107 can be used to provide the necessary additional 
gain and the level shift. In Figure 17, R4 is used to set the 
output at zero volts with no input signal. The frequency of 
the VCO can be adjusted with R3 to provide zero output 
voltage when an input signal is present. 
The design of the filter network proceeds as follows: 
It is necessary to choose o> n such that the peak phase error 
in the loop is less than 90° for all conditions of modulation. 
Allowing for noise modulation at low levels of signal to 
noise, a desirable peak phase error might be 1 radian or 57 
degrees, leaving a 33 degree margin for noise. Assuming 
sinusoidal modulation, Figure 6 can be used to estimate the 
peak normalized phase error. It will be necessary to make 
several sample calculations, since the normalized phase er- 
ror is a function of w n . 




•— O 



FIGURE 17. IRIG Channel 13 Demodulator 



TL/H/7363-19 



127 



Selecting a worst case of a> n /ft) m = 1, co n = 2tt X 220 Hz; 
selecting a damping factor of 0.707, 



= 0.702 



Act>/ct) n 



Aw 2 7T X 1088 Hz 

$ e = 0.702 — = 0.702 — = 3.45 radians 

w n 2 7T X 220 Hz 

this is unacceptable, since it would throw the loop out of 
lock, so it is necessary to try a higher value of o n . Let co n = 
27rx 500 Hz, then oi m /cii n = 0.44, and 

Aw 2 it X 1088 

e = 0.44 — = 0.44 X = 0.95 radians 

a> n 2 7T X 500 

this should be a good choice, since it is close to 1 radian. 
Operating at 1 4.5 kHz, the LM565 has a loop gain K Kd of 

2.28 X 14.5 X 103 = 33 X 103sec 

the value of the loop filter capacitor, Ci , can be found from 
Figure 4: 

t-i + t 2 = 3.5 X 10~3 sec 

from Figure 5, the value of t 2 can be found (for a damping 
factor of 0.707) 

t 2 = 4.4 x 10~4 sec 

r-i = (35 - 4.4) x 10-4 sec = 31.4 x 10- 4 sec 
r 1 31.4X10-4 sec 

Ci = r = 5^ " 1fAp 

4.4 x 10-4 sec 

R 2 = — .,„ c r. = 440H 

* 1 X 10-6 jaF 

Looking at Figure 10, the noise bandwidth B|_ can be esti- 
mated to be 

Bl = 0.6 o n = 0.6 X 3150 rad/sec 
= 1890 Hz 

the complete circuit is shown in Figure 17. Measured per- 
formance of the circuit is summarized below with a fully 
modulated signal as described above and an input level of 
40 mVrms: 

f 3 dB 200 

£ 0.8 

Output Level 770 mVrms 

Distortion 0.4% 

Signal to Noise at verge of loss of lock 

(bandwidth of noise = 1 00 kHz) - 8.4 dB 

It will be noted that the loop is capable of demodulating 
signals lower in level than the noise; this is not in disagree- 
ment with earlier statements that loss of lock occurs at sig- 
nal to noise ratios of approximately + 6 dB because of the 
bandwidths involved. The above number of -8.4 dB signal 
to noise for threshold was obtained with a noise spectrum 



1 00 kHz wide. The noise power in the loop will be reduced 
by the ratio of loop noise bandwidth to input noise band- 
width 



Bloqp _ 1890 Hz 
BiNPUT 100 kHz 



= 0.02 or -17 dB 



the equivalent signal to noise in the loop is -8.4 dB +17 
dB = + 8.6 dB which is close to the above-mentioned limit 
of +6 dB. It should also be noted that loss of lock was 
noted with full modulation of the signal which will degrade 
threshold somewhat (although the measurement is more re- 
alistic). 



100K 



100 
10 

1 



^ 






- 


oil = 250 -*J\ 

o) 2 = 2500 ~l \ 
1 III* 


. o) — * 

X i 



10 



100 



IK 



10K 100K 

TL/H/7363-20 

FIGURE 18. Bode Plot for Circuit of Figure 17 

FSK DEMODULATOR 

Frequency shift keying (FSK) is widely used for the trans- 
mission of Teletype information, both in the computer pe- 
ripheral and communications field. Standards have evolved 
over the years, and the commonly used frequencies are as 
follows: 

mark 2125 

space 2975 

mark 1070 

space 1270 

mark 2025 

space 2225 

(a) is commonly used as subcarrier tones for radio Teletype, 
while b) and c) are used as carriers for data transmission 
over telephone and land lines. 

As a design example, a demodulator for the 2025 Hz and 
2225 Hz mark and space frequencies will be discussed. 
Since this is an FM system employing square wave modula- 
tion, the natural frequency of the loop must be chosen again 
so that peak phase errors do not exceed 90° under all con- 
ditions. Figure 7 shows peak phase error for a step in fre- 
quency; if a damping factor of 0.707 is selected, the peak 
phase error is 



a) 



b) 



c) 



Hz 
Hz 
Hz 
Hz 
Hz 
Hz 



0« 



Ato/o) n 



0.45 



128 




> 



4 wv 4 




TL/H/7363-21 



FIGURE 19. FSK Demodulator (2025-2225 cps) 

♦24V 




TL/H/7363-22 



FIGURE 20. FSK Demodulator with DC Restoration 



129 





r 






.- -- 1 






INPUT FROM _ 




<p DETECTOR 


1 


FILTER 




TAPE RECORDER °" 






1 








i i 


LM565 


| 














VCO 












2400 Hz 


* 1 






L_ 


IT 




J 








+90 










\ 














<£ DETECTOR 
LM1596 




FILTER 




^ VIDEO 


1ATION 












™ INFORN 


























w HORIZC 


NTAL 


















—^ SYNC 



TL/H/7363-23 



FIGURE 21. Block Diagram of Weather Satellite Demodulator 



0.45- 



. Aw 

0>n 



Aw 
a> n = 0.45 — 

in our case, Aw = 2ir X 200 Hz = 1250, if 6 e = 1 radian, 

„ 1250rad/sec r „„ .. 

w n = 0-45 = 500 rad/sec 

1 radian 

f n = 80 Hz 
The final circuit is shown in Figure 19. The values of the 
loop filter components (C-| = 2.2 juF and R1 = 700O) were 
changed to accommodate a keying rate of 300 baud 
(150 Hz), since the values calculated above caused too 
much roll off of a square wave modulation signal of 1 50 Hz. 
The two 10k resistors and 0.02 /uF capacitors at the input to 
the LM1 1 1 comparator provide further filtering of the carrier, 
and hence smoother operation of the circuit. 
A problem encountered with this simple demodulator is that 
of dc drift. The frequency must be adjusted to provide zero 
volts to the input of the comparator so that with modulation, 
switching occurs. Since the deviation of the signal is small 
(approximately 10%), the peak to peak demodulated output 
is only 150 mV. It should be apparent that any drift in fre- 
quency of the VCO will cause a dc change and hence may 
lock the comparator in one state or the other. A circuit to 
overcome this problem is shown in Figure 20. While using 
the same basic demodulator configuration, an LM111 is 
used as an accurate peak detector to provide a dc bias for 
one input to the comparator. When a "space" frequency is 
transmitted, and the output at pin 7 of the LM565 goes neg- 



ative and switching occurs, the detected and filtered voltage 
of pin 3 to the comparator will not follow the change. This is 
a form of "dc restorer" circuit: it will track changes in drift, 
making the comparator self compensating for changes in 
frequency, etc. 

WEATHER SATELLITE PICTURE DEMODULATOR 

As a last example of how a phase locked loop can be used 
in communications systems, a weather satellite picture de- 
modulator is shown. Weather satellites of the Nimbus, 
ESSA, and ITOS series continually photograph the earth 
from orbits of 100 to 800 miles. The pictures are stored 
immediately after exposure in an electrostatic storage vidi- 
con, and read out during a succeeding 200 second period. 
The video information is AM modulated on a 2.4 kHz sub- 
carrier which is frequency modulated on a 137.5 MHz RF 
carrier. Upon reception, the output from the receiver FM 
detector will be the 2.4 kHz tone containing AM video infor- 
mation. It is common practice to record the tone on an audio 
quality tape recorder for subsequent demodulation and dis- 
play. The 2.4 kHz subcarrier frequency may be divided by 
600 to obtain the horizontal sync frequency of 4 Hz. 
Due to flutter in the tape recorder, noise during reception, 
etc., it is desirable to reproduce the 2.4 kHz subcarrier with 
a phase locked loop, which will track any flutter and instabili- 
ty in the recorder, and effectively filter out noise, in addition 
to providing a signal large enough for the digital frequency 
divider. In addition, an in phase component of the VCO sig- 
nal may be used to drive a synchronous demodulator to 
detect the video information. A block diagram of the system 
is shown in Figure 21, and a complete schematic in Figure 
22. 



130 



> 
z 

I 



S£ 



^\-», 




?0— H>- 




MWr 



t 5 ~T 



§ 



♦AA/V-i 



O 




<MVVV • | |i 

HH 



HH 1 " Hf* 



131 



The design of the loop parameters was based on the follow- 
ing objectives 

f n = 10 Hz, co n = 75 rad/sec 

B|_ = 40 Hz (from Figure 10) 
the complete loop filter, calculated from Figures 4 and 5, is 
shown in Figure 22. When the loop is in lock and the free 
running frequency of the VCO is 2.4 kHz, the VCO square 
wave at pin 4 of the 565 will be in quadrature (90°) with the 
input signal; however, the zero crossings of the triangle 
wave across the timing capacitor will be in phase, and if 
their signal is applied to a double balanced demodulator, 
such as an LM1596, switching will occur in the demodulator 
in phase with the 2.4 kHz subcarrier. The double balanced 
demodulator will produce an output proportional to the am- 
plitude of the subcarrier applied to its signal input. An emit- 
ter follower, Q-| , is used to buffer the triangle wave across 
the timing capacitor so excessive loading does not occur. 
The demodulated video signal from the LM1596 is taken 
across a 25k potentiometer and filtered to a bandwidth of 
1 .4 kHz, the bandwidth of the transmitted video. Depending 
on the type of display to be used (oscilloscope, slow scan 
TV monitor, facsimile reproducer), it may be necessary to 
further buffer or amplify the signal obtained. If desired, an- 
other load resistor may be used between pin 6 and VCO to 
obtain a differential output; an operational amp could then 
be used to provide more gain, level shift, etc. 



A vertical sweep circuit is shown using an LM308 low input 
current op amp as a Miller rundown circuit. The values are 
chosen to produce an output voltage ramp of -4.5V/220 
sec, although this may be adjusted by means of the 22 meg. 
charging resistor. If an oscilloscope is used as a readout, 
the horizontal sync can be supplied to the trigger input with 
the sweep set to provide a total sweep time of something 
less than 250 ms. A camera is used to photograph the 200 
second picture. 

SUMMARY AND CONCLUSIONS 

A brief review of phase lock techniques has been presented 
and several design tools have been presented that may be 
useful in predicting the performance of phase locked loops. 
A phase locked loop integrated circuit has been described 
and several applications have been given to illustrate the 
use of the circuit and the design techniques presented. 

REFERENCES 

1. Floyd M. Gardner, "Phaselock Techniques", John Wiley 
and Sons, 1966. 

2. Elliot L. Greenberg, "Handbook of Telemetry and Remote 
Control", McGraw-Hill, 1967. 

3. Andrew Viterbi, "Principles of Coherent Communication", 
McGraw-Hill, 1966. 



132 



Applications for a New 
Ultra-High Speed Buffer 



INTRODUCTION 

Voltage followers have gained in popularity in applications 
such as sample and hold circuits, general purpose buffers, 
and active filters since the introduction of IC operational am- 
plifiers. Since they were not specifically designed as follow- 
ers, these early IC's had limited usage due to low band- 
width, low slew rate and high input current. Usage of voltage 
followers was expanded in 1967 with the introduction of the 
LM102, the first IC designed specifically as a voltage follow- 
er. With the LM102, engineers were able to obtain an order 
of magnitude improvement in performance and extend us- 
age into medium speed applications. The LM110, an im- 
proved LM102, was introduced in late 1969. However, even 
higher speeds and lower input currents were needed for 
very fast sample and holds, A to D and D to A converters, 
coax cable drivers, and other video applications. 
The solution to this application problem was attained by 
combining technologies into a single package. The result, 
the LH0033 high speed buffer, utilizes JFET and bipolar 
technology to produce a ultra-fast voltage follower and buff- 
er whose propagation delay closely approaches speed-of- 
light delay across its package, while not compromising input 
impedance or drive characteristics. Table I compares vari- 
ous voltage followers and illustrates the superiority of the 
LH0033 in both low input current or high speed video appli- 
cations. 

CIRCUIT CONSIDERATIONS 

The junction FET makes a nearly ideal input device for a 
voltage follower, reducing input bias current to the picoamp 
range. However, FET's exhibit moderate voltage offsets and 
offset drifts which tend to be difficult to compensate. The 
simple voltage follower of Figure 1 eliminates initial offset 
and offset drift if Q-\ and Q2 are identically matched transis- 
tors. Since the gate to source voltage of Q2 equals zero 
volts, then Qi's gate to source voltage equals zero volts. 
Furthermore as Vpi changes with temperature (approxi- 
mately 2.2 mv7°C), Vp2 will change by a corresponding 
amount. However, as load current is drawn from the output, 
Qi and Q2 will drift at different rates, A circuit which over- 
comes offset voltage drift is used in a new high speed buffer 
amplifier, the LH0033. Initial offset is typically 5 mV and 
offset drift is 20 fiV/°C. Resistor R2 is used to establish the 
drain current of current source transistor, Q2 at 10 mA. 
The same drain current flows through Q 1 causing a voltage 
at the source of approximately 1.1V. The 10 mA flowing 
through Ri plus Q3's V BE of 0.6V causes the output to sit at 



National Semiconductor 
Application Note 48 




v+ 



¥ £ 



6 

V" 

TL/K/7318-1 

FIGURE 1. Simple Voltage Follower Schematic 

zero volts for zero volts in. Q 3 and Q4 eliminate loading the 
input stage (except for base current) and CR1 and CR2 es- 
tablish the output stage collector current. 

If Q1 and Q2 are matched, the resulting drift is reduced to a 
few jaV/°C. 

PERFORMANCE OF THE LH0033 FAST VOLTAGE 
FOLLOWER/BUFFER 

The major electrical characteristics of the LH0033 are sum- 
marized in Table II. All the virtues of a ultra-high speed buff- 
er have been incorporated. 

Figure 3 is a plot of input bias current vs temperature and 
shows the typical FET input characteristics. Other typical 
performance curves are illustrated in Figures 4 through 10. 
Of particular interest is Figure 8, which demonstrates the 
performance of the LH0033 in video applications to over 
100 MHz. 

APPLICATIONS FOR ULTRA-FAST FOLLOWERS 

The LH0033's high input impedance (101 1 ft, shunted by 
2 pF) and high slew rate assure minimal loading and high 
fidelity in following high speed pulses and signals. As 
shown below, the LH0033 is used as a buffer between MOS 
logic and a high speed dual limit comparator. The device's 
high input impedance prevents loading of the MOS logic 
signal (even a conventional scope probe will distort high 
output impedance MOS). The LH0033 adds about a 1 .5 ns 
to the total delay of the comparator. Adjustment of voltage 
divider R 1f R 2 allows interface to TTL, DTL and other high 
speed logic forms. 



TABLE I. COMPARISON OF VOLTAGE FOLLOWERS 





Conventional 


First Generation 


Second Generation 


Specially Designed 


Parameter 


Monolithic Op Amp 


Voltage Follower 


Voltage Follower 


Voltage Follower 




LM741 


LM102 


LM110 


LH0033 


Input Bias Current 


200 nA 


3.0 nA 


1.0 nA 


0.05 nA 


Slew Rate 


0.5 V/ju.s 


10V/ju,s 


30V/jj,s 


1500V/ jus 


Bandwidth 


1.0 MHz 


10 MHz 


20 MHz 


100 MHz 


Prop. Delay Time 


350 ns 


35 ns 


18 ns 


1.2 ns 


Output Current Capability 


±5mA 


±2mA 


±2mA 


± 100 mA 





133 



00 

z 

< 




OUTPUT 







00O 



© 



©-£>-© 



,0. 



OFFSET "\© © © 



0, 



OFFSET 



Top View 
FIGURE 2. LH0033 Schematic 



TABLE II 



Parameter 



Conditions 



Value 



Parameter 



Conditions 



Value 



Output Offset Voltage 
Input Bias Current 
Input Impedance 

Voltage Gain 

Output Voltage Swing 



R s = 100 kH 

Vin = 1 .0 Vrms 

R L = 1k,f = 1 kHz 

Vin = 1 .0 Vrms 

R L = 1k, f = 1kHz,R s = 100k 

V s = ±15V, Rs = 100k 

R L = 1k 



5mV 
50 pA 
1011 n 

0.98 

±13V 



Output Current Capability 
Slew Rate 
Propagation Delay 

Bandwidth 



R s = 50n,R L = 1k 



Vin = 1 .0 Vrms 
R s = 50n, R L = 1k 



± 100 mA peak 

1500V//xs 

1.2 ns 

100 MHz 



134 



I 

I"" 













































±15V — 














V,-±1 


IV 













































25 SO 75 105 125 

TEMPERATURE f*C| 















v. 


- ±15.0V 


1.0 












R< 


'tOtk ' 


















«.o 


































2.0 





















































50 IN 

TEMPERATURE CO 





1 








Rciootn 















































































SUPPLY VOLTAGE (IV) 



FIGURE 3. Input Bias 
Current vs Temperature 



FIGURE 4. Output Offset 
Voltage vs Temperature 



FIGURE 5. Output Voltage vs 
Supply Voltage 



V,-±1SV ,_ 

S • «-R»-son |Pw 

J. I R L -1kR l| 

i mi ' i I f - 

S . _|_ input — •£ 

§ "• t- 1 — output f 

§ ^t M 

I -„ 



30 «0 

TMEM 



FIGURE 6. Negative 
Pulse Response 



£ ,2 

Ml 


V, "±15V 

R t ■ i ui. r, - son 

[ T T_j — 

| INPUT — »ti 
'•m OUTPUT II 

— f- 



10 » 30 40 00 

TIME In) 

FIGURE 7. Positive Pulse 
Response 



Vf 


1 1 

•itSV 


1 








Rt-son 

R L *f0R 










v M 


•1.0V 


rim 






I 










* 


J 












/ 










, 


/ 










A 










S 


r 





30 2 
2S £ 



2J S.0 10J 20J 00 

FREQUENCY <MHt) 

FIGURE 8. Frequency 
Response 



f. 

























































\H 


■-OS 


•c 








\ N T A .+2t*C 








N T A -+12TC 















15 
i(*V) 



FIGURE 9. Supply Current 
vs Supply Voltage 



1 '•" 

a 

s 

i « 



v« 


■±1SV 












"Rt'MR 
-R t «1k 






















<i 












































V 







































TEMPERATURE CO 

FIGURE 10. Rise and Fall 
Time vs Temperature 



TL/K/7318-3 



135 



00 




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1/4 5402 



'REF2 y- 

FIGURE 11. High Speed Dual Limit Comparator for MOS Logic 



The LH0033 was designed to drive long cables, shielded 
cables, coaxial cables and other generally stringent line 
driving requirements. It will typically drive 200 pF with no 
degradation in slew rate and several thousand pF at a re- 
duced rate. In order to prevent oscillations with large capac- 
itive loads, provision has been made to insert damping re- 
sistors between V+ and pin 1, and V - and pin 9. Values 
between 47 and 100ft work well for C L > 1000 pF. For non- 
reactive loads, pin 1 2 should be shorted to pin 1 and pin 1 
shorted to pin 9. A coaxial driver is shown in Figure 13. Pin 6 
is shorted to pin 7, obtaining an initial offset of 5.0 mV, and 
the 43ft coupled with the LH0033's output impedance 
(about 6ft) match the coaxial cable's characteristic imped- 
ance. C-| is adjusted as a function of cable length to opti- 
mize rise and fall time. Rise time for the circuit as shown in 
Figure 12, is 1 ns. 

Another application that utilizes the low input current, high 
speed and high capacitance drive capabilities of the 
LH0033 is a shield or line driver for high speed automatic 
test equipment. In this example, the LH0033 is mounted 



close to the device under test and drives the cable shield 
thus allowing higher speed operation since the device under 
test does not have to charge the cable. 













































































































H0R2 


:10ns/DIV 
















VERT:2V/DIV 



TL/K/7318-5 

FIGURE 12. LH0033 Pulse Response into 
10 Foot Open Ended Coaxial Cable 




10FT 0FRG-S9 



■O OUTPUT 



VERT 2V/cm 
H0RIZ: lOnt/cm 



-1SV 



TL/K/7318-6 



FIGURE 13 



136 




TL/K/7318-7 

FIGURE 14. Instrumentation Shield/Line Driver 

The LH0033's high input impedance and low input bias cur- 
rent may be utilized in medium speed circuits such as Sam- 
ple and Hold, and D to A converters. Figure 15 shows an 
LH0033 used as a buffer in medium speed D to A converter. 



Offset null is accomplished by connecting a 100Q pot be- 
tween pin 7 and V - . It is generally a good idea to insert 20H 
in series with the pot to prevent excessive power dissipation 
in the LH0033 when the pot is shorted out. In non-critical or 
AC coupled applications, pin 6 should be shorted to pin 7. 
The resulting output offset is typically 5 mV at 25°C. 
The high output current capability and slew rate of the 
LH0033 are utilized in the sample and hold circuit of Figure 
16. Amplifier, A1 is used to buffer high speed analog sig- 
nals. With the configuration shown, acquisition time is limit- 
ed by the time constant of the switch "ON" resistance and 
sampling capacitor, and is typically 200 or 300 ns. 
A2's low input bias current, results in drifts in hold mode of 



50 mV 
sec 



• at 25°C and 



1V 

— at125°C. 
sec 



The LH0033 may be utilized in AC applications such as vid- 
eo amplifiers and active filters. The circuit of Figure 17 uti- 
lizes boot strapping to achieve input impedances in excess 
of 10 Mil. 



12 "=■ 






1 .„.,., J 


— 1 

1 


! 






w < 


1 

: 


L - 


< 




































i 

Vr 


!> 

F 







rn 



FIGURE 15 



137 



00 



ANALOG i 

INPUT 




'Polycarbonate or Teflon 



FIGURE 16. High Speed Sample and Hold 



INPUT O 




INPUT O 



fH ;> 100 MHz 




TL/K/7318-10 

FIGURE 17. High Input Impedance 
AC Coupled Amplifier 

A single supply, AC coupled amplifier is shown in Figure 18. 
Input impedance is approximately 500k and output swing is 
in excess of 8V peak-to-peak with a 1 2V supply. 
The LH0033 may be readily used in applications where sym- 
metrical supplies are unavailable or may not be desirable. A 



TL/K/7318-11 

FIGURE 18. Single Supply AC Amplifier 

typical application might be an interface to an MOS shift 
register where V+ = 5.0V and V~ = -25V. In this case, 
an apparent output offset occurs. In reality, the output volt- 
age is due to the LH0033's voltage gain of less than unity. 



138 



The output voltage shift due to asymmetrical supplies may 
be predicted by: 



AV = (1 - Av) 



(V+ - V-) 



= .005 (V+ - V-) 



where: Av = No load voltage gain, typically 0.99. 

V+ = Positive Supply Voltage. 

V~ = Negative Supply Voltage. 
For the foregoing application, AVo would be - 100 mV. This 
apparent "offset" may be adjusted to zero as outlined 
above. 

Figure 19 shows a high Q, notch filter which takes advan- 
tage of the LH0033's wide bandwidth. For the values 
shown, the center frequency is 4.5 MHz. 
The LH0033 can also be used in conjunction with an opera- 
tional amplifier as current booster as shown in Figure 20. 



Output currents in excess of 100 mA may be obtained. In- 
clusion of 1 50H resistors between pins 1 and 1 2, and 9 and 
10 provide short circuit protection, while decoupling pins 1 
and 9 with 1000 pF capacitors allow near full output swing. 
The value for the short circuit current is given by: 

V+ v- 
isc s = 

R LIMIT RlIMIT 

where: Isc ^ 100 mA. 
SUMMARY 

The advantages of a FET input buffer have been demon- 
strated. The LH0033 combined very high input impedance, 
wide bandwidth, very high slew rate, high output capability, 
and design flexibility, making it an ideal buffer for applica- 
tions ranging from DC to in excess of 100 MHz. 



> 
Z 

00 




C2 
300 pF 

L — WV— •— VW— J 

Ri R1 
220O 220n 

V 

FIGURE 19. 4.5 MHz Notch Filter 



•u 


2irR1C1 


R1 


= 2R2 


C1 


_ C2 
2 


TL/K/7318-12 



INPUT 



RF 

■AAAr 



+15V 
O .001 ju.F 

ison 




_Q OUTPUT 



±15 
ISC = = 100 mA 



TL/K/7318-13 



FIGURE 20. Using LH0033 as an Output Buffer 



139 



PIN Diode Drivers 



National Semiconductor 
Application Note 49 



^ 



INTRODUCTION 

The DH0035/DH0035C is a TTL/DTL compatible, DC cou- 
pled, high speed PIN diode driver. It is capable of delivering 
peak currents in excess of one ampere at speeds up to 
1 MHz. This article demonstrates how the DH0035 may be 
applied to driving PIN diodes and comparable loads which 
require high peak currents at high repetition rates. The sa- 
lient characteristics of the device are summarized in Table I. 

TABLE I. DH0035 Characteristics 



Parameter 


Conditions 


Value 


Differential Supply 
Voltage (V+ - V~) 




30V Max. 


Output Current 




1000 mA 


Maximum Power 




1.5W 


tdelay 


PRF = 5.0 MHz 


10 ns 


Vise 


V+ - V- = 20V 
10% to 90% 


15 ns 


tfall 


V+ - V- = 20V 

90% to 10% 


10 ns 



PIN DIODE SWITCHING REQUIREMENTS 

Figure 1 shows a simplified schematic of a PIN diode switch. 
Typically, the PIN diode is used in RF through microwave 
frequency modulators and switches. Since the diode is in 
shunt with the RF path, the RF signal is attenuated when 
the diode is forward biased ("ON"), and is passed unattenu- 
ated when the diode is reversed biased ("OFF"). There are 
essentially two considerations of interest in the "ON" condi- 
tion. First, the amount of "ON" control current must be suffi- 
cient such that RF signal current will not significantly modu- 
late the "ON" impedance of the diode. Secondly, the time 
required to achieve the "ON" condition must be minimized. 



RF0UT 




CONTROL NODE 

TL/H/8750-1 

FIGURE 1. Simplified PIN Diode Switch 



The charge control model of a diode 1 . 2 leads to the charge 
continuity equation given in equation (1 ). 



. = dQ Q 
' dt t 



(D 



where: Q = charge due excess minority carriers 
t = mean lifetime of the minority carriers 
Equation (1) implies a circuit model shown in Figure 2. Un- 

dQ 
der steady conditions — = 0, hence: 
dt 



where: 



Q 
Idc = - or Q = Iqc • f 

T 

steady state "ON" current. 



(2) 



I = Total Current 
Inc = SS Control Current 
iRF = RF Signal Current 



I * 'OC + 'RF 



TL/H/8750-2 

FIGURE 2. Circuit Model for PIN Switch 

The conductance is proportional to the current, I; hence, in 
order to minimize modulation due to the RF signal, Irx > 
iRF. Typical values for Iqc range from 50 mA to 200 mA 
depending on PIN diode type, and the amount of modulation 
that can be tolerated. 

The time response of the excess charge, Q, may be evalu- 
ated by taking the Laplace transform of equation (1) and 
solving for Q: 

Tl(S) 



Q(s) 



1 + ST 



(3) 



Solving equation (3) for Q(t) yields: 

Q(t) = L-1 [Q(s)] = It (1 - e~^) (4) 

The time response of Q is shown in Figure 3a. As can be 
seen, several carrier lifetimes are required to achieve the 
steady state "ON" condition (Q = Iqc • *)• 



140 



The time response of the charge, hence the time for the 
diode to achieve the "ON" state could be shortened by ap- 
plying a current spike, Ipk, to the diode and then dropping 
the current to the steady state value, Idc. as shown in Fig- 
ure 3b. The optimum response would be dictated by: 

(Ipk) (t) = r • l DC (5) 




FIGURE 3a 



Idc" 



TL/H/8750-4 



FIGURE 3b 



The turn off requirements for the PIN diode are quite similar 
to the turn on, except that in the "OFF" condition, the 
steady current drops to the diode's reverse leakage current. 
A charge, Idc • T > was stored in the diode in the "ON" 
condition and in order to achieve the "OFF" state this 
charge must be removed. Again, in order to remove the 
charge rapidly, a large peak current (in the opposite direc- 
tion) must be applied to the PIN diode: 



Q 
-Ipk > - 



(6) 



It is interesting to note an implication of equation (5). If the 
peak turn on current were maintained for a period of time, 
say equal to t, then the diode would acquire an excess 
charge equal to Ipk • T. This same charge must be removed 
at turn off, instead of a charge Idc • T > resulting in a consid- 
erably slower turn off. Accordingly, control of the width of 
turn on current peak is critical in achieving rapid turn off. 

APPLICATION OF THE DH0035 AS A PIN DIODE DRIVER 

The DH0035 is specifically designed to provide both the 
current levels and timing intervals required to optimally drive 
PIN diode switches. Its schematic is shown in Figure 4. The 
device utilizes a complementary TTL input buffer such as 
the DM7830/DM8830 or DM5440/DM7440 for its input sig- 
nals. 

Two configurations of PIN diode switch are possible: cath- 
ode grounded and anode grounded. The design procedures 
for the two configurations will be considered separately. 

ANODE GROUND DESIGN 

Selection of power supply voltages is the first consideration. 
Table I reveals that the DH0035 can withstand a total of 
30V differentially. The supply voltage may be divided sym- 
metrically at ±15V, for example. Or asymmetrically at 
+ 20V and -10V. The PIN diode driver shown in Figure 5, 
uses +10V supplies. 

When the Q output of the DM8830 goes high a transient 
current of approximately 50 mA is applied to the emitter of 
Qi and in turn to the base of Q5. 

Q5 has an hf e = 20, and the collector current is hf e x 50 or 
1000 mA. This peak current, for the most part, is delivered 
to the PIN diode turning it "ON" (RF is "OFF"). 
Ipk flows until Cj is nearly charged. This time is given by: 
C2AV 

t = lpF (7) 

where: AV = the change in voltage across C2. 
Prior to Qs's turn on, C2 was charged to the minus supply 
voltage of -10V. C2's voltage will rise to within two diode 
drops plus a V sat of ground: 

V = |V"| - Vf(PIN Diode) - Vfcm - V satQ5 (8) 
forV- = -10V, AV = 8V. 

Once C2 is charged, the current will drop to the steady state 
value, Ipc. which is given by: 

V V+ 
Idc = : 



R3 



Vcc 
R1 



where: Vcc = 5 °V 
R-, = 250fi 
R 3 = 500H 

■'■ Rm = 



(R 3 (AV)(R 1 ) 



R1V+ + IDCR3R1 + V CC R3 



(9) 



(9a) 



141 



R1 
7 250O 

O VNAr- 

U 



R2 
3 3kO 

O— VSAr 



R3 

soon 



T~& T 

fcJ 

4 
TCR3 



< 



C 



5 0GND 



6 6 



TL/H/8750-5 



FIGURE 4. DH0035 Schematic Diagram 



SUV 



n 



200 pF 



r 



LlIl_ m 

I 250 pF _L. 



X- 




> 



20 pF 



1/2 DM8830 






T 



^S^ I DIODE W 

<r | SWITCH -f- 

I 

"I DH003S ! Ju 



o 

-10 V = V" 



1 



TL/H/8750-6 



FIGURE 5. Cathode Grounded Design 



142 



t = 



c 9 = 



(10) 



(11) 



For the driver of Figure 5, and Ipc = 1°° mA > R M is 56ft 
(nearest standard value). 

Returning to equation (7) and combining it with equation (5) 
we obtain: 

Tlpc _ C 2 V 
Ipk Ipk 
Solving equation (10) for C 2 gives: 

' dct 
V 

Forr = 10 ns, C 2 = 120 pF. 

One last consideration should be made with the diode in the 
"ON" state. The power dissipated by the DH0035 is limited 
to 1.5W (see Table I). The DH0035 dissipates the maximum 
power with Q5 "ON". With Q5 "OFF", negligible power is 
dissipated by the device. Power dissipation is given by: 

Pdiss « [idc(|v-| - av) + (V+ ~ 3 V)2 ] 

X (D.C.) £ P max 
where: D.C. = Duty Cycle = 

("ON" time) 



(12) 



("ON" time + "OFF" time) 
Pmax = 1.5W 



In terms of Idc : 



Idc^ 



[(Pmax) 
I (D.C.) 



(V- 



V-)2 



500 



(12a) 



|V~| - AV 

For the circuit of Figure 5 and a 50% duty cycle, P diss = 
0.5W. 

Turn-off of the PIN diode begins when the Q output of the 
DM8830 returns to logic "0" and the Q output goes to logic 
"1". Q2 turns "ON", and in turn, causes Q3 to saturate. 
Simultaneously, Q1 is turned "OFF" stopping the base drive 



to Q5. Q3 absorbs the stored base charge of Q5 facilitating 
its rapid turn-off. As Qs's collector begins to rise, Q 4 turns 
"ON". At this instant, the PIN diode is still in conduction and 
the emitter of Q4 is held at approximately -0.7V. The in- 
stantaneous current available to clear stored charge out of 
the PIN diode is: 

V + ~ Vbe Q4 + V f(PIN) 



<0 



Ipk = 



R3 



hfe+1 
(h fe + D(V + ) 
R 3 



(13) 



where: 

hf e + 1 = current gain of Q4 = 20 
Vbe Q4 = base-emitter drop of Q4 = 0.7V 
Vf(piM) = forward drop of the PIN diode = 0.7V 
For typical values given, Ipk = 400 mA. Increasing V+ 
above 10V will improve turn-off time of the diode, but at the 
expense of power dissipation in the DH0035. Once turn-off 
of the diode has been achieved, the DH0035 output current 
drops to the reverse leakage of the PIN diode. The attend- 
ant power dissipation is reduced to about 35 mW. 

CATHODE GROUND DESIGN 

Figure 6 shows the DH0035 driving a cathode grounded PIN 
diode switch. The peak turn-on current is given by: 
(V+ -V-) (h f e + 1) 



Ipk = 



R3 



(14) 



= 800 mA for the values shown. 

The steady state current, Ipc. is set by Rp and is given by: 
(V+ - 2V BE 



be - 



R3 



h fe + 1 



+ R P 



(15) 



where: 2Vbe = forward drop of Q4 base emitter junction 
plus V f of the PIN diode = 1.4V. 



143 



V* = 10V 

Q 



3.UV 



n 



200 pF 



M~ 



£t*1 



0.1 >jF 



LOGIC O- 
INPUT o- 



01 







1/2 OM7830/OM8830 j ' i 



I 



L>Tt>Th 

•^ ^ 1 12 

^^ , DIODE ~T 

r I I SWITCH ^ 

DH0035 . _|_ 



T"T3-* 



C2 

R M i 120 

56ft > 



n. 



FIGURE 6. Anode Grounded Driver 



TL/H/8750-7 



In terms of Rp, equation (15) becomes: 
(h fe +1)(V+ -2V BE ) 



Rp = 



!dcR9 



(15a) 



(hfe+ 1)lDC 

For the circuit of Figure 6, and Iqc = 1 00 mA, Rp is 62H 
(nearest standard value). 

It now remains to select the value of C-|. To do this, the 
change in voltage across Ci must be evaluated. In the 
"ON" state, the voltage across C-|, Vc, is given by: 
,..„, V + R 3 + Rp(h f e+1)(2V BE ) 

(VC)ON = P 4. (H 4-tiDn (16) 

F>3 + (hfe + 1)Rp 
For the values indicated above, (Vc)on = 3.8V. 
In the "OFF" state, Vc is given by: 

(VC)0Fp - Rp + R 3 07) 

= 8.0V for the circuit of Figure 6. 
Hence, the change in voltage across C-t is: 
V = (Vc)off - (Vc)on 
= 8.0 - 3.8 
= 4.2V 
The value of C4 is given, as before, by equation (11): 

For a diode with r = 10 ns and Iqc = 1 00 mA, C1 = 
250 pF. 



(18) 



(19) 



Again the power dissipated by the DH0035 must be consid- 
ered. In the "OFF" state, the power dissipation is given by: 

rv+ - v-)2i 



P0FF = 



R 3 



(D.C.) 



(20) 



where: D.C. = duty cycle = 

"OFF" time 



"OFF" time + "ON" time 



The "ON" power dissipation is given by: 

PON = [^^ + 'DC X (Vc)on] (1 - D.C.) (21) 

where: (Vc)on is defined by equation (16). 

Total power dissipated by the DH0035 is simply Pon + 

Pqff- For a 50% dlJ ty c y c ' e and tne circuit of Figure 6, 

Pdiss = 616 mW. 

The peak turn-off current is, as indicated earlier, equal to 

50 mA x hf e which is about 1000 mA. Once the excess 

stored charge is removed, the current through Q5 drops to 

the diodes leakage current. Reverse bias across the diode 

= V - - V sat as - 10V for the circuit of Figure 6. 

REPETITION RATE CONSIDERATIONS 

Although ignored until now, the PRF, in particular, the 
"OFF" time of the PIN diode is important in selection of C2, 
Rm, and C-) , Rp. The capacitors must recharge completely 
during the diode "OFF" time. In short: 

4 R M C 2 ^ t 0F F (22a) 

4 RpCT < t 0F F (22b) 



144 



CONCLUSION 

The circuit of Figure 6 was breadboarded and tested in con- 
junction with a Hewlett-Packard 33622A PIN diode. 
Irj>c was set at 100 mA, V+ = 10V, V~ = 10V. Input signal 
to the DM8830 was a 5V peak, 100 kHz, 5 jj.s wide pulse 
train. RF turn-on was accomplished in 10-12 ns while turn- 
off took approximately 5 ns, as shown in Figures 7 and 8. 
In practice, adjustment C2 (C1) may be required to accom- 
modate the particular PIN diode minority carrier lifetime. 



SUMMARY 

A unique circuit utilized in the driving of PIN diodes has been 
presented. Further a technique has been demonstrated 
which enables the designer to tailor the DH0035 driver to 
the PIN diode application. 

REFERENCES 

1. "Pulse, Digital, & Switching Waveforms", Jacob Millman 
& Herbert Taub, McGraw-Hill Book Company, Inc., New 
York, N.Y. 

2. "Models of Transistors and Diodes", John G. Linvill, 
McGraw-Hill Book Company, Inc., New York, N.Y. 

3. National Semiconductor AN- 18, Bert Mitchell, March 
1969. 

4. Hewlett-Packard Application Note 314, January 1967. 



> 

Z 
■ 



145 



1.2 V Reference 



National Semiconductor 
Application Note 56 




INTRODUCTION 

Temperature compensated zener diodes are the most easi- 
ly used voltage reference. However, the lowest voltage tem- 
perature-compensated zener is 6.2V. This makes it inconve- 
nient to obtain a zero temperature-coefficient reference 
when the operating supply voltage is 6V or lower. With the 
availability of the LM113, this problem no longer exists. 
The LM1 13 is a 1.2V temperature compensated shunt regu- 
lator diode. The reference is synthesized using transistors 
and resistors rather than a breakdown mechanism. It pro- 
vides extremely tight regulation over a wide range of operat- 
ing currents in addition to unusually low breakdown voltage 
and low temperature coefficient. 

DESIGN CONCEPTS 

The reference in the LM113 is developed from the highly- 
predictable emitter-base voltage of integrated transistors. In 
its simplest form, the voltage is equal to the energy-band- 
gap voltage of the semiconductor material. For silicon, this 
is 1 .205V. Further, the output voltage is well determined in a 
production environment. 

A simplified version of this reference 1 is shown in Figure 1. 
In this circuit, Qi is operated at a relatively high current 
density. The current density of Qg is about ten times lower, 
and the emitter-base voltage differential (AVbe) between 
the two devices appears across R3. If the transistors have 
high current gains, the voltage across R2 will also be pro- 
portional to AVbe- Q3 is a gain stage that will regulate the 
output at a voltage equal to its emitter base voltage plus the 
drop across R2. The emitter base voltage of Q3 has a nega- 
tive temperature coefficient while the AVbe component 
across R2 has a positive temperature coefficient. It will be 
shown that the output voltage will be temperature compen- 
sated when the sum of the two voltages is equal to the 
energy-band-gap voltage. 



R2 
Vref = V BE + — AV BE 




GROUND 



TL/H/7370-1 

FIGURE 1. The Low Voltage Reference 
in One of Its Simpler Forms 



Conditions for temperature compensation can be derived 
starting with the equation for the emitter-base voltage of a 
transistor which is 2 

VBE = V g0 (l-^) + V B Eo(^) + 



nkT T ^ kT l c 

q T q Ico 



(D 



where V g0 is the extrapolated energy-band-gap voltage for 
the semiconductor material at absolute zero, q is the charge 
of an electron, n is a constant which depends on how the 
transistor is made (approximately 1.5 for double-diffused, 
NPN transistors), k is Boltzmann's constant, T is absolute 
temperature, lc is collector current and Vbeo is the emitter- 
base voltage at Tq and Ico- 

The emitter-base voltage differential between two transis- 
tors operated at different current densities is given by 



kT J! 

AV BE = — log e — 

q J 2 



(2) 



where J is current density. 

Referring to Equation (1), the last two terms are quite small 
and are made even smaller by making lc vary as absolute 
temperature. At any rate, they can be ignored for now be- 
cause they are of the same order as errors caused by non- 
theoretical behavior of the transistors that must be deter- 
mined empirically. 

If the reference is composed of Vbe plus a voltage propor- 
tional to AVbe, the output voltage is obtained by adding (1 ) 
in its simplified form to (2): 



V r e, = V g0 (l-l) + V BE o(^) + ^log e ^ 



(3) 



(4) 



Differentiating with respect to temperature yields 

3Vref 
3T 

For zero temperature drift, this quantity should equal zero, 
giving 



v go Vbeo , k ^ 
To T q J2 



kT Ji 
V g o = Vbeo + ~r log e t- 
q J 2 



(5) 



The first term on the right is the initial emitter-base voltage 
while the second is the component proportional to emitter- 
base voltage differential. Hence, if the sum of the two are 
equal to the energy-band-gap voltage of the semiconductor, 
the reference will be temperature-compensated. 
Figure 2 shows the actual circuit of the LM113. Q1 and Q2 
provide the AVbe term ar| d Q4 provides the Vbe term as in 
the simplified circuit. The additional transistors are used to 
decrease the dynamic resistance, improving the regulation 
of the reference against current changes. Q3 in conjunction 
with current inverter, Q5 and Qq, provide a current source 
load for Q4 to achieve high gain. 

Q7 and Q9 buffer Q4 against changes in operating current 
and give the reference a very low output resistance. Qs sets 
the minimum operating current of Q7 and absorbs any leak- 



146 







FIGURE 2. Schematic of the LM113 



age from Qg. Capacitors C-), C2 and resistors Rg and R10 
frequency compensate the regulator diode. 

PERFORMANCE 

The most important features of the regulator diode are its 
good temperature stability and low dynamic resistance. Fig- 
ure 3 shows the typical change in output voltage over a 
-55°C to +125°C temperature range. The reference volt- 
age changes less than 0.5% with temperature, and the tem- 
perature coefficient is relatively independent of operating 
current. 

Figure 4 shows the output voltage change with operating 
current. From 0.5 mA to 20 mA there is only 6 mV of 
change. A good portion of the output change is due to the 
resistance of the aluminum bonding wires and the Kovar 
leads on the package. At currents below about 0.3 mA the 
diode no longer regulates. This is because there is insuffi- 
cient current to bias the internal transistors into their active 
region. Figure 5 illustrates the breakdown characteristic of 
the diode. 



> 1.230 



10 

1 • 

3 6 

X 

u 

a 4 

< 

1 ■ 

e 

-2 

















II 


















1 


25° C 

mi 


~*; 
















• 










,*V 


















/ 
















. 


'Ml 


^-5 


i°C 





















30 



0.3 1 3 10 

REVERSE CURRENT (mA) 

TL/H/7370-4 

FIGURE 4. Output Voltage Change with Current 



10- 2 















1 


t*1mA 































































































































U10 



1200 

-55 -35 -15 5 25 45 65 05 105 125 

TEMPERATURE (°C) 

TL/H/7370-3 

FIGURE 3. Output Voltage Change with Temperature 



























125° 


25°Cy 




^55°C 







10- 4 



ir B 

0.2 0.4 0.6 0.1 1.0 1.2 1.4 
REVERSE VOLTAGE (V) 

TL/H/7370-5 

FIGURE 5. Reverse Breakdown Characteristics 
APPLICATIONS 

The applications for zener diodes are so numerous that no 
attempt to delineate them will be made. However, the low 



147 



breakdown voltage and the fact that the breakdown voltage 
is equal to a physical property of silicon — the energy band 
gap voltage— makes it useful in several interesting applica- 
tions. Also the low temperature coefficient makes it useful in 
regulator applications — especially in battery powered sys- 
tems where the input voltage is less than 6V. 
Figure 6 shows a 2V voltage regulation which will operate 
on input voltages of only 3V. An LM1 13 is the voltage refer- 
ence and is driven by a FET current source, Q-| . An opera- 
tional amplifier compares a fraction of the output voltage 
with the reference. Drive is supplied to output transistor Q 2 
through the V+ power lead of the operational amplifier. Pin 
6 of the op amp is connected to the LM1 13 rather than the 
output since this allows a lower minimum input voltage. The 
dynamic resistance of the LM113 is so low that current 
changes from the output of the operational amplifier do not 
appreciably affect regulation. Frequency compensation is 
accomplished with both the 50 pF and the 1 jnF output ca- 
pacitor. 

Win > 3V 




Vout = ZV 



t Solid tantalum 



TL/H/7370-6 

FIGURE 6. Low Voltage Regulator Circuit 

It is important to use an operational amplifier with low quies- 
cent current such as an LM108. The quiescent current flows 
through R 2 and tends to turn on Q 2 . However, the value 
shown is low enough to insure that Q 2 can be turned off at 
worst case condition of no load and 1 25°C operation. 
Figure 7 shows a differential amplifier with the current 
source biased by an LM113. Since the LM113 supplies a 
reference voltage equal to the energy band gap of silicon, 
the output current of the 2N2222 will vary as absolute tem- 
perature. This compensates the temperature sensitivity of 
the transconductance of the differential amplifier making the 
gain temperature stable. Further, the operating current is 




FIGURE 7. Amplifier Biasing for 
Constant Gain with Temperature 

regulated against supply variations keeping the gain stable 
over a wide supply range. 

As shown, the gain will change less than two per cent over a 
-55°C to +125°C temperature range. Using the LM114A 
monolithic transistor and low drift metal film resistors, the 
amplifier will have less than 2 ju,V/°C voltage drift. Even low- 
er drift may be obtained by unbalancing the collector load 
resistors to null out the initial offset. Drift under nulled condi- 
tion will be typically less than 0.5 ju.V/°C. 
The differential amplifier may be used as a pre-amplifier for 
a low-cost operational amplifier such as an LM101A to im- 
prove its voltage drift characteristics. Since the gain of the 
operational amplifier is increased by a factor of 100, the 
frequency compensation capacitor must also be increased 
from 30 pF to 3000 pF for unity gain operation. To realize 
low voltage drift, case must be taken to minimize thermo- 
electric potentials due to temperature gradients. For exam- 
ple, the thermoelectric potential of some resistors may be 
more than 30 ju,V/°C, so a 1°C temperature gradient across 
the resistor on a circuit board will cause much larger errors 
than the amplifier drift alone. Wirewound resistors such as 
Evenohm are a good choice for low thermoelectric poten- 
tial. 

Figure 8 illustrates an electronic thermometer using an inex- 
pensive silicon transistor as the temperature sensor. It can 
provide better than 1°C accuracy over a 100°C range. The 
emitter-base turn-on voltage of silicon transistors is linear 
with temperature. If the operating current of the sensing 
transistor is made proportional to absolute temperature the 
nonlinearily of emitter-base voltage can be minimized. Over 
a -55°C to 125°C temperature range the nonlinearily is less 
than 2 mV or the equivalent of 1°C temperature change. 
An LM113 diode regulates the input voltage to 1.2V. The 
1.2V is applied through R 2 to set the operating current of 
the temperature-sensing transistor. 
Resistor R 4 biases the output of the amplifier for zero output 
at 0°C. Feedback resistor R5 is then used to calibrate the 
output scale factor to 1 00 mV/°C. Once the output is ze- 
roed, adjusting the scale factor does not change the zero. 



148 



R6 
100K 




CJ1 



t Adjust for OV at 0°C 
* Adjust for 100 mV/°C 



TL/H/7370-8 



FIGURE 8. Electronic Thermometer 



CONCLUSION 

A new two terminal low voltage shunt regulator has been 
described. It is electrically equivalent to a temperature-sta- 
ble 1.2V breakdown diode. Over a -55°C to 125°C temper- 
ature range and operating currents of 0.5 mA to 20 mA the 
LM113 has one hundred times better reverse characteris- 
tics than breakdown diode. Additionally, wideband noise 
and long term stability are good since no breakdown mech- 
anism is involved. 

The low temperature coefficient and low regulation voltage 
make it especially suitable for a low voltage regulator or 
battery operated equipment. Circuit design is eased by the 



fact that the output voltage and temperature coefficient are 
largely independent of operating current. Since the refer- 
ence voltage is equal to the extrapolated energy-band-gap 
of silicon, the device is useful in many temperature compen- 
sation and temperature measurement applications. 

REFERENCES 

1 . R.J. Widlar, "On Card Regulator for Logic Circuits, " Na- 
tional Semiconductor AN-42, February, 1971. 

2. J.S. Brugler, "Silicon Transistor Biasing for Linear Collec- 
tor Current Temperature Dependence," IEEE Journal of 
Solid State Circuits, pp. 57-58, June, 1967. 



149 



LM380 Power Audio 
Amplifier 



National Semiconductor 
Application Note 69 



^ 



INTRODUCTION 

The LM380 is a power audio amplifier intended for consum- 
er applications. It features an internally fixed gain of 50 
(34 dB) and an output which automatically centers itself at 
one-half of the supply voltage. A unique input stage allows 
inputs to be ground referenced or AC coupled as required. 
The output stage of the LM380 is protected with both short 
circuit current limiting and thermal shutdown circuitry. All of 
these internally provided features result in a minimum exter- 
nal parts count integrated circuit for audio applications. 
This paper describes the circuit operation of the LM380, its 
power handling capability, methods of volume and tone con- 
trol, distortion, and various application circuits such as a 
bridge amplifier, a power supply splitter, and a high input 
impedance audio amplifier. 

CIRCUIT DESCRIPTION 

Figure 1 shows a simplified circuit schematic of the LM380. 
The input stage is a PNP emitter-follower driving a PNP dif- 
ferential pair with a slave current-source load. The PNP 



input is chosen to reference the input to ground, thus en- 
abling the input transducer to be directly coupled. 
The output is biased to half the supply voltage by resistor 
ratio R1/R2. Negative DC feedback, through resistor R2, 
balances the differential stage with the output at half supply, 
since R 1 = 2R 2 (Figure 1). 

The second stage Is a common emitter voltage gain amplifi- 
er with a current-source load. Internal compensation is pro- 
vided by the pole-splitting capacitor C Pole-splitting com- 
pensation is used to preserve wide power bandwidth 
(100 kHz at 2W, 8Q). The output is a quasi-complementary 
pair emitter-follower. 

The amplifier gain is internally fixed to 34 dB or 50. This is 
accomplished by the internal feedback network R2-R3. The 
gain is twice that of the ratio R2/R3 due to the slave current- 
source which provides the full differential gain of the input 
stage. 



TABLE I. Electrical Characteristics (Note 1) 



Parameter 


Conditions 


Min 


Typ 


Max 


Units 


Power Output (rms) 


8fl loads, 3% T.H.D. (Notes 3,4) 


2.5 






Wrms 


Gain 




40 


50 


60 


V/V 


Output Voltage Swing 


8il load 




14 




Vp. p 


Input Resistance 






150k 




a 


Total Harmonic Distortion 


P = 1W,(Notes4&5) 




0.2 




% 


Power Supply Rejection 


Cbypass = 5u,F, t = 120 Hz 
(Note 2) 




38 




dB 


Supply Voltage Range 




8 




22 


V 


Bandwidth 


P = 2W, R L = en 




100k 




Hz 


Quiescent Output Voltage 




8 


9 


10 


V 


Quiescent Supply Current 






7 


25 


mA 


Short Circuit Current 






1.3 




A 



Note 1: Vs = 18V; T^ = 25°C unless otherwise specified. 

Note 2: Rejection ratio referred to output. 

Note 3: With device Pins 3, 4, 5, 10, 1 1, 12 soldered into a 1 /i«" epoxy glass board with 2 ounce copper foil with a minimum surface of six square inches. 

Note 4: If oscillation exists under some load conditions, add a 2.7(1 resistor and 0.1 p,F series network from Pin 6 to ground. 

Note 5: Cb ypa ss = °-47 /i.F on Pin 1 . 

Note 6: Pins 3, 4, 5, 10, 1 1, 12 at 50°C derates 25°C/W above 50°C case. 



150 



OV s (14) 




> 

Z 
■ 



FIGURE 1 



GENERAL OPERATING CHARACTERISTICS 

The output current of the LM380 is rated at 1 .3A peak. The 
14 pin dual-in-line package is rated at 35°C/W when sol- 
dered into a printed circuit board with 6 square inches of 2 
ounce copper foil (Figure 2). Since the device junction tem- 
perature is limited to 1 50°C via the thermal shutdown circuit- 
ry, the package will support 3 watts dissipation at 50°C am- 
bient or 3.7 watts at 25°C ambient. 
Figure 2 shows the maximum package dissipation versus 
ambient temperature for various amounts of heat sinking. 

12.0 



a 

B 4.0 

> 

° 2.0 



10 20 30 40 50 60 70 80 

T A - AMBIENT TEMPERATURE (°C) TL/H/7380-2 

FIGURE 2. Device Dissipation vs Ambient Temperature 

Figures 3a, b, and c show device dissipation versus output 
power for various supply voltages and loads. 

3.5 




I COPPER FOIL PC BOABO 3TC/W 
I. COPPER FOIL PC. BOARD WZI* 

I. COPKfl FOIL P.C. SOARO 
T3*C/W 










3 


XDIST. 
LEVEL 
















\ 






Vs 








/ 




oc 
cc 
-=> 
u 

< 




14V 
12V 
10V 










t 
10% 




/ 








' > 










/ 


UVEL 


9V 




■V 








x: 
















X 





0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 

OUTPUT POWER WATTS) TL/H/7380-3 

FIGURE 3a. Device Dissipation 
vs Output Power — 4ft Load 




0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.S 5.0 
OUTPUT POWER (WATTS) 

FIGURE 3b. Device Dissipation 
vs Output Power — 8ft Load 



TL/H/7380-4 




0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 
OUTPUT POWER (WATTS) 

FIGURE 3c. Device Dissipation 
vs Output Power — 16ft Load 



TL/H/7380-5 



151 



<0 



The maximum device dissipation is obtained from Figure 2 
for the heat sink and ambient temperature conditions under 
which the device will be operating. With this maximum al- 
lowed dissipation, Figures 3a, b and c show the maximum 
power supply allowed (to stay within dissipation limits) and 
the output power delivered into 4, 8 or 16fl loads. The three 
percent total-harmonic distortion line is approximately the 
on-set of clipping. 

2.0 
| 1.8 

£ 1.6 

o 

te I-* 

5 1.2 

o 10 



100 200 S00 Ik 2k Sk 10k 20k 
FREQUENCY (Hz) 

TL/H/7380-6 

FIGURE 4. Total Harmonic Distortion vs Frequency 

Figure 4 shows total harmonic distortion versus frequency 
for various output levels, while Figure 5 shows the power 
bandwidth of the LM380. 













"l 


=8n 












1SV 






-ST7 


VER" 


17" t 


EAT 


ilNK- 
































— 1 

/ 


OOmV 


i 


2W- 

/ 














/ 




H 


y 




IMP 





































i i i i i 
V C c = 18V 




















































f 


































L - " 

1 1 




























PHASE '■ 

II 1 




























1 t 1 

r l = 8n ^ 

'out = 2W 































































60° 

120° 

180"! 

240°' 

300° 

360° 



10 100 Ik 10k 100k 1M 10M 
FREQUENCY (Hz) 

TL/H/7380-7 

FIGURE 5. Output Voltage Gain vs Frequency 

Power supply decoupling is achieved through the AC divider 
formed by Ri (Figure 1) and an external bypass capacitor. 
Resistor R-| is split into two 25 kCl halves providing a high 



504B 







































Sjif 


















S\ 


u 


! Or 
















*Aluf 
















HUP 












NO 


B 


rPAS 


CAP 


\l 


ITOR 












III 


I 




111 



,4048 

■Mil 



>20dS 

8: 



10 Hz 1MHz 1kHz 10 kHz 

FREQUENCY 

TL/H/7380-8 

FIGURE 6. Supply Decoupling vs Frequency 



source impedance for the integrator. Figure 6 shows supply 
decoupling versus frequency for various bypass capacitors. 

BIASING 

The simplified schematic of Figure 1 shows that the LM380 
is internally biased with the 150 kft resistance to ground. 
This enables input transducers which are referenced to 
ground to be direct-coupled to either the inverting or non-in- 
verting inputs of the amplifier. The unused input may be 
either: 1) left floating, 2) returned to ground through a resis- 
tor or capacitor or 3) shorted to ground. In most applications 
where the non-inverting input is used, the inverting input is 
left floating. When the inverting input is used and the non-in- 
verting input is left floating, the amplifier may be found to be 
sensitive to board layout since stray coupling to the floating 
input is positive feedback. This can be avoided by employ- 
ing one of three alternatives: 1) AC grounding the unused 
input with a small capacitor. This is preferred when using 
high source impedance transducer. 2) Returning the unused 
input to ground through a resistor. This is preferred when 
using moderate to low DC source impedance transducers 
and when output offset from half supply voltage is critical. 
The resistor is made equal to the resistance of the input 
transducer, thus maintaining balance in the input differential 
amplifier and minimizing output offset. 3) Shorting the un- 
used input to ground. This is used with low DC source im- 
pedance transducers or when output offset voltage is non- 
critical. 

OSCILLATION 

The normal power supply decoupling precautions should be 
taken when installing the LM380. If Vs is more than 2" to 3" 
from the power supply filter capacitor it should be decou- 
pled with a 0.1 juiF disc ceramic capacitor at the V$ terminal 
of the IC. 

The Re and Cc shown as dotted line components on Figure 
7 and throughout this paper suppresses a 5 to 10 MHz 




TL/H/7380-9 

•For Stability With High Current Loads 

FIGURE 7. Minimum Component Configuration 

small amplitude oscillation which can occur during the nega- 
tive swing into a load which draws high current. The oscilla- 
tion is of course at too high of a frequency to pass through a 
speaker, but it should be guarded against when operating in 
an RF sensitive environment. 



152 



APPLICATIONS 

With the internal biasing and compensation of the LM380, 
the simplest and most basic circuit configuration requires 
only an output coupling capacitor as seen in Figure 7. 
An application of this basic configuration is the phonograph 
amplifier where the addition of volume and tone controls is 
required. Figure 8 shows the LM380 with a voltage divider 
volume control and high frequency roll-off tone control. 




TL/H/7380-10 

•For Stability with High Current Loads 

FIGURE 8. Phono Amp 
When maximum input impedance is required or the signal 
attenuation of the voltage divider volume control is undesir- 
able, a "common mode" volume control may be used as 
seen in Figure 9. 




TL/H/7380-11 
•For Stability with High Current Loads 

FIGURE 9. "Common Mode" Volume Control 

With this volume control the source loading impedance is 
only the input impedance of the amplifier when in the full- 
volume position. This reduces to one-half the amplifier input 
impedance at the zero volume position. Equation 1 de- 
scribes the output voltage as a function of the potentiome- 
ter setting. 

/ 150 x 103 \ 

VoUT = 50V IN ^- kiRv+15ox10 3J o ^^ (1) 




_ _ . • . .• .. ~ . ^ TL/H/7380-12 

•For Stability with High Current Loads 
••Audio Tape Potentiometer (10% of Rt at 50% Rotation) 

FIGURE 10. "Common Mode" Volume and Tone Control 

This "common mode" volume control can be combined with 
a "common mode" tone control as seen in Figure 10. 



This circuit has a distinct advantage over the circuit of Fig- 
ure 7 when transducers of high source impedance are used, 
in that, the full input impedance of the amplifier is realized. It 
also has an advantage with transducers of low source im- 
pedance since the signal attenuation of the input voltage 
divider is eliminated. The transfer function of the circuit of 
Figure 10 is given by: 



Vqut . 

Vin ' 



50 



150k 



kiR T k 2 Rv + 



150k+- 



k 2 Ry 

j277fCl 



(2) 



kiRr + k 2 Rv + : 



j27TfCl , 



O^k^l 
0^k 2 ^1 



Figure 1 1 shows the response of the circuit of Figure 10. 

50 




100 Hz 1kHz 10 kHz 100 kHz 
FREQUENCY 

TL/H/7380-13 

FIGURE 11. Tone Control Response 

Most phonograph applications require frequency response 
shaping to provide the RIAA equalization characteristic 
When recording, the low frequencies are attenuated to pre- 
vent large undulations from destroying the record groove 
walls. (Bass tones have higher energy content than high 
frequency tones). Conversely, the high frequencies are em- 
phasized to achieve greater signal-to-noise ratio. Therefore, 
when played back the phono amplifier should have the in- 
verse frequency response as shown in Figure 12. 

30 
20 







., j . 




























"*> 


"I 








































3 — 














/ 








S 




y\ 























































































10 Hi 100 Hz IkHi 10 kHz 100 kHz 
FREQUENCY 

TL/H/7380-14 

FIGURE 12. RIAA Playback Equalization 

This response is achieved with the circuit of Figure 13. 
The mid-band gain, between frequencies f 2 and f3, Figure 
12, is established by the ratio of Ri to the input resistance 
of the amplifier (150 kn). 



153 



Mid-band Gain = 



Rj + 150 Ml 
150kft 



(3) 




TL/H/7380-15 
* For Stability with High Current Loads 

FIGURE 13. RIAA Phono Amplifier 
Capacitor C-| sets the corner frequency f 2 where 
R1 = Xci. 

Capacitor C2 establishes the corner frequency f3 where Xc2 
equals the impedance of the inverting input. This is normally 
1 50 Ml. However, in the circuit of Figure 13 negative feed- 
back reduces the impedance at the inverting input as: 

Where: 

Z = impedance at node 6 without external feedback 
(150 Ml) 
= gain without external feedback (50) 

Ao-A 



Ao 




feedback transfer function /3 



A Q A 



A = closed loop gain with external feedback. 
Therefore 

1 1 



C 2 = 



**(t^) -(^) 



(6) 



+ A /3, 

BRIDGE AMPLIFIER 

Where more power is desired than can be provided with one 
amplifier, two amps may be used in the bridge configuration 
shown in Figure 14. 



_ — 




, * 




s(14 14p^+ 

1310 J^S«-I \-q!^ LM3M 


12 


'If 

2.SM ] 




— C2 
■*»51pF 


LI 


t 












- L - 'h- " L - 

'T* 0.1 at 'T N 

■ CflVPASS CgvpASSI 

















TL/H/7380-16 
•For Stability with High Current Loads 

FIGURE 14. Bridge Configuration 

This provides twice the voltage swing across the load for a 
given supply, thereby, increasing the power capability by a 



factor of four over the single amplifier. However, in most 
cases the package dissipation will be the first parameter 
limiting power delivered to the load. When this is the case, 
the power capability of the bridge will be only twice that of 




t.o 2.0 3.0 4.0 
OUTPUT POWER (WATTS) 



TL/H/7380-17 



FIGURE 15A. 811 Load 

the single amplifier. Figures 15A and B show output power 
versus device package dissipation for both 8 and 1 6fl loads 
in the bridge configuration. The 3% and 10% harmonic 




OUTPUT POWER (WATTS) IBS! LOAD 



FIGURE 15B. 1611 Load 



TL/H/7380-18 



distortion contours double back due to the thermal limiting 
of the LM380. Different amounts of heat sinking will change 
the point at which the distortion contours bend. 
The quiescent output voltage of the LM380 is specified at 9 
± 1 volts with an 18 volt supply. Therefore, under the worst 
case condition, it is possible to have two volts DC across 
the load. 




TL/H/7380-19 
•For Stability with High Current Loads 

FIGURE 16. Quiescent Balance Control 

With an 8fl speaker this 0.25A which may be excessive. 
Three alternatives are available; 1) care can be taken to 
match the quiescent voltages, 2) a non-polar capacitor may 
be placed in series with the load, 3) the offset balance con- 
trol of Figure 16 may be used. 



154 







TL/H/7380-20 



•For Stability with High Current Loads 



FIGURE 17. Voltage Divider Input 




1380 ^♦Ht— CV^. 

/T ir n)-Hh 

=T Cc'-x.- | REMOTE I I 



TL/H/7380-21 



•For Stability with High Current Loads 



FIGURE 18. Intercom 



The circuits of Figures 14 and 16 employ the "common 
mode" volume control as shown before. However, any of 
the various input connection schemes discussed previously 
may be used. Figure 17 shows the bridge configuration with 
the voltage divider input. As discussed in the "Biasing" 
section the undriven input may be AC or DC grounded. If Vs 
is an appreciable distance from the power supply (>3") fil- 
ter capacitor it should be decoupled with a 1 jaF tantaulum 
capacitor. 

INTERCOM 

The circuit of Figure 18 provides a minimum component in- 
tercom. With switch S-| in the talk position, the speaker of 
the master station acts as the microphone with the aid of 
step-up transformer T^ . 

A turns ratio of 25 and a device gain of 50 allows a maxi- 
mum loop gain of 1250. Ry provides a "common mode" 
volume control. Switching Si to the listen position reverses 
the role of the master and remote speakers. 

LOW COST DUAL SUPPLY 

The circuit shown in Figure 19 demonstrates a minimum 
parts count method of symmetrically splitting a supply volt- 
age. Unlike the normal R, C, and power zener diode tech- 




TL/H/7380-22 

FIGURE 19. Dual Supply 

nique the LM380 circuit does not require a high standby 
current and power dissipation to maintain regulation. 
With a 20 volt input voltage (±10 volt output) the circuit 
exhibits a change in output voltage of approximately 2% per 
100 mA of unbalanced load change. Any balanced load 
change will reflect only the regulation of the source voltage 
Vin- 

The theoretical plus and minus output tracking ability is 
100% since the device will provide an output voltage at 
one-half of the instantaneous supply voltage in the absence 
of a capacitor on the bypass terminal. The actual error in 



155 



tracking will be directly proportional to the unbalance in the 
quiescent output voltage. An optional potentiometer may be 
placed at pin 1 as shown in Figure 19 to null output offset. 
The unbalanced current output for the circuit of Figure 18 is 
limited by the power dissipation of the package. 
In the case of sustained unbalanced excess loads, the de- 
vice will go into thermal limiting as the temperature sensing 
circuit begins to function. For instantaneous high current 
loads or short circuits the device limits the output current to 
approximately 1.3 amperes until thermal shut-down takes 
over or until the fault is removed. 

HIGH INPUT IMPEDANCE CIRCUIT 

The junction FET isolation circuit shown in Figure 20 raises 
the input impedance to 22 MO for low frequency input sig- 
nals. The gate to drain capacitance (2 pF maximum for the 
KE4221 shown) of the FET limits the input impedance as 
frequency increases. 



V.nO 




VoOT 



TUH/7380-23 



FIGURE 20 



At 20 kHz the reactance of this capacitor is approximately 
-j4 Mft giving a net input impedance magnitude of 3.9 Mft. 
The values chosen for R-j, R 2 and C-\ provide an overall 
circuit gain of at least 45 for the complete range of parame- 
ters specified for the KE4221 . 

When using another FET device the relevant design equa- 
tions are as follows: 



A V = 



Ri 



R 1+ — 
9m 



(50) 



9m - 9m0 



0-S) 



Vgs = IdsRi 
Ids = Idss(i --^rf) 



(7) 
(8) 

(9) 
(10) 



The maximum value of R2 is determined by the product of 
the gate reverse leakage Iqss and R2. This voltage should 
be 1 to 1 00 times smaller than Vp. The output impedance 
of the FET source follower is: 



9m 



(11) 



so that the determining resistance for the interstage RC 
time constant is the input resistance of the LM380. 



BOOSTED GAIN USING POSITIVE FEEDBACK 

For applications requiring gains higher than the internally 
set gain of 50, it is possible to apply positive feedback 
around the LM380 for closed loopgains of up to 300. Figure 
21 shows a practical example of an LM380 in a gain of 200 
circuit. 




TL/H/7380-24 



FIGURE 21. Boosted Gain of 200 
Using Positive Feedback 

The equation describing the closed loop gain is: 

A V(o>) 



Avcl = 



1 _ A v(*>) 
R 2 



(12) 



where Ay( W ) is complex at high frequencies but is nominally 
the 40 to 60 specified on the data sheet for the pass band 
of the amplifier. If 1 + Ri/R 2 approaches the value of 
Av(c), the denominator of equation 1 2 approaches zero, the 
closed loop gain increases toward infinity, and the circuit 
oscillates. This is the reason for limiting the closed loop gain 
values to 300 or less. Figure 22 shows the loaded and un- 
loaded bode plot for the circuit shown in Figure 21. 

250 



t 150 



R 


1 ■ I0K 










f" 


L -Kl 




1 




, 


* 




) 






f 








\ 




1 








\ 





10 



10M 



100 Ik 10k 100k 1M 
FREQUENCY (Hz) - 

TL/H/7380-25 

FIGURE 22. Boosted Gain Bode Plot 

The 24 pF capacitor C 2 shown on Figure 21 was added to 
give an overdamped square wave response under full load 
conditions. It causes a high frequency roll-off of: 

(13) 



f 2 = 



27tR 2 C 2 

The circuit of Figure 21 will have a very long (1000 sec) turn 
on time if R|_ is not present, but only a 0.01 second turn on 
time with an 8ft load. 



156 



Micropower Circuits Using 
the LM4250 Programmable 
Op Amp 



National Semiconductor 
Application Note 71 
George Cleveland 




> 

Z 
■ 

-4 



INTRODUCTION 

The LM4250 is a highly versatile monolithic operational am- 
plifier. A single external programming resistor determines 
the quiescent power dissipation, input offset and bias cur- 
rents, slew rate, gain-bandwidth product, and input noise 
characteristics of the amplifier. Since the device is in effect 
a different op amp for each externally programmed set cur- 
rent, it is possible to use a single stock item for a variety of 
circuit functions in a system. 

This paper describes the circuit operation of the LM4250, 
various methods of biasing the device, frequency response 
considerations, and some circuit applications exercising the 
unique characteristics of the LM4250. 

CIRCUIT DESCRIPTION LM4250 

The LM4250 has two special features when compared with 
other monolithic operational amplifiers. One is the ability to 
externally set the bias current levels of the amplifiers, and 
the other is the use of PNP transistors as the differential 
input pair. 



Referring to Figure 1, Qi and Q2 are high current gain later- 
al PNPs connected as a differential pair. R1 and R2 provide 
emitter degeneration for greater stability at high bias cur- 
rents. Q3 and Q4 are used as active loads for Q-\ and Q2 to 
provide nigh gain and also form a current inverter to provide 
the maximum drive for the single ended output into Q5. Q5 is 
an emitter follower which prevents loading of the input stage 
by the succeeding amplifier stage. 
One advantage of this lateral PNP input stage is a common 
mode swing to within 200 m V of the negative supply. This 
feature is especially useful in single supply operation with 
signals referred to ground. Another advantage is the almost 
constant input bias current over a wide temperature range. 
The input resistance Rin is approximately equal to 2/3 (Rg 
+ r e ) where J3 is the current gain, r e is the emitter resist- 
ance of one of the input lateral PNPs, and Re is the resist- 
ance of one of the 1 kft emitter resistor. Using a DC beta 
of 100 and the normal temperature dependent expression 
for r e gives: 




FIGURE 1. LM4250 Schematic Diagram 



157 



2MH + 2 



kT 
qlB 



(D 



where \q is input bias current. At room temperature this for- 
mula becomes: 



RlN ~ 2 Mn + 



52 mV 
Ib 



(2) 



100 

so 















-T, 


= 25°C 






























li- 





























































































































































































































■OiA) 



FIGURE 2. Input Resistance vs Iset 

Figure 2 gives a typical plot of Rin vs l se t derived from the 
above equation. 

Continuing with the circuit description, Q6 level shifts down- 
ward to the base of Q& which is the second stage amplifier. 
Q8 is run as a common emitter amplifier with a current 
source load (Q12) to provide maximum gain. The output of 
Q$ drives the class B complementary output stage com- 
posed of Q15 and Q-is- 

The bias current levels in the LM4250 are set by the amount 
of current (l se t) drawn out of Pin 8. The constant current 
sources Q10, Q11. and Q12 are controlled by the amount of 
l se t current through the diode connected transistor Qg and 
resistor Rg. The constant collector current from Q10 biases 
the differential input stage. Therefore, the level Q10 is set at 
will control such amplifier characteristics as input bias cur- 
rent, input resistance, and amplifier slew rate. Current 
source Q-\ 1 biases Q5 and Q$. The current ratio between Q5 
and Q6 is controlled by constant current sink Q7. Current 
source C12 sets the currents in diodes Q13 and Q14 which 
bias the output stage to the verge of conduction thereby 
eliminating the dead zone in the class B output. Q12 also 
acts as the load for Qq and limits the drive current to Q15. 
The output current limiting is provided by Q16 and Q17 and 
their associated resistors R-| 6 and R17. When enough cur- 
rent is drawn from the output, Q16 turns on and limits the 
base drivB of Q15. Similarly Q17 turns on when the LM4250 
attempts to sink too much current, limiting the base drive of 
Q18 and therefore output current. Frequency compensation 
is provided by the 30 pF capacitor across the second stage 
amplifier, Qe, of the LM4250. This provides a 6 dB per oc- 
tave rolloff of the open loop gain. 

BIAS CURRENT SETTING PROCEDURE 

The single set resistor shown in Figure 3a offers the most 
straightfoi-ward method of biasing the LM4250. When the 
set resistor is connected from Pin 8 to ground the resistance 
value for a given set current is: 

Rset = — i < 3 > 

'SET 

The 0.5 volts shown in Equation 3 is the voltage drop of the 

master bias current diode connected transistor on the inte- 



grated circuit chip. In applications where the regulation of 
the V+ supply with respect to the V - supply (as in the case 
of tracking regulators) is better than the V+ supply with 
respect to ground the set resistor should be connected from 
Pin 8 to V-. Rset 's then: 

Rset = v+ + |v-|-o.s m 

Iset 
The transistor and resistor scheme shown in Figure 3b al- 
lows one to switch the amplifier off without disturbing the 
main V+ and V - power supply connections. Attaching C-\ 
across the circuit prevents any switching transient from ap- 
pearing at the amplifier output. The dual scheme shown in 
Figure 3c has a constant set current flowing through Rsi 
and a variable current through Rs2- Transistor Q2 acts as an 
emitter follower current sink whose value depends on the 
control voltage V c on the base. This circuit provides a meth- 



T0PIN8 
Q 



Rset 



6 

V-OR 
GROUND 

TL/H/7382-3 

3a 



TO PIN 8 




3b 





TL/H/7382-5 TL/H/7382-6 

3c 3d 

FIGURE 3. Biasing Schemes 

od of varying the amplifier's characteristics over a limited 
range while the amplifier is in operation. The FET circuit 
shown in Figure 3d covers the full range of set currents in 
response to as little as a 0.5V gate potential change on a 
low pinch-off voltage FET such as the 2N3687. The limit 
resistor prevents excessive current flow out of the LM4250 
when the FET is fully turned on. 

FREQUENCY RESPONSE OF A 
PROGRAMMABLE OP AMP 

This section provides a method of determining the sine and 
step voltage response of a programmable op amp. Both the 
sine and step voltage responses of an amplifier are modified 
when the rate of change of the output voltage reaches the 
slew rate limit of the amplifier. The following analysis devel- 



158 



ops the Bode plot as well as the small signal and slew rate 
limited responses of an amplifier to these two basic catego- 
ries of waveforms. 

SMALL SIGNAL SINE WAVE RESPONSE 

The key to constructing the Bode plot for a programmable 
op amp is to find the gain bandwidth product, GBWP, for a 
given set current. Quiescent power drain, input bias current, 
or slew rate considerations usually dictate the desired set 
current. The data sheet curve relating GBWP to set current 
provides the value of GBWP which when divided by one 
yields the unity gain crossover of f u . Assuming a set current 
of 6 /xA gives a GBWP of 200,000 Hz and therefore an f u of 
200 kHz for the example shown in Figure 4. Since the de- 
vice has a single dominant pole, the rolloff slope is -20 dB 
of gain per decade of frequency (-6 dB/octave). The dot- 
ted line shown on Figure 4 has this slope and passes 



Iset = «mA I 
GBWP - 200,000 Hi 




100 Hz 1kHz 10 kHz 100 kHz 1MHz 



FIGURE 4. Bode Plot 



through the 200 kHz f u point. Arbitrarily choosing an invert- 
ing amplifier with a closed loop gain magnitude of 50 deter- 
mines the height of the 34 dB horizontal line shown in Fig- 
ure 4. Graphically finding the intersection of the sloped line 
and the horizontal line or mathematically dividing GBWP by 
50 determines the 3 dB down frequency of 4 kHz for the 
closed loop response of this amplifier configuration. There- 
fore, the amplifier will now apply a gain of - 50 to all small 
signal sine waves at frequencies up to 4 kHz. For frequen- 
cies above 4 kHz, the gain will be as shown on the sloped 
portion of the Bode plot. 

SMALL SIGNAL STEP INPUT RESPONSE 

The amplifier's response to a positive step voltage change 
at the input will be an exponentially rising waveform whose 
rise time is a function of the closed loop 3 dB down band- 
width of the amplifier. The amplifier may be modeled as a 
single pole low pass filter followed by a gain of 50 wideband 
amplifier. From basic filter theory*, the 10% to 90% rise 
time of a single pole low pass filter is: 

f 3dB 
For the example shown in Figure 4 the 4 kHz 3 dB down 
frequency would give a rise time of 87.5 jus. 

SLEW RATE LIMITED LARGE SIGNAL RESPONSE 

The final consideration, which determines the upper speed 
limitation on the previous two types of signal responses, is 
the amplifier slew rate. The slew rate of an amplifier is the 
maximum rate of change of the output signal which the am- 
plifier is capable of delivering. In the case of sinosoidal sig- 
nals, the maximum rate of change occurs at the zero cross- 
ing and may be derived as follows: 

•See reference. 



V = V p Sin 27Tf t 
^2 = 2tt f V p cos 2tt f t 



dVp l 

dt It = o 



27rfV n 



S r = 2tt f max Vp 



(6) 
(7) 

(8) 
(9) 



where: 



S r = maximum - 



Vo = output voltage 
V p = peak output voltage 
dV 
dt 

The maximum sine wave frequency an amplifier with a given 
slew rate will sustain without causing the output to take on a 
triangular shape is therefore a function of the peak ampli- 
tude of the output and is expressed as: 
S r 



f MAX - 



27rV r 



(10) 



Figure 5 shows a quick reference graphical presentation of 
this formula with the area below any V pea |< line representing 
an undistorted small signal sine wave response for a given 
frequency and amplifier slew rate and the area above the 
Vpeak l' ne representing a distorted sine wave response due 
to slew rate limiting for a sine wave with the given V pea k. 

100k 



mi 




II! 
























: LIMITING 












■ — 
















VPEAK =1V 














■ VppiK = 2V — 






















Vp 


fcAK 




















jVffljfeL 
















yKnTri 










/peak = 16V . 




















X\ 1 Ml ' "" 

'] | )[| SMALI SIRNAI : 






















| I III RFSPflNSF 










1 III! I 


II 




Mil 



.0001 .001 .01 0.1 1.0 10 

REQUIRED MAXIMUM SLEW RATE "S r " (V/ps) 

TL/H/7382-8 

FIGURE 5. Frequency vs Slew Rate Limit vs Peak 
Output Voltage 

Large signal step voltage changes at the output will have a 
rise time as shown in equation 5 until a signal with a rate of 
output voltage change equal to the slew rate of the amplifier 
occurs. At this point the output will become a ramp function 
with a slope equal to S r . This action occurs when: 

c ^ V step 
Sr t r 



(11) 







I {^_|_[ LOW PASS 




















! £^} FILTER RESPONSE: 






: NWU^ 


Vstep = 32V _ 






'ffiflftf 


Ystep - '6V 






.jjLSUjavL 


l/ STE P = 8Vj= 


. "' 






IJJ 




















t- 




















.t 
















' 




r 














I 






i 














TE : 

Ul_ 












I LIMITINC 












J 


I 


I 


I 













.001 

.1 1.0 10 100 1000 10,000 

t, (usee) 10% TO 90% 

TL/H/7382-9 

FIGURE 6. Slew Rate vs Rise Time vs Step Voltage 



159 



Figure 6 graphically expresses this formula and shows the 
maximum amplitude of undistorted step voltage for a given 
slew rate and rise time. The area above each step voltage 
line represents the undistorted low pass filter type response 
mode of the amplifier. If the intersection of the rise time and 
slew rate values of a particular amplifier configuration falls 
below the expected step voltage amplitude line, the rise 
time will be determined by the slew rate of the amplifier. The 
rise time will then be equal to the amplitude of the step 
divided by the slew rate S r . 

FULL POWER BANDWIDTH 

The full power bandwidth often found on amplifier specifica- 
tion sheets is the range of frequencies from zero to the 
frequency found at the intersection on Figure 5 of the maxi- 
mum rated output voltage and the slew rate S r of the ampli- 
fier. Mathematically this is: 

ffullpower = i^^ (12) 

The full power bandwidth of a programmable amplifier such 
as the LM4250 varies with the master bias set current. 
The above analysis of sine wave and step voltage amplifier 
responses applies for all single dominant pole op amps 
such as the LM101A, LM1107, LM108A, LM112, LM118, 
and LM741 as well as the LM4250 programmable op amp. 

500 MANO-WATT X10 AMPLIFIER 

The X10 inverting amplifier shown in Figure 7 demonstrates 
the low power capability of the LM4250 at extremely low 
values of supply voltage and set current. The circuit draws 
260 nA from the +1.0V supply of which 50 nA flows 
through the 12 Mfl set resistor. The current into the -1.0V 
supply is only 210 nA since the set resistor is tied to ground 
rather than V - . Total quiescent power dissipation is: 

P D = (260 nA) (1V) + (210 nA) (1V) (13) 

P D = 470nW (14) 

The slew rate determined from the data sheet typical per- 
formance curve is 1 V/ms for a .05 /xA set current. Samples 
of actual values observed were 1.2 V/ms for the negative 
slew rate and 0.85 V/ms for the positive slew rate. This 
difference occurs due to the non-symmetry in the current 
sources used for charging and discharging the internal 30 
pF compensation capacitor. 



The 3 dB down (gain of -7.07) frequency observed for this 
configuration was approximately 300 Hz which agrees fairly 
closely with the 3.5 kHz GBWP divided by 10 taken from an 
extrapolation of the data sheet typical GBWP versus set 
current curve. 

Peak-to-peak output voltage swing into a 100 kfl load is 
0.7V or ± 0.35V peak. An increase in supply voltage to 
± 1 .35V such as delivered by a pair of mercury cells directly 
increases the output swing by ± 0.35V to 1.4V peak-to- 
peak. Although this increases the power dissipation to ap- 
proximately 1 fiW per battery, a power drain of 1 5 ju.W or 
less will not affect the shelf life of a mercury cell. 



330K 



V,n O— VW-#- - 




TL/H/7382-10 

FIGURE 7. 500 nW x 10 Amplifier 

MICRO-POWER MONITOR WITH HIGH CURRENT 
SWITCH 

Figure 8 shows the combination of a micro-power compara- 
tor and a high current switch run from a separate supply. 
This circuit provides a method of continuously monitoring an 
input voltage while dissipating only 1 00 /xW of power and 
still being capable of switching a 500 mA load if the input 
exceeds a given value. The reference voltage can be any 
value between +8.5V and -8.5V. With a minimum gain of 
approximately 100,000 the comparator can resolve input 
voltage differences down into the 0.2 mV region. 



VrefO 




i I < k < 0.5A 



TL/H/7382-11 



FIGURE 8. ju-Power Comparator with 
High Current Switch 



160 



The bias current for the LM4250 shown in Figure 8 is set at 
0.44 jliA by the 200 MO R se t resistor. This results in a total 
comparator power drain of 100 ju,W and a slew rate of ap- 
proximately 1 1 V/ms in the positive direction and 12.8 V/ms 
in the negative direction. Potentiometer R-| provides input 
offset nulling capability for high accuracy applications. 
When the input voltage is less than the reference voltage, 
the output of the LM4250 is at approximately -9.5V caus- 
ing diode D-i to conduct. The gate of Qi is held at -8.8V by 
the voltage developed across R3. With a large negative volt- 
age on the gate of Q-\ it turns off and removes the base 
drive from Q2. This results in a high voltage or open switch 
condition at the collector of C^- When the input voltage ex- 
ceeds the reference voltage, the LM4250 output goes to 
+ 9.5V causing D1 to be reverse biased. Q-\ turns on as 
does Qz, and the collector of Q2 drops to approximately 1V 
while sinking the 500 mA of load current. 
The load denoted as Z(_ can be resistor, relay coil, or indica- 
tor lamp as required; but the load current should not exceed 
500 mA. For V+ values of less than 15V and l|_ values of 
less than 25 mA both Q 2 and R2 may be omitted. With only 
the 2N4860 JFET as an output device the circuit is still ca- 
pable of driving most common types of indicator lamps. 

IC METER AMPLIFIER RUNS ON TWO FLASHLIGHT 
BATTERIES 

Meter amplifiers normally require one or two 9V transistor 
batteries. Due to the heavy current drain on these supplies, 
the meters must be switched to the OFF position when not 
in use. The meter circuit described here operates on two 
1 .5V flashlight batteries and has a quiescent power drain so 
low that no ON-OFF switch is needed. A pair of Eveready 
No. 950 "D" cells will serve for a minimum of one year 
without replacement. As a DC ammeter, the circuit will pro- 
vide current ranges as low as 1 00 nA full-scale. 
The basic meter amplifier circuit shown in Figure 9 is a cur- 
rent-to-voltage converter. Negative feedback around the 
amplifier insures that currents l|\ and If are always equal, 
and the high gain of the op amp insures that the input volt- 
age between Pins 2 and 3 is in the microvolt region. Output 




-1.5V 

TL/H/7382-12 

FIGURE 9. Basic Meter Amplifier 

voltage V is therefore equal to -IfRf. Considering the 
± 1 .5V sources ( ± 1 .2V end-of-life) a practical value of V 
for full scale meter deflection is 300 mV. With the master 
bias-current setting resistor (R s ) set at 10 Mft, the total qui- 
escent current drain of the circuit is 0.6 /xA for a total power 
supply drain of 1 .8 jxW. The input bias current, required by 
the amplifier at this low level of quiescent current, is in the 
range of 600 pA. 



THE COMPLETE NANOAMMETER 

The complete meter amplifier shown in Figure 10 is a differ- 
ential current-to-voltage converter with input protection, ze- 
roing and full scale adjust provisions, and input resistor bal- 
ancing for minimum offset voltage. Resistor R'f (equal in 
value to Rf for measurements of less than 1 ju,A) insures 
that the input bias currents for the two input terminals of the 
amplifier do not contribute significantly to an output error 
voltage. The output voltage V for the differential current-to- 
voltage converter is equal to -2 IfRf since the floating input 
current l tN must flow through R f and R'f. R'f may be omitted 




TL/H/7382-13 



+1.5V C* 



B1 ~ isw 



_t4 



POWER 
SUPPLY 



- ■» "~ 1.5V 

-1.5V O ' 

TL/H/7382-14 

FIGURE 10. Complete Meter Amplifier 

Resistance Values for 
DC Nano and Micro Ammeter 



I FULL SCALE 


Rf[n] 


R 'f [n] 


100nA 


1.5M 


1.5M 


500 nA 


300k 


300k 


1 p,A 


300k 





5 jaA 


60k 





10jmA 


30k 





50/xA 


6k 





IOOjuA 


3k 






for Rf values of 500 kft or less, since a resistance of this 
value contributes an error of less than 0.1% in output volt- 
age. Potentiometer Rg provides an electrical meter zero by 
forcing the input offset voltage V os to zero. Full scale meter 
deflection is set by R1. Both R-| and R2 only need to be set 
once for each op amp and meter combination. For a 50 
microamp 2 kft meter movement, R1 should be about 4 kft 
to give full scale meter deflection in response to a 300 mV 
output voltage. Diodes D1 and D2 provide full input protec- 
tion for overcurrents up to 75 mA. 

With an Rf resistor value of 1.5M the circuit in Figure 10 
becomes a nanommeter with a full scale reading capability 



161 



of 1 00 nA. Reducing Rf to 3 kfi in steps, as shown in Figure 
10 increases the full scale deflection to 100 ju,A, the maxi- 
mum for this circuit configuration. The voltage drop across 
the two input terminals is equal to the output voltage V 
divided by the open loop gain. Assuming an open loop gain 
of 10,000 gives an input voltage drop of 30 ju.V or less. 

CIRCUIT FOR HIGHER CURRENT READINGS 

For DC current readings higher than 100 jxA, the inverting 
amplifier configuration shown in Figure 1 1 provides the re- 
quired gain. Resistor Ra develops a voltage drop in re- 
sponse to input current l/y. This voltage is amplified by a 
factor equal to the ratio of Rf/Re- Rb must be sufficiently 
larger than Ra, so as not to load the input signal. Figure 1 1 
also shows the proper values of Ra, Rb and Rf for full scale 
meter deflections of from 1 mA to 10A. 

Resistance Values for DC Ammeter 



I FULL SCALE 


R A [n] 


H B [n] 


Rf[fi] 


1 mA 


3.0 


3k 


300k 


10 mA 


.3 


3k 


300k 


100 mA 


.3 


30k 


300k 


1A 


.03 


30k 


300k 


10A 


.03 


30k 


30k 



A 10 mV TO 100V FULL-SCALE VOLTMETER 

A resistor inserted in series with one of the input leads of 
the basic meter amplifier converts it to a wide range voltme- 
ter circuit, as shown in Figure 12. This inverting amplifier has 
a gain varying from -30 for the 10 mV full scale range to 
-0.003 for the 100V full scale range. Figure 12 also lists 
the proper values of R v , Rf, and R'f for each range. Diodes 
Di and D2 provide complete amplifier protection for input 
overvoltages as high as 500V on the 10 mV range, but if 
overvoltages of this magnitude are expected under continu- 
ous operation, the power rating of R v should be adjusted 
accordingly. 

Resistance Values for a DC Voltmeter 



V FULL SCALE 


R v tft] 


Rf[n] 


R'f [a] 


10 mV 


100k 


1.5M 


1.5M 


100 mV 


1M 


1.5M 


1.5M 


1V 


10M 


1.M 


1.5M 


10V 


10M 


300k 





100V 


10M 


30k 








TL/H/7382-15 



FIGURE 11. Ammeter 



VOLTMETER 

FIGURE 12. Voltmeter 



TL/H/7382-16 



162 



va 




> 

I 



JLJl 



TL/H/7382-17 



FIGURE 13. Pulse Generator 



LOW FREQUENCY PULSE GENERATOR USING A 
SINGLE +5V SUPPLY 

The variable frequency pulse generator shown in Figure 13 
provides an example of the LM4250 operated from a single 
supply. The circuit is a buffered output free running multivi- 
brator with a constant width output pulse occurring with a 
frequency determined by potentiometer R2. 
The LM4250 acts as a comparator for the voltages found at 
the upper plate of capacitor C1 and at the reference point 
denoted as V r on Figure 13. Capacitor C1 charges and dis- 
charges with a peak-to-peak amplitude of approximately 1 V 
determined by the shift in reference voltage V r at Pin 3 of 
the op amp. The charge path of C1 is from the amplifier 
output, which is at its maximum positive voltage Vhiqh (ap- 
proximately V+ -0.5V), through R1 and through the poten- 
tiometer R2. Diode D1 is reverse biased during the charge 
period. When C1 charges to the V r value determined by the 
net result of Vhigh through resistor R5 and V+ through the 
voltage divider made up of resistors R3 and R4 the amplifier 
swings to its lower limit of approximately 0.5V causing C-\ to 
begin discharging. The discharge path is through the for- 
ward biased diode D-|, through resistor R-|, and into Pin 6 of 
the op amp. Since the impedance in the discharge path 
does not vary for R2 settings of from 3 kil to 5 Mil, the 
output pulse maintains a constant pulse width of 41 jus 
±1.5 jxs over this range of potentiometer settings. Figure 
14 shows the output pulse frequency variation from 6 kHz 
down to 360 Hz as R2 places from 100 kfl up to 5 Mfl of 
additional resistance in the charge path of C-|. Setting R2 to 
zero ohms will short out diode D1 and cause a symmetrical 
square wave output at a frequency of 1 kHz. Increasing the 
value of C-\ will lower the range of frequencies available in 
response to the R2 variation shown on Figure 14. Electrolyt- 
ic capacitors may be used for the larger values of C-\ since it 
has only positive voltages applied to it. 



The output buffer Qt presents a constant load to the op 
amp output thereby preventing frequency variations caused 
by Vhigh and Vlow voltages changing as a function of load 
current. The output of Q1 will interface directly with a stan- 
dard TTL or DTL logic device. Reversing diode D1 will invert 
the polarity of the generator output providing a series of 
negative going pulses dropping from + 5V to the saturation 
voltage of Q-). 





































































































■s 














> 

£ t.000 
























































oc 














"" 











































R 2 (iVs) 

TL/H/7382-18 

FIGURE 14. Pulse Frequency vs R2 

The change in output frequency as a function of supply volt- 
age is less than ±4% for a V+ change of from 4V to 10V. 
This stability of frequency versus supply voltage is due to 
the fact that the reference voltage V r and the drive voltage 
for the capacitor are both direct functions of V + . 
The power dissipation of the free running multivibrator is 
300 ju.W and the power dissipation of the buffer circuit is 
approximately 5.8 mW. 



163 



+1.SV 




O v 



Note 1: Quiescent Pq = 10 jnW 

Note 2: R2, R3, R4, R5, R6 and R7 are 1 % resistors 

Note 3: R1 1 and C1 are for DC and AC common mode rejection adjustments 



TL/H/7382-19 



FIGURE 15. x 100 Instrumentation Amplifier 



X100 INSTRUMENTATION AMPLIFIER 

The instrumentation amplifier circuit shown in Figure 15 has 
a full differential input center tapped to ground. With the 
bias current set at approximately 0.1 juA, the impedance 
looking into either V|n 1 or V|n 2 is 100 Mft with respect to 
ground, and the input bias current at either terminal is 0.2 
nA. The two non-inverting input stages Ai and A2 apply a 
gain of 10 to the input signal, and the differential output 
stage applies an additional gain of -10 for a net amplifier 
gain of - 1 00: 

V = -100(V, N1 -V| N2 ). (15) 

The entire circuit can run from two 1 .5V batteries connected 
directly (no power switch) to the V+ and V - terminals. With 
a total current drain of 2.8 ju,A the quiescent power dissipa- 
tion of the circuit is 8.4 fiW. This is low enough to have no 
significant effect on the shelf life of most batteries. 
Potentiometer R-n provides a means for matching the gains 
of A-| and A2 to achieve maximum DC common mode rejec- 
tion ratio CMRR. With R-n adjusted to its null point for DC 
common mode rejection the small AC CMRR trimmer ca- 
pacitor C1 will normally give an additional 10 to 20 dB of 
CMRR over the operating frequency range. Since C-\ actual- 
ly balances wiring capacitance rather than amplifier fre- 
quency characteristics, it may be necessary to attach it to 
Pin 2 of either A1 or A2 as required. Figure 16 shows the 
variation of CMRR (referred to the input) with frequency for 
this configuration. Since the circuit applies a gain of 1 00 or 
40 dB to an input signal, the actual observed rejection ratio 



100 

80 







I 
















CMRR 
















! I HI 












K 
























\ 


N 























100 



1,000 10,000 



FREQUENCY (Hz) 

TL/H/7382-20 

FIGURE 16. Ay and CMRR vs Frequency 

is the difference between the CMRR curve and Ay curve. 
For example, a 60 Hz common mode signal will be attenuat- 
ed by 67 dB minus 40 db or 27 dB for an actual rejection 
ratio of Vin/Vo equal to 22.4. 

The maximum peak-to-peak output signal into a 100 kft 
load resistor is approximately 1 .8V. With no input signal, the 
noise seen at the output is approximately 0.8 mvp^s or 
8 ju-Vrms referred to the input. When doing power dissipa- 
tion measurements on this circuit, it should be kept in mind 
that even a 1 Mil oscilloscope probe placed between 
+ 1 .5V and - 1 .5V will more than double the power drawn 
from the batteries. 



164 



5V REGULATOR FOR CMOS LOGIC CIRCUITS 

The ideal regulator for low power CMOS logic elements 
should dissipate essentially no power when the CMOS de- 
vices are running at low frequencies, but be capable of de- 
livering full output power on demand when the CMOS devic- 
es are running in the 0.1 MHz to 10 MHz region. With a 10V 
input voltage, the regulator shown in Figure 1 7 will dissipate 
350 ju,W in the stand-by mode but will deliver up to 50 mA of 
continuous load current when required. 
The circuit is basically a boosted output voltage-follower ref- 
erenced to a low current zener diode. The voltage divider 
consisting of R2 and R3 provides a 5V tap voltage from the 
6.5V reference diode to determine the regulator output. 
Since a standard 6.5V zener diode does not exhibit good 
regulation in the 2 ju,A to 60 /*A reverse current region, Q% 
must be a special device. An NPN transistor with its collec- 
tor and base terminals grounded and its emitter tied to the 
junction of R1 and R2 exhibits a well-controlled base emitter 
reverse breakdown voltage. A National Semiconductor pro- 
cess 25 small signal NPN transistor sorted to a 



2N registration such as 2N3252 has a BVebo at 10 J^A 
specified as 5.5V minimum, 6.5V typical, and 7.0V maxi- 
mum. Using a diode connected 2N3252 as a reference, the 
regulator output voltage changed 78 mV in response to an 
8V to 36V change in the input voltage. This test was done 
under both no load and full load conditions and represents a 
line regulation of better than 1 .6%. 
A load change from 1 jmA to 50 mA caused a 1 mV change 
in output voltage giving a load regulation value of 0.05%. 
When operating the regulator at load currents of less than 
25 mA, no heat sink is required for Q-|. For load currents in 
excess of 50 mA, Q1 should be replaced by a Darlington 
pair with the 2N3019 acting as a driver for a higher power 
device such as a 2N3054. 

REFERENCES 

Millman, J. and Halkias, C.C.: "Electronic Device and Cir- 
cuits," pp. 465-466, McGraw-Hill Book Company, New 
York, 1967. 



> 
Z 




GN0 C* 



•SEE TEXT 

FIGURE 17. 350 jj.W Quiescent Drain 5 Volt Regulator 



TL/H/7382-21 



165 



The LM3900: A New 
Current-Differencing Quad 
of ± Input Amplifiers 



National Semiconductor 
Application Note 72 




PREFACE 

With all the existing literature on "how to apply op amps" why should another application note be produced on this subject? 
There are two answers to this question; 1) the LM3900 operates in quite an unusual manner (compared to a conventional op 
amp) and therefore needs some explanation to familiarize a new user with this product, and 2) the standard op amp 
applications assume a split power supply (±15 Vqc) is available and our emphasis here is directed toward circuits for lower 
cost single power supply control systems. Some of these circuits are simply "re-biased" versions of conventional handbook 
circuits but many are new approaches which are made possible by some of the unique features of the LM3900. 

Table of Contents 



1.0 AN INTRODUCTION TO THE NEW "NORTON" 
AMPLIFIER 

1.1 Basic Gain Stage 

1.2 Obtaining a Non-inverting Input Function 

1 .3 The Complete Single-Supply Amplifier 

2.0 INTRODUCTION TO APPLICATIONS OF THE LM3900 

3.0 DESIGNING AC AMPLIFIERS 

3.1 Single Power Supply Biasing 

3.2 A Non-inverting Amplifier 

3.3 "N Vbe" Biasing 

3.4 Biasing Using a Negative Supply 

3.5 Obtaining High Input Impedance and High Gain 

3.6 An Amplifier with a DC Gain Control 

3.7 A Line-receiver Amplifier 

4.0 DESIGNING DC AMPLIFIERS 

4.1 Using Common-mode Biasing for V|n = Vqc 

4.2 Adding an Output Diode for Vo = Vrjc 

4.3 A DC Coupled Power Amplifier (l|_ ^ 3 Amps) 

4.4 Ground Referencing a Differential Voltage 

4.5 A Unity Gain Buffer Amplifier 

5.0 DESIGNING VOLTAGE REGULATORS 

5.1 Reducing the Input-output Voltage 

5.2 Providing High Input Voltage Protection 

5.3 High Input Voltage Protection and Low (Vin _ Vout) 

5.4 Reducing Input Voltage Dependence and Adding 
Short-Circuit Protection 

6.0 DESIGNING RC ACTIVE FILTERS 

6.1 Biasing the Amplifiers 

6.2 A High Pass Active Filter 

6.3 A Low Pass Active Filter 

6.4 A Single-amplifier Bandpass Active Filter 

6.5 A Two-amplifier Bandpass Active Filter 

6.6 A Three-amplifier Bandpass Active Filter 

6.7 Conclusions 

7.0 DESIGNING WAVEFORM GENERATORS 

7.1 Sinewave Oscillator 

7.2 Squarewave Generator 



7.0 DESIGNING WAVEFORM GENERATORS (Continued) 

7.3 Pulse Generator 

7.4 Triangle Waveform Generator 

7.5 Sawtooth Waveform Generator 

7.5.1 Generating a Very Slow Sawtooth Waveform 

7.6 Staircase Waveform Generators 

7.7 A Pulse Counter and a Voltage Variable 
Pulse Counter 

7.8 An Up-down Staircase Waveform Generator 

8.0 DESIGNING PHASE-LOCKED LOOPS AND VOLTAGE 
CONTROLLED OSCILLATORS 

8.1 Voltage Controlled Oscillators (VCO) 

8.2 Phase Comparator 

8.3 A Complete Phase-locked Loop 

8.4 Conclusions 

9.0 DESIGNING DIGITAL AND SWITCHING CIRCUITS 

9.1 An "OR" Gate 

9.2 An "AND" Gate 

9.3 A Bi-stable Multivibrator 

9.4 Trigger Flip Flops 

9.5 Monostable Multivibrators (One-shots) 

9.5.1 A Two-amplifier One-shot 

9.5.2 A Combination One-shot/Comparator Circuit 

9.5.3 A One-amplifier One-shot (Positive Pulse) 

9.5.4 A One-amplifier One-shot (Negative Pulse) 

9.6 Comparators 

9.6.1 A Comparator for Positive Input Voltages 

9.6.2 A Comparator for Negative Input Voltages 

9.6.3 A Power Comparator 

9.6.4 A More Precise Comparator 

9.7 Schmitt Triggers 

10.0 SOME SPECIAL CIRCUIT APPLICATIONS 

10.1 Current Sources and Sinks 

10.1.1 A Fixed Current Source 

10.1.2 A Voltage Variable Current Source 

10.1.3 A Fixed Current Sink 

10.1 .4 A Voltage Variable Current Sink 



166 





Table of Contents (Continued) 


10.0 SOME SPECIAL CIRCUIT 


10.0 SOME SPECIAL CIRCUIT 




APPLICATIONS (Continued) 


APPLICATIONS (Continued) 


10.2 Operation from ±15 Vqc Power Supplies 


10.8 Audio Mixer or Channel Selector 




10.2.1 An AC Amplifier Operating with ±15 Vrx 


10.9 A Low Frequency Mixer 




Power Supplies 


10.10 A Peak Detector 




10.2.2 A DC Amplifier Operating with ±15 Vqc 


10.11 Power Circuits 




Power Supplies 


10.11.1 Lamp and/or Relay Drivers (£30 mA) 


10.3 Tachometers 


10.11.2 Lamp and/or Relay Drivers (£300 mA) 




10.3.1 A Basic Tachometer 


10.11.3 Positive Feedback Oscillators 




10.3.2 Extending Vout (Minimum) to Ground 


10.12 High Voltage Operation 




10.3.3 A Frequency Doubling Tachometer 


10.12.1 A High Voltage Inverting Amplifier 


10.4 A Squaring Amplifier 


10.12.2 A High Voltage Non-inverting Amplifier 


10.5 A Differentiator 


10.12.3 A Line Operated Audio Amplifier 


10.6 A Difference Integrator 


10.13 Temperature Sensing 


10.7 A Low Drift Sample and Hold Circuit 


10.14 A "Programmable Unijunction" 




10.7.1 Reducing the "Effective" Input Biasing 
Current 


10.15 Adding a Differential Input Stage 




10.7.2 A Low Drift Ramp and Hold 






10.7.3 Sample-Hold and Compare with New +V|n 






List of Illustrations 


1 


Basic Gain Stage 




2 


Adding a PNP Transistor to the Basic Gain Stage 




3 


Adding a Current Mirror to Achieve a Non-inverting Input 




4 


The Amplifier Stage 




5 


Open-loop Gain Characteristics 




6 


Schematic Diagram of the LM3900 




7 


An Equivalent Circuit of a Standard IC Op Amp 




8 


An Equivalent Circuit of the "Norton" Amplifier 




9 


Applying the LM3900 Equivalent Circuit 




10 


Biasing Equivalent Circuit 




11 


AC Equivalent Circuit 




12 


Inverting AC Amplifier Using Single-supply Biasing 




13 


Non-inverting AC Amplifier Using Voltage Reference Biasing 




14 


Inverting AC Amplifier Using N Vbe Biasing 




15 


Negative Supply Biasing 




16 


A High Zin High Gain Inverting AC Amplifier 




17 


An Amplifier with a DC Gain Control 




18 


A Line-receiver Amplifier 




19 


A DC Amplifier Employing Common-mode Biasing 




20 


An Ideal Circuit Model of a DC Amplifier with Zero Input Voltage 


21 


A Non-inverting DC Amplifier with Zero Volts Output for Zero Volts Input 


22 


Voltage Transfer Function for a DC Amplifier with a Voltage Gain of 1 


23 


A DC Power Amplifier 




24 


Ground Referencing a Differential Input DC Voltage 




25 


A Network to Invert and to Ground Reference a Negative DC Differential Input Voltage 


26 


A Unity-gain DC Buffer Amplifier 




27 


Simple Voltage Regulators 




28 


Reducing (V iN - V ut) 




29 


High V|n Protection and Self-regulation 




30 


A High Vin Protected, Low (Vin - Vout) Regulator 





167 



LiSt Of Illustrations (Continued) 

31 Reducing V|n Dependence 

32 Adding Short-Circuit Current Limiting 

33 Biasing Considerations 

34 A High Pass Active Filter 

35 A Low Pass Active Filter 

36 Biasing the Low Pass Filter 

37 Biasing Equivalent Circuit 

38 A One Op amp Bandpass Filter 

39 A Two Op amp Bandpass Filter 

40 The "Bi-quad" RC Active Bandpass Filter 

41 A Sinewave Oscillator 

42 A Squarewave Oscillator 

43 A Pulse Generator 

44 A Triangle Waveform Generator 
4d Gated Sawtooth Generators 

46 Generating Very Slow Sawtooth Waveforms 

47 Pumping the Staircase Via Input Differentiator 

48 A Free Running Staircase Generator 

49 An Up-down Staircase Generator 

50 A Voltage Controlled Oscillator 

5 ' Adding Input Common-Mode Biasing Resistors 

52 Reducing Temperature Drift 

53 Improving Mark/Space Ratio 

54 Phase Comparator 

55 A Phase- Locked Loop 

56 An "OR" Gate 

57 An "AND" Gate 

58 A Large Fan-in "AND" Gate 

59 A Bi-Stable Multivibrator 

60 A Trigger Flip Flop 

61 A Two-amplifier Trigger Flip Flop 

62 A One-Shot Multivibrator 

63 A One-Shot Multivibrator with an Input Comparator 

64 A One-Amplifier One-Shot (Positive Output) 

65 A One-Amplifier One-Shot (Negative Output) 

66 An Inverting Voltage Comparator 

67 A Non-Inverting Low-voltage Comparator 

68 A Non-Inverting Power Comparator 

69 A More Precise Comparator 

70 Schmitt Triggers 

71 Fixed Current Sources 

72 A Voltage Controlled Current Source 

73 Fixed Current Sinks 

74 A Voltage Controlled Current Sink 

75 An AC Amplifier Operating with ±15 Vqc 

76 DC Biasing for ±15 Vqc Operation 

77 A DC Amplifier Operating with ±15 Vpc 

78 A Basic Tachometer 

79 Adding Biasing to Provide Vq = Vrjc 

80 A Frequency Doubling Tachometer 

81 A Squaring Amplifier with Hysteresis 

82 A Differentiator Circuit 

83 A Difference Integrator 

168 



List Of Illustrations (Continued) Aj 

84 Reducing Ib "Effective"to Zero 

85 A Low-Drift Ramp and Hold Circuit 

86 Sample-Hold and Compare with New +V|n 

87 Audio Mixing or Selection 

88 A Low Frequency Mixer 

89 A Peak Detector 

90 Sinking 20 to 30 mA Loads 

91 Boosting to 300 mA Loads 

92 Positive Feedback Power Oscillators 

93 A High Voltage Inverting Amplifier 

94 A High Voltage Non-Inverting Amplifier 

95 A Line Operated Audio Amplifier 

96 Temperature Sensing 

97 A "Programmable Unijunction" 

98 Adding a Differential Input Stage 



169 



The LM3900: A New Current-Differencing 
Quad of + Input Amplifiers 



1.0 An Introduction to the New 
"Norton" Amplifier 

The LM3900 represents a departure from conventional am- 
plifier designs. Instead of using a standard transistor differ- 
ential amplifier at the input, the non-inverting input function 
has been achieved by making use of a "current-mirror" to 
"mirror" the non-inverting input current about ground and 
then to extract this current from that which is entering the 
inverting input terminal. Whereas the conventional op amp 
differences input voltages, this amplifier differences input 
currents and therefore the name "Norton Amp" has been 
used to indicate this new type of operation. Many biasing 
advantages are realized when operating with only a single 
power supply voltage. The fact that currents can be passed 
between the input terminals allows some unusual applica- 
tions. If external, large valued input resistors are used (to 
convert from input voltages to input currents) most of the 
standard op amp applications can be realized. 
Many industrial electronic control systems are designed that 
operate off of only a single power supply voltage. The con- 
ventional integrated-circuit operational amplifier (IC op amp) 
is typically designed for split power supplies (±15 Vdc) and 
suffers from a poor output voltage swing and a rather large 
minimum common-mode input voltage range (approximately 
+ 2 Vqc) when used in a single power supply application. In 
addition, some of the performance characteristics of these 
op amps could be sacrificed — especially in favor of reduced 
costs. 

To meet the needs of the designers of low-cost, single-pow- 
er-supply control systems, a new internally compensated 
amplifier has been designed that operates over a power 
supply voltage range of +4 Vdc to 36 Vdc with small 
changes in performance characteristics and provides an 
output peak-to-peak voltage swing that is only 1 V less than 
the magnitude of the power supply voltage. Four of these 
amplifiers have been fabricated on a single chip and are 
provided in the standard 14-pin dual-in-line package. 
The cost, application and performance advantages of this 
new quad amplifier will guarantee it a place in many single 
power supply electronic systems. Many of the "housekeep- 
ing" applications which are now handled by standard IC op 
amps can also be handled by this "Norton" amplifier operat- 
ing off the existing ±15 Vqc power supplies. 

1.1 BASIC GAIN STAGE 

The gain stage is basically a single common-emitter amplifi- 
er. By making use of current source loads, a large voltage 
gain has been achieved which is very constant over tem- 
perature changes. The output voltage has a large dynamic 
range, from essentially ground to one Vg^ 'ess than the 
power supply voltage. The output stage is biased class A for 
small signals but converts to class B to increase the load 
current which can be "absorbed" by the amplifier under 
large signal conditions. Power supply current drain is essen- 
tially independent of the power supply voltage and ripple on 
the supply line is also rejected. A very small input biasing 
current allows high impedance feedback elements to be 
used and even lower "effective" input biasing currents can 
be realized by using one of the amplifiers to supply essen- 
tially all of the bias currents for the other amplifiers by mak- 
ing use of the "matching" which exists between the 4 ampli- 
fiers which are on the same IC chip (see Figure 84). 



The simplest inverting amplifier is the common-emitter 
stage. If a current source is used in place of a load resistor, 
a large open-loop gain can be obtained, even at low power- 
supply voltages. This basic stage (Figure 1) is used for the 
amplifier. 

v + 0- 




TL/H/7383-1 

FIGURE 1. Basic Gain Stage 

All of the voltage gain is provided by the gain transistor, Q2, 
and an output emitter-follower transistor, Q1, serves to iso- 
late the load impedance from the high impedance that ex- 
ists at the collector of the gain transistor, Q2. Closed-loop 
stability is guaranteed by an on-chip capacitor C = 3 pF, 
which provides the single dominant open-loop pole. The 
output emitter-follower is biased for class-A operation by the 
current source I2. 

This basic stage can provide an adequate open-loop volt- 
age gain (70 dB) and has the desired large output voltage 
swing capability. A disadvantage of this circuit is that the DC 
input current, Iin, is large; as it is essentially equal to the 
maximum output current, Iout. divided by 2 . For example, 
for an output current capability of 1 mA the input current 
would be at least 1 jaA (assuming /3 2 = 10 4 ). It would be 
desirable to further reduce this by adding an additional tran- 
sistor to achieve an overall /3 3 reduction. Unfortunately, if a 
transistor is added at the output (by making Q1 a Darlington 
pair) the peak-to-peak output voltage swing would be some- 
what reduced and if Q2 were made a Darlington pair the DC 
input voltage level would be undesirably doubled. 
To overcome these problems, a lateral PNP transistor has 
been added as shown in Figure 2. This connection neither 
reduces the output voltage swing nor raises the DC input 
voltage, but does provide the additional gain that was need- 
ed to reduce the input current. 




TL/H/7383-2 

FIGURE 2. Adding a PNP Transistor to the 
Basic Gain Stage 



170 



Notice that the collector of this PNP transistor, Q-|, is con- 
nected directly to the output terminal. This "bootstraps" the 
output impedance of Qi and therefore reduces the loading 
at the high-impedance collector of the gain transistor, Q 3 . 
In addition, the collector-base junction of the PNP transistor 
becomes forward biased under a large-signal negative out- 
put voltage swing condition. The design of this device has 
allowed Q-\ to convert to a vertical PNP transistor during this 
operating mode which causes the output to change from the 
class A bias to a class B output stage. This allows the ampli- 
fier to sink more current than that provided by the current 
source I2, (1 .3 mA) under large signal conditions. 

1.2 OBTAINING A NON-INVERTING INPUT FUNCTION 

The circuit of Figure 2 has only the inverting input. A general 
purpose amplifier requires two input terminals to obtain both 
an inverting and a non-inverting input. In conventional op 
amp designs, an input differential amplifier provides these 
required inputs. The output voltage then depends upon the 
difference (or error) between the two input voltages. An in- 
put common-mode voltage range specification exists and, 
basically, input voltages are compared. 
For circuit simplicity, and ease of application in single power 
supply systems, a non-inverting input can be provided by 
adding a standard IC "current-mirror" circuit directly across 
the inverting input terminal, as shown in Figure 3. 




TL/H/7383-3 

FIGURE 3. Adding a Current Mirror to Achieve a 
Non-inverting Input 

This operates in the current mode as now input currents are 
compared or differenced (this can be thought of as a Norton 
differential amplifier). There is essentially no input common- 
mode voltage range directly at the input terminals (as both 
inputs will bias at one diode drop above ground) but if the 
input voltages are converted to currents (by use of input 
resistors), there is then no limit to the common-mode input 
voltage range. This is especially useful in high-voltage com- 
parator applications. By making use of the input resistors, to 
convert input voltages to input currents, all of the standard 
op amp applications can be realized. Many additional appli- 
cations are easily achieved, especially when operating with 
only a single power supply voltage. This results from the 
built-in voltage biasing that exists at both inputs (each input 
biases at + Vbe) and additional resistors are not required to 



provide a suitable common-mode input DC biasing voltage 
level. Further, input summing can be performed at the rela- 
tively low impedance level of the input diode of the current- 
mirror circuit. 

1.3 THE COMPLETE SINGLE-SUPPLY AMPLIFIER 

The circuit schematic for a single amplifier stage is shown in 
Figure 4a. Due to the circuit simplicity, four of these amplifi- 
ers can be fabricated on a single chip. One common biasing 
circuit is used for all of the individual amplifiers. 
A new symbol for this "Norton" amplifier is shown in Figure 
4b. This is recommended to avoid using the standard op 
amp symbol as the basic operation is different. The current 
source symbol between the inputs implies this new current- 
mode of operation. In addition, it signifies that current is 





v„o— [<n 



fr -H£ 



TL/H/7383-4 



(a) Circuit Schematic 




O-* +, 

TL/H/7383-5 
(b) New "NORTON" Amplifier Symbol 

FIGURE 4. The Amplifier Stage 

removed from the (-) input terminal. Also, the current arrow 
on the ( + ) input lead is used to indicate that this functions 
as a current input. The use of this symbol is helpful in under- 
standing the operation of the application circuits and also in 
doing additional design work with the LM3900. 
The bias reference for the PNP current source, V p which 
biases Q1, is designed to cause the upper current source 
(200 jxA) to change with temperature to give first order com- 
pensation for the (i variations of the NPN output transistor, 
Q3. The bias reference for the NPN "pull-down" current 
sink, V n , (which biases Q7) is designed to stabilize this cur- 
rent (1 .3 mA) to reduce the variation when the temperature 
is changed. This provides a more constant pull-down capa- 
bility for the amplifier over the temperature range. The tran- 
sistor, Q4, provides the class B action which exists under 
large signal operating conditions. 



171 



The performance characteristics of each amplifier stage are 
summarized below: 

Power-supply voltage range 4 to 36 V D c or 

±2 to ±18V DC 
Bias current drain per amplifier 

stage 1 .3 mA DC 

Open loop: 

Voltage gain (R L = 10k) 70 dB 

Unity-gain frequency 2.5 MHz 

Phase margin 40° 

Input resistance 1 Mft 

Output resistance 8 kfi 

Output voltage swing (Vcc ~ 1) v pp 

Input bias current 30 nAoc 

Slew rate 0.5V/jxs 

As the bias currents are all derived from diode forward volt- 
age drops, there is only a small change in bias current mag- 
nitude as the power-supply voltage is varied. The open-loop 
gain changes only slightly over the complete power supply 
voltage range and is essentially independent of temperature 
changes. The open-loop frequency response is compared 
with the "741" op amp in Figure 5. The higher unity-gain 
crossover frequency is seen to provide an additional 10 dB 
of gain for all frequencies greater than 1 kHz. 

120 



1 


10P 


AMP 






























LM3900 
































Rl 


= 10 


tflFO 


l\ 








B0 


WAM 


PLIFIEfl 


s 1 







1 10 100 1k 10k 10k 1M 10M 
f - Frequency, (Hz) 

TL/H/7383-6 

FIGURE 5. Open-loop Gain Characteristics 

The complete schematic diagram of the LM3900 is shown in 
Figure 6. The one resistor, R5, establishes the power con- 
sumption of the circuit as it controls the conduction of tran- 
sistor Q28. The emitter current of Q28 is used to bias the 
NPN output class-A biasing current sources and the collec- 
tor current of Q28 is the reference for the PNP current 
source of each amplifier. 

The biasing circuit is initially "started" by Q20. Q30 and CR6- 
After start-up is achieved, Q30 goes OFF and the current 
flow through the reference diodes: CR5, CR7 and CRs, is 
dependent only on Vbe/(R6 + ^7)- This guarantees that 
the power supply current drain is essentially independent of 
the magnitude of the power supply voltage. 
The input clamp for negative voltages is provided by the 
multi-emitter NPN transistor Q21. One of the emitters of this 
transistor goes to each of the input terminals. The reference 
voltage for the base of Q21 is provided by Rq and R7 and is 
approximately Vbe/2. 



2.0 Introduction to Applications of 
the LM3900 

Like the standard IC op amp, the LM3900 has a wide range 
of applications. A new approach must be taken to design 
circuits with this "Norton" amplifier and the object of this 
note is to present a variety of useful circuits to indicate how 
conventional and unique new applications can be de- 
signed — especially when operating with only a single power 
supply voltage. 

To understand the operation of the LM3900 we will com- 
pare it with the more familiar standard IC op amp. When 
operating on a single power supply voltage, the minimum 
input common-mode voltage range of a standard op amp 
limits the smallest value of voltage which can be applied to 
both inputs and still have the amplifier respond to a differen- 
tial input signal. In addition, the output voltage will not swing 
completely from ground to the power supply voltage. The 
output voltage depends upon the difference between the 
input voltages and a bias current must be supplied to both 
inputs. A simplified diagram of a standard IC op amp operat- 
ing from a single power supply is shown in Figure 7. The (+ ) 
and (-) inputs go only to current sources and therefore are 
free to be biased or operated at any voltage values which 
are within the input common-mode voltage range. The cur- 
rent sources at the input terminals, lg + and lpj ~ , represent 
the bias currents which must be supplied to both of the input 
transistors of the op amp (base currents). The output circuit 
is modeled as an active voltage source which depends upon 
the open-loop gain of the amplifier, A v , and the difference 
which exists between the input voltages, (V+ - V - ). 
(-) 

INPUT O— 



\ 



INPUT O- 



V + 



G)'» + 



©MV + 



-O OUTPUT 



v-» 



TL/H/7383-8 

FIGURE 7. An Equivalent Circuit of a Standard 
IC Op Amp 

An equivalent circuit for the "Norton" amplifier is shown in 
Figure 8. The ( + ) and (-) inputs are both clamped by di- 
odes to force them to be one-diode drop above ground — al- 
ways! They are not free to move and the "input common- 
mode voltage range" directly at these input terminals is very 
small — a few hundred mV centered about 0.5 Vnc- This is 



INPUT C* 




O OUTPUT 



TL/H/7383-9 



FIGURE 8. An Equivalent Circuit of the 
"Norton" Amplifier 



172 



10 



■^fi 



^c 



^ 



w^-^iT" 



na 



HH" 



v/ - 



:^2 



"H5 



^ 






HH" 



\s/- 



■w 



V^ F 

H H" ( "V/ — i" 





\!i« — " 



M- 



6 -6 § 



w-^^" 




♦-wvhHI' 



► I * M ►H* 

W 



\!r" 



< ;== rv 



\f/^V/ 



HH" 



\^r 




173 



why external voltages must be first converted to currents 
(using resistors) before being applied to the inputs— and is 
the basis for the current-mode (or Norton) type of operation. 
With external input resistors— there is no limit to the "input 
common-mode voltage range". The diode shown across the 
( + ) input actually exists as a diode in the circuit and the 
diode across the (-) input is used to model the base-emit- 
ter junction of the transistor which exists at this input. 
Only the (-) input must be supplied with a DC biasing cur- 
rent, l B . The (+) input couples only to the (-) input and 
then to extract from this (-) input terminal the same current 
(A|, the mirror gain, is approximately equal to 1) which is 
entered (by the external circuitry) into the ( + ) input terminal. 
This operation is described as a "current-mirror" as the cur- 
rent entering the ( + ) input is "mirrored" or "reflected" 
about ground and is then extracted from the (-) input. 
There is a maximum or near saturation value of current 
which the "mirror" at the (+) input can handle. This is listed 
on the data sheet as "maximum mirror current" and ranges 
from approximately 6 mA at 25°C to 3.8 mA at 70°C. 
This fact that the ( + ) input current modulates or affects the 
(-) input current causes this amplifier to pass currents be- 
tween the input terminals and is the basis for many new 
application circuits — especially when operating with only a 
single power supply voltage. 

The output is modeled as an active voltage source which 
also depends upon the open-loop voltage gain, A v , but only 
the (-) input voltage, V - , (not the differential input volt- 
age). Finally, the output voltage of the LM3900 can swing 
from essentially ground (+90 mV) to within one Vbe of the 
power supply voltage. 

As an example of the use of the equivalent circuit of the 
LM3900, the AC coupled inverting amplifier of Figure 9a will 



be analyzed. Figure 9b shows the complete equivalent cir- 
cuit which, for convenience, can be separated into a biasing 
equivalent circuit {Figure 10) and an AC equivalent circuit 
(Figure 11). From the biasing model of Figure 10 we find the 
output quiescent voltage, Vo, is: 

V = V D - + (I B + l+)R 2> 



and 



where 



and 



1 + 



V+ - V D ^ 
R 3 



(D 



(2) 



V D + = V D - = 0.5V DC 
l B = INPUT bias current (30 nA) 



V+ = Power supply voltage, 
If (2) is substituted into (1) 

V+ -V D 



Vo 



= V D " + ( 



Ib + 



R3 



*-) 



R 2 



(3) 



which is an exact expression for Vo- 
As the second term usually dominates (Vo > Vo - ) and l + 
> l B and V+ > Vq+ we can simplify (3) to provide a more 
useful design relationship 



v °-^ v+ - 



Using (4), if R 3 = 2R 2 we find 



V+ 



u 2R 2 2 



(4) 



(5) 



which shows that the output is easily biased to one-half of 
the power supply voltage by using V+ as a biasing refer- 
ence at the (+) input. 




(a) A Typical Biased Amplifier 



TL/H/7383-10 



R3 (+) 

v + C-WV-O- 



R2 (i + + i B ) 

-vw 



VW I 

» » I 6— — o 



M 



TL/H/7383-12 

FIGURE 10. Biasing Equivalent Circuit 



i— VW- 



- R3 (+) 

v + 0-VW— O 



VN/v i 

Co 

. T T A A~^h- 



vv— u— — I 

V ° + X O a,i+ 




IH. 






TL/H/7383-13 



FIGURE 1 1. AC Equivalent Circuit 



TL/H/7383-11 
(b) Using the LM3900 Equivalent Circuit 

FIGURE 9. Applying the LM3900 Equivalent Circuit 



174 



The AC equivalent circuit of Figure 1 1 is the same as that 
which would result if a standard IC op amp were used with 
the ( + ) input grounded. The closed-loop voltage gain A VCL , 
is given by: 

Vg Rj 



V|N 



if A v (open-loop) > 



R2 
R1' 



The design procedure for an AC coupled inverting amplifier 
using the LM3900 is therefore to first select R-|, Cin, R2. and 
Co as with a standard IC op amp and then to simply add R3 
= 2R2 as a final biasing consideration. Other biasing tech- 
niques are presented in the following sections of this note. 
For the switching circuit applications, the biasing model of 
Figure 10 is adequate to predict circuit operation. 
Although the LM3900 has four independent amplifiers, the 
use of the label " 1 / 4 LM3900" will be shortened to simply 
"LM3900" for the application drawings contained in this 
note. 

3.0 Designing AC Amplifiers 

The LM3900 readily lends itself to use as an AC amplifier 
because the output can be biased to any desired DC level 
within the range of the output voltage swing and the AC gain 
is independent of the biasing network. In addition, the single 
power supply requirement makes the LM3900 attractive for 
any low frequency gain application. For lowest noise per- 
formance, the (+) input should be grounded (Figure 9a) and 
the output will then bias at + V B e- Although the LM3900 is 
not suitable as an ultra low noise tape pre-amp, it is useful in 
most other applications. The restriction to only shunt feed- 
back causes a small input impedance. Transducers which 
can be loaded can operate with this low input impedance. 
The noise degradation which would result from the use of a 
large input resistor limits the usefulness where low noise 
and high input impedance are both required. 

3.1 SINGLE POWER SUPPLY BIASING 

The LM3900 can be biased in several different ways. The 
circuit in Figure 12 is a standard inverting AC amplifier which 
has been biased from the same power supply which is used 
to operate the amplifier. (The design of this amplifier has 
been presented in the previous section). Notice that if AC 
ripple voltages are present on the V+ power supply line 
they will couple to the output with a "gain" of 1 / a . To elimi- 
nate this, one source of ripple filtered voltage can be provid- 
ed and then used for many amplifiers. This is shown in the 
next section. 




TL/H/7383-14 



3.2 A NON-INVERTING AMPLIFIER 

The amplifier in Figure 13 shows both a non-inverting AC 
amplifier and a second method for DC biasing. Once again 
the AC gain of the amplifier is set by the ratio of feedback 
resistor to input resistor. The small signal impedance of the 
diode at the (+) input should be added to the value of R1 
when calculating gain, as shown in Figure 13. 

R3 




VoDC= — 

Tl/H/7383-15 

FIGURE 13. Non-inverting AC Amplifier 
Using Voltage Reference Biasing 

By making R2 = R3, Vodc wi|1 be equal to the reference 
voltage which is applied to the resistor R2. The filtered 
V+/2 reference shown can also be used for other amplifi- 
ers. 

3.3 "N V B e" BIASING 

A third technique of output DC biasing is best described as 
the "N Vbe" method. This technique is shown in Figure 14 
and is most useful with inverting AC amplifier applications. 



<\t 



fV I I 1M 

\VS^-H> 




A V S "ST 



R2 
R1 
TL/H/7383-16 

FIGURE 14. Inverting AC Amplifier Using N V B e Biasing 

The input bias voltage (Vbe) at the inverting input establish- 
es a current through resistor R3 to ground. This current 
must come from the output of the amplifier. Therefore, Vo 
must rise to a level which will cause this current to flow 
through R2. The bias voltage, Vo, may be calculated from 
the ratio of R2 to R3 as follows: 



Vqdc = v be 



(-1) 



FIGURE 12. Inverting AC Amplifier 
Using Single-Supply Biasing 



When NVbe biasing is employed, values for resistors R-| 
and R2 are first established and then resistor R3 is added to 
provide the desired DC output voltage. 



175 






For a design example (Figure 14), a Z in = 1 M and A v a 10 
are required. 
Select Ri = 1M. 
Calculate R 2 = A^ = 10M. 
To bias the output voltage at 7.5 Vqc. R3 is found as: 
R 2 10M 



R 3 



Vo 
vbe 



- 1 



LI 
0.5 



1 



R3 s 680 kn. 
3.4 BIASING USING A NEGATIVE SUPPLY 

If a negative power supply is available, the circuit of Figure 
15 can be used. The DC biasing current, I, is established by 
the negative supply voltage via R3 and provides a very sta- 
ble output quiescent point for the amplifier. 



<V 1 I "i 
— - J }— VW — (► 



<& 




R1 
TL/H/7383-17 



FIGURE 15. Negative Supply Biasing 

3.5 OBTAINING HIGH INPUT IMPEDANCE 
AND HIGH GAIN 

For the AC amplifiers which have been presented, a design- 
er is able to obtain either high gain or high input impedance 
with very little difficulty. The application which requires both 
and still employs only one amplifier presents a new prob- 
lem. This can be achieved by the use of a circuit similar to 
the one shown in Figure 16. When the A v from the input to 




TL/H/7383-18 

FIGURE 16. A High Z, N High Gain Inverting AC Amplifier 



point A is unity (R1 = R 3 ), the A v of the complete stage will 
be set by the voltage divider network composed of R4, R5, 
and C 2 . As the value of R 5 is decreased, the A v of the stage 
will approach the AC open loop limit of the amplifier. The 
insertion of capacitor C 2 allows the DC bias to be controlled 
by the series combination of R3 and R4 with no effect from 
R5. Therefore, R 2 may be selected to obtain the desired 
output DC biasing level using any of the methods which 
have been discussed. The circuit in Figure 16 has an input 
impedance of 1 M and a gain of 1 00. 

3.6 AN AMPLIFIER WITH A DC GAIN CONTROL 

A DC gain control can be added to an amplifier as shown in 
Figure 17. The output of the amplifier is kept from being 
driven to saturation as the DC gain control is varied by pro- 
viding a minimum biasing current via R3. For maximum gain, 
CR 2 is OFF and both the current through R 2 and R3 enter 
the (+ ) input and cause the output of the amplifier to bias at 
approximately 0.6 V+. For minimum gain, CR 2 is ON and 
only the current through R 3 enters the ( + ) input to bias the 
output at approximately 0.3 V+. The proper output bias for 
large output signal accommodation is provided for the maxi- 
mum gain situation. The DC gain control input ranges from 
Vqc for minimum gain to less than 10 Vqc for maximum 
gain. 




TL/H/7383-19 

FIGURE 17. An Amplifier with a DC Gain Control 

3.7 A LINE-RECEIVER AMPLIFIER 

The line-receiver amplifier is shown in Figure 18. The use of 
both inputs cancels out common-mode signals. The line is 
terminated by Rune and tne larger input impedance of the 
amplifier will not affect this matched loading. 



« R5< 

"i 




TL/H/7383-20 

FIGURE 18. A Line-receiver Amplifier 



176 



4.0 Designing DC Amplifiers 

The design of DC amplifiers using the LM3900 tends to be 
more difficult than the design of AC amplifiers. These diffi- 
culties occur when designing a DC amplifier which will oper- 
ate from only a single power supply voltage and yet provide 
an output voltage which goes to zero volts DC and also will 
accept input voltages of zero volts DC. To accomplish this, 
the inputs must be biased into the linear region (+ Vbe) with 
DC input signals of zero volts and the output must be modi- 
fied if operation to actual ground (and not Vsat) ' s required. 
Therefore, the problem becomes one of determining what 
type of network is necessary to provide an output voltage 
(Vo) equal to zero when the input voltage (Vin) is equal to 
zero. (See also section 10.15, "adding a Differential Input 
Stage"). 

We will start with a careful evaluation of what actually takes 
place at the amplifier inputs. The mirror circuit demands that 
the current flowing into the positive input (+) be equaled by 
a current flowing into the negative input (-). The difference 
between the current demanded and the current provided by 
an external source must flow in the feedback circuit. The 
output voltage is then forced to seek the level required to 
cause this amount of current to flow. If, in the steady state 
condition Vq = Vin = 0, the amplifier will operate in the 
desired manner. This condition can be established by the 
use of common-mode biasing at the inputs. 

4.1 USING COMMON-MODE BIASING 
FOR V, N = V DC 

Common-mode biasing is achieved by placing equal resis- 
tors between the amplifier input terminals and the supply 
voltage (V+), as shown in Figure 19. When Vin is set to 
volts the circuit can be modeled as shown in Figure 20, 



V 3 V| N 




TL/H/7383-21 

FIGURE 19. A DC Amplifier Employing 
Common-mode Biasing 



where: 



and 



Req! = Ri 
Req 2 = R 2 

R 3 = R* 



R 5 . 
R e . 



Because the current mirror demands that the two current 
sources be equal, the current in the two equivalent resistors 
must be identical. 




TL/H/7383-22 

FIGURE 20. An Ideal Circuit Model of a DC Amplifier 
with Zero Input Voltage 

If this is true, both R 2 and R6 must have a voltage drop of 
0.5 volt across them, which forces Vo to go to Vq min 
(Vsat)- 

4.2 ADDING AN OUTPUT DIODE FOR V = V DC 
For many applications a Vq min Of 1 00 mV may not be 
acceptable. To overcome this problem a diode can be add- 
ed between the output of the amplifier and the output termi- 
nal (Figure 21). 
v 



-WNr- 



I.5M < < 1.SM R4 



-VNAr- 



100K >v. 

r^ 4 — ^\ „, 

X (J J) LM3900 J>— ^j— 4 



¥ +^ 



A v = 10 



S 10K 



TL/H/7383-23 

FIGURE 21. A Non-inverting DC Amplifier with Zero 
Volts Output for Zero Volts Input 

The function of the diode is to provide a DC level shift which 
will allow Vo to go to ground. With a load impedance (R|_) 
connected, Vo becomes a function of the voltage divider 
formed by the series connection of R4 and R|_. 

0.5 Ri 
If R 4 = 100 R L , then V min = 757^. 

or Vo min = 5 mV D c- 

An offset voltage adjustment can be added as shown (R-|) 
to adjust Vo to OVqc with V| N = Vpc- 
The voltage transfer functions for the circuit in Figure 21, 
both with and without the diode, are shown in Figure 22. 
While the diode greatly improves the operation around 
volts, the voltage drop across the diode will reduce the peak 
output voltage swing of the state by approximately 0.5 volt. 
When using a DC amplifier similar to the one in Figure 21, 
the load impedance should be large enough to avoid exces- 
sively loading the amplifier. The value of R|_ may be signifi- 
cantly reduced by replacing the diode with an NPN transis- 
tor. 



177 



CM 




V m ImV) 

TL/H/7383-24 

FIGURE 22. Voltage Transfer Function for a DC 
Amplifier with a Voltage Gain of 10 

4.3 A DC COUPLED POWER AMPLIFIER (l L -, 3 AMPS) 

The LM3900 may be used as a power amplifier by the addi- 
tion of a Darlington pair at the output. The circuit shown in 
Figure 23 can deliver in excess of 3 amps to the load when 
the transistors are properly mounted on heat sinks. 




TL/H/7383-25 

FIGURE 23. A DC Power Amplifier 

4.4 GROUND REFERENCING A DIFFERENTIAL 
VOLTAGE 

The circuit in Figure 24 employs the LM3900 to ground ref- 
erence a DC differential input voltage. Current h is larger 




TL/H/7383-26 

FIGURE 24. Ground Referencing a Differential 
Input DC Voltage 

than current I3 by a factor proportional to the differential 
voltage, Vr. The currents labeled on Figure 24 axe given by: 
V1 + V R - * 



h = 



4>/R 2 
(V1 - 



«W 



and 



R 3 
R 4 



where 

<{> = Vbe at either input terminal of the LM3900. 

Since the input current mirror demands that 

I- = l+; 
and l+ = l 1 - l 2 

and |- = I3 + I4 

Therefore U = h — '2 - '3- 

Substituting in from the above equation 

Vp ~ <f> _ (V1 + Vr ~ 4>) (<fr) (V1 ~ <fr) 
R 4 H] R 2 R3 

and as R-\ = R 2 = R3 = R4 

V = (V, + V R - <J>) - (<f>) - V, + <f> + <f> 
or 

V = V R . 
The resistors are kept large to minimize loading. With the 
10 Mil resistors which are shown on the figure, an error 
exists at small values of V1 due to the input bias current at 
the (-) input. For simplicity this has been neglected in the 
circuit description. Smaller R values reduce the percentage 
error or the bias current can be supplied by an additional 
amplifier (see Section 10.7.1). 

For proper operation, the differential input voltage must be 
limited to be within the output dynamic voltage range of the 
amplifier and the input voltage V 2 must be greater than 1 
volt. For example; if V 2 = 1 volt, the input voltage V-) may 
vary over the range of 1 volt to - 1 3 volts when operating 
from a 1 5 volt supply. Common-mode biasing may be added 
as shown in Figure 25 to allow both V1 and V 2 to be nega- 
tive. 




TL/H/7383-27 

FIGURE 25. A Network to Invert and to Ground 
Reference a Negative DC Differential Input Voltage 

4.5 A UNITY GAIN BUFFER AMPLIFIER 

The buffer amplifier with a gain of one is the simplest DC 
application for the LM3900. The voltage applied to the input 
(Figure 26) will be reproduced at the output. However, the 
input voltage must be greater than one Vbe Dut less than 
the maximum output swing. Common-mode biasing can be 
added to extend Vin to Vqc. if desired. 



I1 = 



*1 



178 




V| N > V B E 



TL/H/7383-28 

FIGURE 26. A Unity-gain DC Buffer Amplifier 

5.0 Designing Voltage Regulators 

Many voltage regulators can be designed which make use 
of the basic amplifier of the LM3900. The simplest is shown 
in Figure 27a where only a Zener diode and a resistor are 
added. The voltage at the (-) input (one Vbe = 0.5 Vqc) 
appears across R and therefore a resistor value of 51 OH will 
cause approximately 1 mA of bias current to be drawn 
through the Zener. This biasing is used to reduce the noise 
output of the Zener as the 30 nA input current is too small 
for proper Zener biasing. To compensate for a positive tem- 
perature coefficient of the Zener, an additional resistor can 
be added, R2, (Figure 27b) to introduce an arbitrary number, 
N, of "effective" Vbe drops into the expression for the out- 
put voltage. The negative temperature coefficient of these 
diodes will also be added to temperature compensate the 
DC output voltage. For a larger output current, an emitter 
follower (Q1 of Figure 27c) can be added. This will multiply 
the 1 mA (max.) output current of the LM3900 by the £ of 
the added transistor. For example, a /3 = 30 will provide a 
max. load current of 300 mA. This added transistor also 
reduces the output impedance. An output frequency com- 
pensation capacitor is generally not required but may be 
added, if desired, to reduce the output impedance at high 
frequencies. 

The DC output voltage can be increased and still preserve 
the temperature compensation of Figure 27b by adding re- 
sistors Ra and Rg as shown in Figure 27d. This also can be 
accomplished without the added transistor, Q1 . The unregu- 
lated input voltage, which is applied to pin 14 of the LM3900 
(and to the collector of Q1 , if used) must always exceed the 
regulated DC output voltage by approximately 1 V, when the 
unit is not current boosted or approximately 2V when the 
NPN current boosting transistor is added. 

5.1 REDUCING THE INPUT-OUTPUT VOLTAGE 

The use of an external PNP transistor will reduce the re- 
quired (Vin - Vout) t0 a tow tenths of a volt. This will 
depend on the saturation characteristics of the external 
transistor at the operating current level. The circuit, shown 
in Figure 28, uses the LM3900 to supply base drive to the 
PNP transistor. The resistors R1 and R2 are used to allow 
the output of the amplifier to turn OFF the PNP transistor. It 
is important that pin 14 of the LM3900 be tied to the +V|n 
line to allow this OFF control to properly operate. Larger 
voltages are permissible (if the base-emitter junction of Q-| 
is prevented from entering a breakdown by a shunting di- 
ode, for example), but smaller voltages will not allow the 
output of the amplifier to raise enough to give the OFF con- 
trol. 

The resistor, R3, is used to supply the required bias current 
for the amplifier and R4 is again used to bias the Zener 
diode. Due to a larger gain, a compensation capacitor, Co, 
is required. Temperature compensation could be added as 
was shown in Figure 27b. 




IO 



TL/H/7383-29 



(a) Basic Current 




V = V z + N<f> 

TL/H/7383-30 

(b) Temperature Compensating 




V = V Z + 



(c) Current Boosting 



TL/H/7383-31 




TL/H/7383-32 
(d) Raising V Without Disturbing Temperature Compensation 

FIGURE 27. Simple Voltage Regulators 



179 



CM 




TL/H/7383-33 

FIGURE 28. Reducing (V| N - Vqut) 
5.2 PROVIDING HIGH INPUT VOLTAGE PROTECTION 

One of the four amplifiers can be used to regulate the sup- 
ply line for the complete package (pin 14), to provide protec- 
tion against large input voltage conditions, and in addition, 
to supply current to an external load. This circuit is shown in 
Figure 29. The regulated output voltage is the sum of the 
Zener voltage, CR2, and the Vbe of the inverting input termi- 
nal. Again, temperature compensation can be added as in 
Figure 27b. The second Zener, CR-) , is a low tolerance com- 
ponent which simply serves as a DC level shift to allow the 
output voltage of the amplifier to control the conduction of 
the external transistor, Q-\. This Zener voltage should be 
approximately one-half of the CR2 voltage to position the 
DC Output voltage level of the amplifier approximately in the 
center of the dynamic range. 




O«0-V J2 + * 



TL/H/7383-34 

FIGURE 29. High Vin Protection and Self-regulation 



The base drive current for Q-| is supplied via R-|. The maxi- 
mum current through R1 should be limited to 10 mA as 

= Vin (max) - (Vq + Vbe) 



'max 



R1 



To increase the maximum allowed input voltage, reduce the 
output ripple, or to reduce the (Vin - Vout) requirements of 
this circuit, the connection described in the next section is 
recommended. 

5.3 HIGH INPUT VOLTAGE PROTECTION AND LOW (V| N 
- Vout) 

The circuit shown in Figure 30 basically adds one additional 
transistor to the circuit of Figure 29 to improve the perform- 
ance. In this circuit both transistors (Q1 and Q2) absorb any 
high input voltages (and therefore need to be high voltage 
devices) without any increases in current (as with R1 of Fig- 
ure 29). The resistor R1 (of Figure 30) provides a "start-up" 
current into the base of Q2. 

A new input connection is shown on this regulator (the type 
on Figure 29 could also be used) to control the DC output 
voltage. The Zener is biased via R4 (at approximately 1 mA). 
The resistors R3 and R6 provide gain (non-inverting) to al- 
low establishing Vo at any desired voltage larger than Vz- 
Temperature compensation of either sign (±TC) can be ob- 
tained by shunting a resistor from either the ( + ) input to 
ground (to add + TC to Vo) or from the (-) input to ground 
(to add -TC to Vo). To understand this, notice that the 
resistor, R, from the (+) input to ground will add -N Vbe *° 
Vo where 

and Vbe < s the base emitter voltage of the transistor at the 
(+) input. This then also adds a positive temperature 
change at the output to provide the desired temperature 
correction. 

The added transistor, Q2, also increases the gain (which 
reduces the output impedance) and if a power device is 
used for Q1 large load currents (amps) can be supplied. This 
regulator also supplies the power to the other three amplifi- 
ers of the LM3900. 

5.4 REDUCING INPUT VOLTAGE DEPENDENCE AND 
ADDING SHORT-CIRCUIT PROTECTION 

To reduce ripple feedthrough and input voltage depen- 
dence, diodes can be added as shown in Figure 31 to drop- 
out the start once start-up has been achieved. Short-circuit 
protection can also be added as shown in Figure 32. 
The emitter resistor of Q2 will limit the maximum current of 
Q 2 to (V - 2 V BE )/R 5 - 




TL/H/7383-35 



FIGURE 30. A High V IN Protected, Low (V| N - Vqut) Regulator 



180 




CR1 = CR2 = CR3 = 1N914 
TL/H/7383-36 

FIGURE 31. Reducing V| N Dependence 




TL/H/7383-37 

FIGURE 32. Adding Short-circuit Current Limiting 

6.0 Designing RC Active Filters 

Recent work in RC active filters has shown that the perform- 
ance characteristics of multiple-amplifier filters are relatively 
insensitive to the tolerance of the RC components used. 
This makes the performance of these filters easier to con- 
trol in production runs, in many cases where gain is needed 
in a system design it is now relatively easy to also get fre- 
quency selectivity. 

The basis of active filters is a gain stage and therefore a 
multiple amplifier product is a valuable addition to this appli- 
cation area. When additional amplifiers are available, less 
component selection and trimming is needed as the per- 
formance of the filter is less disturbed by the tolerance and 
temperature drifts of the passive components. 
The passive components do control the performance of the 
filter and for this reason carbon composition resistors are 
useful mainly for room temperature breadboarding or for fi- 
nal trimming of the more stable metal film or wire-wound 
resistors. Capacitors present more of a problem in range of 
values available, tolerance and stability (with temperature, 
frequency, voltage and time). For example, the disk ceramic 
type of capacitors are generally not suited to active filter 
applications due to their relatively poor performance. 
The impedance level of the passive components can be 
scaled without (theoretically) affecting the filter characteris- 
tics. In an actual circuit; if the resistor values become too 
small (^10 kfi) an excessive loading may be placed on the 
output of the amplifier which will reduce gain or actually 
exceed either the output current or the package dissipation 
capabilities of the amplifier. This can easily be checked by 
calculating (or noticing) the impedance which is presented 
to the output terminal of the amplifier at the highest operat- 
ing frequency. A second limit sets the upper range of imped- 
ance levels, this is due to the DC bias currents ( = 30 nA) 
and the input impedance of actual amplifiers. The solution 
to this problem is to reduce the impedance levels of the 
passive components (^10 Mfl). In general, better perform- 



ance is obtained with relatively low passive component im- 
pedance levels and in filters which do not demand high 
gain, high Q (Q ^ 50) and high frequency (f > 1 kHz) 
simultaneously. 

A measure of the effects of changes in the values of the 
passive components on the filter performance has been giv- 
en by "sensitivity functions". These assume infinite amplifier 
gain and relate the percentage change in a parameter of the 
filter, such as center frequency (f ), Q, or gain to a percent- 
age change in a particular passive component. Sensitivity 
functions which are small are desirable (as 1 or 1 / 2 ). 
Negative signs simply mean an increase in the value of a 
passive component causes a decrease in that filter perform- 
ance characteristic. As an example, if a bandpass filter list- 
ed the following sensitivity factor 

o 

S = -y 2 . 

C 3 
This states that "if C3 were to increase by 1%, the center 
frequency, o> , would decrease by 0.5%." Sensitivity func- 
tions are tabulated in the reference listed at the end of this 
section and will therefore not be included here. 
A brief look at low pass, high pass and bandpass filters will 
indicate how the LM3900 can be applied in these areas. A 
recommended text (which provided these circuts) is, "Oper- 
ational Amplifiers", Tobey, Graeme, and Huelsman, 
McGraw Hill, 1971. 

6.1 BIASING THE AMPLIFIERS 

Active filters can be easily operated off of a single power 
supply when using these multiple single supply amplifiers. 
The general technique is to use the ( + ) input to accomplish 
the biasing function. The power supply voltage, V+, is used 
as the DC reference to bias the output voltage of each am- 
plifier at approximately V+/2. As shown in Figure 33, unde- 
sired AC components on the power supply line may have to 




vc— vw* 



TL/H/7383-38 



(a) Biasing From a "Noise-Free" Power Supply 
v* 




TL/H/7383-39 



(b) Biasing From a "Noisy" Power Supply 



FIGURE 33. Biasing Considerations 

be removed (by a filter capacitor, Figure 33b) to keep the 
filter output free of this noise. One filtered DC reference can 
generally be used for all of the amplifiers as there is essen- 
tially no signal feedback to this bias point. 
In the filter circuits presented here, all amplifiers will be bi- 
ased at V+ /2 to allow the maximum AC voltage swing for 
any given DC power supply voltage. The inputs to these 
filters will also be assumed at a DC level of V+/2 (for those 
which are direct coupled). 



181 



6.2 A HIGH PASS ACTIVE FILTER 

A single amplifier high pass RC active filter is shown in Fig- 
ure 34. This circuit is easily biased using the ( + ) input of the 
LM3900. The resistor, R3, can be simply made equal to R2 
and a bias reference of V+/2 will establish the output Q 
point at this value (V+/2). The input is capacitively coupled 
(C-|) and there are therefore no further DC biasing problems. 




TL/H/7383-40 

FIGURE 34. A High Pass Active Filter 

The design procedure for this filter is to select the pass 

band gain, Ho, the Q and the corner frequency, f c . A Q 

value of 1 gives only a slight peaking near the bandedge 

(<2 dB) and smaller Q values decrease this peaking. The 

slope of the skirt of this filter is 12 dB/octave (or 40 dB/dec- 

ade). If the gain, Ho, is unity all capacitors have the same 

value. The design proceeds as: 

Given: Hq, Q and o> c = 2wi c 

To find: R 1p R 2 , C^ C 2 , and C 3 

let C1 = C3 and choose a convenient starting value. 

Then: 



R1 = 



1 



Qco c C 1 (2H + D 
R 2 = -^r(2H + 1), 



and 



o) c C 1 



C 2 = 



Ho' 



(D 



(2) 



(3) 



As a design example, 
Require: Ho = 1 , 
Q = 10, 
and f c = 1 kHz (<o c = 6.28 X 103 r ps). 
Start by selecting C1 = 300 pF and then from equation (1) 



R 1 = 



1 



(10) (6.28 x 103) (3 X 10- 
R-l = 17.7kft 
and from equation (2) 

n -. 10 O) 

2 (6.28 X 103) (3 X 10-10) 
R 2 = 15.9 MO 
and from equation (3) 

C 2 = — = C1 



10) (3) 



Now we see that the value of R 2 is quite large; but the other 
components look acceptable. Here is where impedance 
scaling comes in. We can reduce R 2 to the more convenient 
value of 10 Mfl which is a factor of 1.59:1. Reducing R1 by 
this same scaling factor gives: 

17.7 X 103 



1 1NEW 



1.59 



= 11.1 kn 



and the capacitors are similarly reduced in impedance as: 
fa = C 2 = C 3 )new = (1-59) (300) pF 



C 1NEW = 477 P F - 

To complete the design, R3 is made equal to R 2 (10 Mfl) 
and a Vref of V+/2 is used to bias the output for large 
signal accommodation. 

Capacitor values should be adjusted to use standard valued 
components by using impedance scaling as a wider range 
of standard resistor values is generally available. 

6.3 A LOW PASS ACTIVE FILTER 

A single amplifier low pass filter is shown in Figure 35. The 
resistor, R 4 , is used to set the output bias level and is se- 
lected after the other resistors have been established. 




f c = 1 kHz 
GAIN = 1 



TL/H/7383-41 

FIGURE 35. A Low Pass Active Filter 

The design procedure is as follows: 
Given: Hq, Q, and a) c = 27rf c 
To find: R-|, R 2 , R 3 , R 4 , C^ and C 2 
Let C-\ be a convenient value, 
then 

C 2 = KCt (4) 

where K is a constant which can be used to adjust compo- 
nent values. For example, with K = 1, C-| = C 2 . Larger 
values of K can be used to reduce R 2 and R3 at the ex- 
pense of a larger value for C 2 . 



-fc 



R 2 = 



1 



2Q toe C1 



[W 



1 | 4QZ(Hq+1) 



and 



R3 



1 



As a design example: 
Require: Ho = 1 . 

Q= 1, 
and f c = 1 kHz (« c 



«c 2 Ci 2 R 2 (K) 



6.28 x 103 rps). 



(5) 



(6) 



(7) 



182 



iFio>[ 1±VfT H 



Start by selecting C-| = 300 pF and K = 1 so C2 is also 300 
pF (equation 4). 
Now from equation (6) 

R 2 = ! 

2 2 (1) (6.28 X 103) (3 X 

R 2 = 1.06 Mfl 

Then from equation (5) 

R 1 = R 2 = 1.06 MH 

and finally from equation (7) 

1 

Rg = 

(6.28 X 103) 2 (3 X 10-10) 2 (1.06 X 106) (1) 
R 3 = 266 kft. 
To select R4, we assume the DC input level is 7 Vqc and 
the DC output of this filter is to also be 7 Vqc- This gives us 
the circuit of Figure 36. Notice that Hq = 1 gives us not only 



^7VdcO VS/Sr 




+ 7V 0C 



TL/H/7383-42 

FIGURE 36. Biasing the Low Pass Filter 

equal resistor values (R1 and R 2 ) but simplifies the DC bias 
calculation as I1 = l 2 and we have a DC amplifier with a 
gain of - 1 (so if the DC input voltage increases 1 Vqc t ne 
output voltage decreases 1 Vqc)- The resistors R1 and R 2 
are in parallel so that the circuit simplifies to that shown in 
Figure 37 where the actual resistance values have been 
added. The resistor R4 is given by 



R 4 



<£♦*) 



+ R 3 



or, using values 



R 4 = 2[^-^ + 266k j = 1.5 MH 



R1 R2 = R1/2 




+'5Voc TL/H/7383-43 

FIGURE 37. Biasing Equivalent Circuit 



6.4 A SINGLE-AMPLIFIER BANDPASS ACTIVE FILTER 

The bandpass filter is perhaps the most interesting. For low 
frequencies, low gain and low Q (^10) requirements, a sin- 
gle amplifier realization can be used. A one amplifier circuit 
is shown in Figure 38 and the design procedure is as fol- 
lows; 

Given: Ho, Q and w = 2th. 
To find: R1, R 2 , R3. R4. C 1 and C 2 . 



SIOpF 



-4 




f = 1 kHz 
Q = 5 
GAIN = 1 

+V REF (V + ) 

TL/H/7383-44 

FIGURE 38. A One Op Amp Bandpass Filter 

Let C1 = C 2 and select a convenient starting value. 
Then 

Q 



R1 = 



HqWoC-i 



R 2 



Q 



R 3 = 



(2Q2-H )o) C 1 
2Q 



&) C-| 



and 



R 4 = 2R 3 (forV REF = V+) 
As a design example: 
Require: Ho = 1 
Q = 5 

f = 1 kHz (w = 6.28 X 103 rps ). 
Start by selecting 

C-, = C 2 = 510 pF. 
Then using equation (8) 

= 5 

1 (6.28 X 103) (5.1 X 10-1°) 
Rt = 1.57 Mil, 
and using equation (9) 

Rz ~ [2(25) - 1] (6.28 X 103) (5.1 x 10-10) 
R 2 = 32 kft 
from equation (1 0) 

n 2 & 

3 (6.28 X 103) (5.1 X 10-10) 

R 3 = 3.13 Mft, 

and finally, for biasing, using equation (11) 

R 4 = 6.2 MO. 



(8) 

(9) 

(10) 

(11) 



183 



6.5 A TWO-AMPLIFIER BANDPASS ACTIVE FILTER 

To allow higher Q (between 10 and 50) and higher gain, a 
two amplifier filter is required. This circuit, shown in Figure 
39, uses only two capacitors. It is similar to the previous 
single amplifier bandpass circuit and the added amplifier 
supplies a controlled amount of positive feedback to im- 
prove the response characteristics. The resistors R5 and Rs 
are used to bias the output voltage of the amplifiers at 
V+/2. 

Again, R5 is simply chosen as twice R4 and Rs must be 
selected after R$ and R7 have been assigned values. The 
design procedure is as follows: 
Given: Q and f 

To find: R1 through R7, and C1 and C 2 
Let: C1 = C2 and choose a convenient starting value and 
choose a value for K to reduce the spread of element val- 
ues or to optimize sensitivity (1 <. Kxypically^l )- 
Then 



Rl = R 4 = R 6 = 



Q 
<u Ci 



R 2 = R! 



KQ 



R 3 = 



(2Q - 1) 
Rl 



Q2- 1 -2/K+1/KQ 



and 



R 7 = KR! 

H = VQ K. 
As a design example: 
Require: Q = 25 and f = 1 kHz. 
Select: C-| = C 2 = 0.1 jxF 
and K = 3. 
Then from equation (1 2) 

25 



(12) 

(13) 

(14) 

(15) 
(16) 



R4 = Re = 



(2tt X 103) (10-7) 



and from equation (13) 
R 2 = (40 X 103)- 



3(25) 



[2(25) 
R 2 = 61 kft 
and from equation (14) 

40 X 103 



R 3 = 



(25)2 _ 1 _ 2/3 + 



1 



3(25) 
R 3 = 64ft 
And R7 is given by equation (15) 

R 7 = 3(40kft) = 120 kft, 
and the gain is obtained from equation (16) 

H = >/25(3) = 15(23dB). 
To properly bias the first amplifier 

R 5 = 2R 4 = 80 kft 
and the second amplifier is biased by Re- Notice that the 
outputs of both amplifiers will be at V+ /2. Therefore R6 and 
R7 can be paralleled and 

R 8 = 2(R 6 || R 7 ) 
or 

[(40) (120) X 103] 



*-«[! 



160 



; ] = 



59 kft 



R 1 = 40 kft 



These values, to the closest standard resistor values, have 
been added to Figure 39. 

6.6 A THREE-AMPLIFIER BANDPASS ACTIVE FILTER 

To reduce Q sensitivity to element variation even further or 
to provide higher Q (Q>50) a three amplifier bandpass filter 
can be used. This circuit, Figure 40, pre-dates most of the 
literature on RC active filters and has been used on analog 
computers. Due to the use of three amplifiers it often is 
considered too costly — especially for low Q applications. 
The multiple amplifiers of the LM3900 make this a very use- 
ful circuit. It has been called the "Bi-Quad" as it can pro- 
duce a transfer function which is "Quad"-ratic in both nu- 
merator and denominator (to give the "Bi"). A newer real- 



0.1 M F 




<>— OVo 



f = 1 kHz 

Q = 25 

GAIN = 15(23dB) 



TL/H/7383-45 



FIGURE 39. A Two Op Amp Bandpass Filter 



184 



V )N DC = 




-J 



f = 1 KHz 

Q = 50 

H = 100 (40 dB) 



FIGURE 40. The "Bi-quad" RC Active Bandpass Filter 



TL/H/7383-46 



ization technique for this type of filter is the "second-degree 
state-variable network." Outputs can be taken at any of 
three points to give low pass, high pass or bandpass re- 
sponse characteristics (see the reference cited). 
The bandpass filter is shown in Figure 40 and the design 
procedure is: 
Given: Q and f . 

To simplify: Let C-| = C 2 and choose a convenient starting 
value and also let 2Ri = R2 = R3 and choose a conve- 
nient starting value. 
Then: 

R 4 = R! (20. - 1), (17) 

1 
R 5 = R7 = 



and for biasing the amplifiers we require 

R 6 = R 8 = 2R 5 . 
The mid-band gain is: 

"1 



(18) 



(19) 



(20) 



As a design example; 

Require: f = 1 kHz and Q = 50. 

To find: C-|, C2 and R1 through R 8 . 

Choose: Q,\ = C 2 = 330 pF 

and 2Ri = R 2 = R 3 = 360 kn, and R-\ = 180 kn. 



Then from equation (1 7), 

R 4 = (1.8 X 105) [2(50)- 1] 

R 4 = 17.8 Mil 
From equation (18), 

1 

R5 - R7 - (2w x 1Q3) (3 3 x 10 -10) 

R 5 = 483 kil. 

And from equation (1 9), 

R 6 = R 8 a 1 Ma. 

From equation (20) the midband gain is 100 (40 dB). The 

value of R4 is high and can be lowered by scaling only R-i 

through R 4 by the factor 1 .78 to give: 

360 X 10 3 
2R-| = R 2 = R3 = — r^ — = 200 kil, R1 



and 



R 4 



1.78 



17.8 X 1Q6 
1.78 



100 kfl. 



10 Ma. 



These values (to the nearest 5% standard) have been add- 
ed to Figure 40. 

6.7 CONCLUSIONS 

The unity-gain cross frequency of the LM3900 is 2.5 MHz 
which is approximately three times that of a "741 " op amp. 
The performance of the amplifier does limit the performance 
of the filter. Historically, RC active filters started with little 



185 



concern for these practical problems. The sensitivity func- 
tions were a big step forward as these demonstrated that 
many of the earlier suggested realization techniques for RC 
active filters had passive component sensitivity functions 
which varied as Q or even Q 2 . The Bi-Quad circuit has re- 
duced the problems with the passive components (sensitivi- 
ty functions of 1 or 1 / 2 ) and recently the contributions of the 
amplifier on the performance of the filter are being investi- 
gated. An excellent treatment ("The Biquad: Part I — Some 
Practical Design Considerations," LC. Thomas, IEEE 
Transactions on Circuit Theory, Vol. CT-18, No. 3, May 
1971) has indicated the limits imposed by the characteris- 
tics of the amplifier by showing that the design value of Q 
(Qd) will differ from the actual measured value of Q (Qa) by 
the given relationship 

n Qd 

q a ^ (21) 



1 + 



2Qp 
Ao&> a 



(co a - 2fc) p ) 



where Ao is the open loop gain of the amplifier, &> a is the 
dominant pole of the amplifier and o> p is the resonant fre- 
quency of the filter. The result is that the trade-off between 
Q and center frequency (a> p ) can be determined for a given 
set of amplifier characteristics. When Qa differs significantly 
from Qq excessive dependence on amplifier characteristics 
is indicated. An estimate of the limitations of an amplifier 
can be made by arbitrarily allowing approximately a 10% 
effect on Qa which results if 

2Qd , 
(co a - 2co p ) = 0.1 



M= 2.5 X 10-2 (*>) 



+ 0.5. 



(22) 



As an example, using Ao = 2800 for the LM3900 we can 
estimate the maximum frequency where a Qd = 50 would 
be reasonable as 



f = 2.5 x 10" 
fa 



/ 2.8 X 1Q3 \ 
V 5X10 J 



+ 0.5 



therefore 



f = 1 - 



f D = 1.9 f a . 



Again, using data of the LM3900, f a = 1 kHz so this upper 
frequency limit is approximately 2 kHz for the assumed Q of 
50. As indicated in equation (26) the value of Qa can actual- 
ly exceed the value of Qp (Q enhancement) and, as expect- 
ed, the filter can even provide its own input (oscillating). 
Excess phase shift in the high frequency characteristics of 
the amplifier typically cause unexpected oscillations. Phase 
compensation can be used in the Bi-Quad network to re- 
duce this problem (see L.C. Thomas paper). 
Designing for large passband gain also increases filter de- 
pendency on the characteristics of the amplifier and finally 
signal to noise ratio can usually be improved by taking gain 
in an input RC active filter (again see L.C. Thomas paper). 
Somewhat larger Q's can be achieved by adding more filter 
sections in either a synchronously tuned cascade (filters 
tuned to same center frequency and taking advantage of 
the bandwidth shrinkage factor which results from the series 
connection) or as a standard multiple pole filter. All of the 
conventional filters can be realized and selection is based 
upon all of the performance requirements which the applica- 
tion demands. The cost advantages of the LM3900, the rel- 
atively large bandwidth and the ease of operation on a sin- 
gle power supply voltage make this product an excellent 
"building block" for RC active filters. 

7.0 Designing Waveform 
Generators 

The multiple amplifiers of the LM3900 can be used to easily 
generate a wide variety of waveforms in the low frequency 
range (f <, 10 kHz). Voltage controlled oscillators (VCO)'s) 
are also possible and are presented in section 8.0 "Design- 
ing Phase-locked Loops and Voltage Controlled 




DIFFERENCE AVERAGER 



V PEAK = 2 Vref 

f = 1 kHz 

THD = 0.1% (Vo = 5V p ) 

TL/H/7383-48 



FIGURE 41. A Sinewave Oscillator 



186 



Oscillators." In addition, power oscillators (such as noise 
makers, etc.) are presented in section 10.11.3. The wave- 
form generators which will be presented in this section are 
mainly of the switching type, but for completeness a sine- 
wave oscillator has been included. 

7.1 A SINEWAVE OSCILLATOR 

The design of a sinewave oscillator presents problems in 
both amplitude stability (and predictability) and output wave- 
form purity (THD). If an RC bandpass filter is used as a high 
Q resonator for the oscillator circuit we can obtain an output 
waveform with low distortion and eliminate the problem of 
relative center frequency drift which exists if the active filter 
were used simply to filter the output of a separate oscillator. 
A sinewave oscillator which is based on this principle is 
shown in Figure 41. The two-amplifier RC active filter is 
used as it requires only two capacitors and provides an over- 
all non-inverting phase characteristic. If we add a non-in- 
verting gain controlled amplifier around the filter we obtain 
the desired oscillator configuration. Finally, the sinewave 
output voltage is sensed and regulated as the average value 
is compared to a DC reference voltage, Vref. by use of a 
differential averaging circuit. It can be shown that with the 
values selected for R15 and Ri6 (ratio of 0.64/1) that there 
is first order temperature compensation for CR3 and the 
internal input diodes of the IC amplifier which is used for the 
"difference averager". Further, this also provides a simple 
way to regulate and to predict the magnitude of the output 
sinewave as 

V peak = 2 V REF 
which is essentially independent of both temperature and 
the magnitude of the power supply voltage (if Vref is de- 
rived from a stable voltage source). 

7.2 SQUAREWAVE GENERATOR 

The standard op amp squarewave generator has been mod- 
ified as shown in Figure 42. The capacitor, C-|, alternately 




:rur 



TL/H/7383-47 

FIGURE 42. A Squarewave Oscillator 

charges and discharges (via R-j) between the voltage limits 
which are established by the resistors R2, R3 and R4. This 
combination produces a Schmitt Trigger circuit and the op- 
eration can be understood by noticing that when the output 
is low (and if we neglect the current flow through R4) the 
resistor R2 (3M) will cause the trigger to fire when the cur- 
rent through this resistor equals the current which enters 
the (+) input (via R 3 ). This gives a firing voltage of approxi- 
mately R2/(R3) V+ (or V+/3). The other trip point, when 
the output voltage is high, is approximately [2(R2/R3)1 V+, 
as R3 = R4, or 2 / 3 (V+). Therefore the voltage across the 
capacitor, C-|, will be the first one-half of an exponential 
waveform between these voltage trip limits and will have 
good symmetry and be essentially independent of the mag- 
nitude of the power supply voltage. If an unsymmetrical 
squarewave is desired, the trip points can be shifted to pro- 
duce any desired mark/space ratio. 



7.3 PULSE GENERATOR 

The squarewave generator can be slightly modified to pro- 
vide a pulse generator. The slew rate limits of the LM3900 
(0.5V/ju,sec) must be kept in mind as this limits the ability to 
produce a narrow pulse when operating at a high power 
supply voltage level. For example, with a + 1 5 Vpc power 
supply the rise time, t r , to change 1 5V is given by: 
15V 15V 



tr = 



0.5V/ju,sec 



Slew Rate 
t r = 30 jmsec. 
The schematic of a pulse generator is shown in Figure 43. A 
diode has been added, CR^, to allow separating the charge 
path to C1 (via R-|) from the discharge path (via R2). The 

I CHARGE -, CM 
39K '»'« 

■WV-— 14 




100 jj.s 
1 kHz 



FIGURE 43. A Pulse Generator 



m\-m- 



TL/H/7383-49 



circuit operates as follows: Assume first that the output volt- 
age has just switched low (and we will neglect the current 
flow through R4). The voltage across C1 is high and the 
magnitude of the discharge current (through R2) is given by 
_ Vc-, - Vbe 

'Discharge — □ 

This current is larger than that entering the (+) input which 
is given by 

V + ~ Vbe 
lR3-_ ^~- 
The excess current entering the (— ) input terminal causes 
the amplifier to be driven to a low output voltage state (satu- 
ration). This condition remains for the long time interval 
(1 /Pulse Repetition Frequency) until the R 2 Ci discharge 
current equals the Ir 3 value (as CR1 is OFF during this inter- 
val). The voltage across C<\ at the trip point, V|_, is given by 

V L = (Ir 3 ) (R 2 ). 
or 



V L = (v+ - V BE ) 



m- 



(D 



At this time the output voltage will switch to a high state, 
VoHi. and the current entering the ( + ) input will increase to 



•m" 



V+ 



- Vbe + Vqhj ~ v be 
r 3 R 4 



187 



Also CRi goes ON and the capacitor, Ci, charges via R-|. 
Some of this charge current is diverted via R2 to ground (the 
(-) input is at Vcesat during this interval as the current 
mirror is demanding more current than the (-) input termi- 
nal can provide). The high trip voltage, Vh, is given by 

V H = (Im + )R2 or 



V H 



.(VI 



VBE , V Hi - v B e n 



R 2 . 



(2) 



R 3 R 4 

A design proceeds by first choosing the trip points for the 
voltage across C1 . The resistors R3 and R 4 are used only 
for this trip voltage control. The resistor R 2 affects the dis- 
charge time (the long interval) and also both of the trip volt- 
ages so this resistor is determined first from the required 
pulse repetition frequency (PRF). The value of R2 is deter- 
mined by the RC exponential discharge from Vh to Vl as 
this time interval, T^ controls the PRF <J-\ = 1/PRF). If we 
start with the equation for the RC discharge we have 

Ti 
Vl = V H e R2C1 



T1 



|p Vl = 
V H R2C1 



Vh 

Ti = R 2 Ciln-f 

V|_ 



(3) 



To provide a low duty cycle pulse train we select small val- 
ues for both V H and Vl (such as 3V and 1 .5V) and choose a 
starting value for C-|. Then R2 is given by 

R - T1 

2 Cl ln^' W 

Vl 

If R2 from (4) is not in the range of approximately 100 kft to 
1 Mfi, choose another value for C-|. Now equation (1) can 
be used to find a value for R 3 to provide the Vl which was 
initially assumed. Similarly equation (2) allows R 4 to be cal- 
culated. Finally R1 is determined by the required pulse width 
(PW) as the capacitor, C lf must be charged from Vl to Vh 
by R-|. This RC charging is given by (neglecting the loading 
due to R2) 

V H s (V Hi-V D )(l -e~R^j 



T2 " R ' c <4-*^d 



R1 « 



v OHi _ V D J 
T 2 



, and finally 



(5) 



where T 2 is the pulse width desired and Vp is the forward 
voltage drop across CR-|. 
As a design example: 

Required: Provide a 100 jas pulse every 1 ms. The power 
supply voltage is + 1 5 Vqc 
1 .0 Start by choosing V L = 1 .5V 
and V H = 3.0V 



2.0 Find R 2 from equation (4) assuming C1 = 0.01 juF, 

10-3 
R 2 = — 



10-8 In 
105 



(S) 



R 2 = 777^7 = 144 Ml 
0.694 

3.0 Find R3 from equation (1) 

(V+ - V BE ) R 2 



R 3 = 



R 3 



(15 



V L 
0.5)1.44x105 



1.5 



R 3 = 1.39 Mft 
4.0 Find R4 from equation (2), 

p _ (Vohi- Vbe) 

R 4 



R 4 = 

1.44x105 
R 4 = 1.32 Mil 
5.0 Find R1 from equation (5), 

10" 



V H 
R 2 


v+ - 

R3 

(14.2 - 


V B E 
0.5) 






3 


15- 


0.5 



1.39x106 



Rl = 



R1 = 



R1 = 



-10 



-8 



I 1 (14.2 -0.7) J 



-,n(l-JL) 
V 13.5/ 



104 



= 39.7 kn. 



0.252 

These values (to the nearest 5% standard) have been add- 
ed to Figure 43. 

7.4 TRIANGLE WAVEFORM GENERATOR 

Triangle waveforms are usually generated by an integrator 
which receives first a positive DC input voltage, then a nega- 
tive DC input voltage. The LM3900 easily provides this oper- 
ation in a system which operates with only a single power 
supply voltage by making use of the current mirror which 
exists at the (+) input. This allows the generation of a trian- 
gle waveform without requiring a negative DC input voltage. 
The schematic diagram of a triangle waveform generator is 
shown in Figure 44. One amplifier is doing the integration by 



IM I (S 

VO— 4/W— * 




SCHMITT TRIGGER 

TL/H/7383-50 

FIGURE 44. A Triangle Waveform Generator 



188 



operating first with the current through Ri to produce the 
negative output voltage slope, and then when the output of 
the second amplifier (the Schmitt Trigger) is high, the cur- 
rent through R2 causes the output voltage to increase. If R1 
= 2R2, the output waveform will have good symmetry. The 
timing for one-half of the period (T/2) is given by 

T (RjCQAVq 
2 V+ - V BE 
or the output frequency becomes 

f - V+ ~ V BE 

2R 1 C 1 AV 
where we have assumed R1 = 2R2, Vg^ is the DC voltage 
at the (-) input (0.5 Vqc). and AVrj is the difference be- 
tween the trip points of the Schmitt Trigger. The design of 
the Schmitt Trigger has been presented in the section on 
Digital and Switching Circuits (9.0) and the trip voltages con- 
trol the peak-to-peak excursion of the triangle output volt- 
age waveform. The output of the Schmitt circuit provides a 
squarewave of the same frequency. 

7.S SAWTOOTH WAVEFORM GENERATOR 

The previously described triangle waveform generator, Fig- 
ure 44, can be modified to produce a sawtooth waveform. 
Two types of waveforms can be provided, both a positive 
ramp and a negative ramp sawtooth waveform by selecting 
R1 and R2. The reset time is also controlled by the ratio of 
R1 and R2. For example, if R-| = 10 Rg a positive ramp 
sawtooth results and if R2 = 10 R1 a negative ramp saw- 
tooth can be obtained. Again, the slew rate limits of the 
amplifier (0.5V/ jxs) will limit the minimum retrace time, and 
the Increased slew rate of a negative going output will allow 
a faster retrace for a positive ramp sawtooth waveform. 



To provide a gated sawtooth waveform, the circuits shown 
in Figure 45 can be used. In Figure 45(a), a positive ramp is 
generated by integrating the current, I, which is entering the 
( + ) input. Reset is provided via R1 and CR1 keeps R1 from 
loading at the (-) input during the sweep interval. This will 
sweep from Vrj min to v O max and will remain at Vo max 
until reset. The interchange of the input leads, Figure 45(b), 
will generate a negative ramp, from Vq max to Vq min- 



RESET o— <vw 



^1 
10 




(a) Positive Ramp 



TL/H/7383-51 



o— wv-i- 




TL/H/7383-52 



(b) Negative Ramp 

FIGURE 45. Gated Sawtooth Generators 




TL/H/7383-53 



FIGURE 46. Generating Very Slow Sawtooth Waveforms 



189 



7.5.1 GENERATING A VERY SLOW 
SAWTOOTH WAVEFORM 

The LM3900 can be used to generate a very slow sawtooth 
waveform which can be used to generate long time delay 
intervals. The circuit is shown in Figure 46 and uses four 
amplifiers. Amps 1 and 2 are cascaded to increase the gain 
of the integrator and the output is the desired very slow 
sawtooth waveform. Amp 3 is used to exactly supply the 
bias current to Amp 1 . 

With resistor Rg opened up and the reset control at zero 
volts, the potentiometer, R 5 , is adjusted to minimize the drift 
in the output voltage of Amp 2 (this output must be kept in 
the linear range to insure that Amp 2 is not in saturation). 
Amp 4 is used to provide a bias reference which equals the 
DC voltage at the (-) input of Amp 3. The resistor divider, 
R7 and Rg provides a 0.1 Vrx reference voltage across Rg 
which also appears across Re. The current which flows 
through Rg, I, enters the (-) input of Amp 3 and causes the 
current through R6 to drop by this amount. This causes an 
imbalance as now the current flow through R4 is no longer 
adequate to supply the input current of Amp 1 . The net re- 
sult is that this same current, I, is drawn from capacitor C1 
and causes the output voltage of Amp 2 to sweep slowly 
positive. As a result of the high impedance values used, the 
PC component board used for this circuit must first be 
cleaned and then coated with silicone rubber to eliminate 
the effects of leakage currents across the surface of the 
board. The DC leakage currents of the capacitor, C1 , must 
also be small compared to the 1 nA charging current. For 
example, an insulation resistance of 100,000 Mil will leak 
0.1 nA with 10 Vqc across the capacitor and this leakage 
rapidly increases at higher temperatures. Dielectric polariza- 
tion of the dielectric material may not cause problems if the 
circuit is not rapidly cycled. The resistor, R$, and the capaci- 
tor, C1, can be scaled to provide other basic sweep rates. 
For the values shown on Figure 46 the 1 nA current and 
the 1ju,F capacitor establish a sweep rate of 100 sec/volt. 
The reset control pulse (Amp 3 (+) input) causes Amp 3 to 
go to the positive output saturation state and the 10 Mft 
(R4) gives a reset rate of 0.7 sec/volt. The resistor, R-|, 
prevents a large discharge current of C1 from overdriving 
the (-) input and overloading the input clamp device. For 
larger charging currents, a resistor divider can be placed 
from the output of Amp 4 to ground and Rs can tie from this 
tap point directly to the (-) input of Amp 1 . 



7.6 STAIRCASE WAVEFORM GENERATORS 

A staircase generator can be realized by supplying pulses to 
an integrator circuit. The LM3900 also can be used with a 
squarewave input signal and a differentiating network where 
each transition of the input squarewave causes a step in the 
output waveform (or two steps per input cycle). This is 
shown in Figure 47. These pulses of current are the charge 
and discharge currents of the input capacitor, C-|. The 
charge current, Iq, enters the (+) input and is mirrored 
about ground and is "drawn into" the (-) input. The dis- 
charge current, Id, is drawn through the diode at the input, 
CR-|, and therefore also causes a step on the output stair- 
case. 

A free running staircase generator is shown in Figure 48. 
This uses all four of the amplifiers which are available in one 
LM3900 package. 

Amp 1 provides the input pulses which "pump up" the stair- 
case via resistor R1 (see section 7.3 for the design of this 
pulse generator). Amp 2 does the integrate and hold func- 
tion and also supplies the output staircase waveform. Amps 
3 and 4 provide both a compare and a one-shot multivibra- 
tor function (see the section on Digital and Switching Cir- 
cuits for the design of this dual function one-shot). Resistor 
R4 is used to sample the staircase output voltage and to 
compare it with the power supply voltage (V+) via R3. When 
the output exceeds approximately 80% of V+ the connec- 
tion of Amps 3 and 4 causes a 1 00 ju,sec reset pulse to be 
generated. This is coupled to the integrator (Amp 2) via R2 
and causes the staircase output voltage to fall to approxi- 
mately zero volts. The next pulse out of Amp 1 then starts a 
new stepping cycle. 

7.7 A PULSE COUNTER AND A VOLTAGE VARIABLE 
PULSE COUNTER 

The basic circuit of Figure 48 can be used as a pulse coun- 
ter simply by omitting Amp 1 and feeding input voltage puls- 
es directly to R-|. A simpler one-shot/comparator which re- 
quires only one amplifier can also be used in place of Amps 
3 and 4 (again, see the section on Digital and Switching 
Circuits). To extend the time interval between pulses, an 
additional amplifier can be used to supply base current to 
Amp 2 to eliminate the tendency for the output voltage to 
drift up due to the 30 nA input current (see section 7.5.1). 
The pulse count can be made voltage variable simply by 
removing the comparator reference (R3) from V+ and using 
this as a control voltage input. Finally, the input could be 
derived from differentiating a squarewave input as was 
shown in Figure 47 and if only one step per cycle were 
desired, the diode, CR1 of Figure 47, can be eliminated. 




2 STEPS/CYCLE 



FIGURE 47. Pumping the Staircase Via Input Differentiator 



TL/H/7383-54 



190 



7.8 AN UP-DOWN STAIRCASE WAVEFORM 
GENERATOR 

A staircase waveform which first steps up and then steps 
down is provided by the circuit shown in Figure 49. An input 
pulse generator provides the pulses which cause the output 
to step up or down depending on the conduction of the 
clamp transistor, Q^ When this is ON, the "down" cur- 



rent pulse is diverted to ground and the staircase then steps 
"up". When the upper voltage trip point of Amp 2 (Schmitt 
Trigger— see section on Digital and Switching Circuits) is 
reached, Qi goes OFF and as a result of the smaller 
"down" input resistor (one-half the value of the "up" resis- 
tor, R-j) the staircase steps "down" to the low voltage trip 
point of Amp 2. The output voltage therefore steps up and 
down between the trip voltages of the Schmitt Trigger. 



ro 



0.01 (if , 



v+o— Wv 

PULSE GENERATOR 




/I 



TL/H/7383-55 



FIGURE 48. A Free Running Staircase Generator 




PULSE 
GENERATOR "ST 



SCHMITT-TRIGGER 

FIGURE 49. An Up-down Staircase Generator 



TL/H/7383-56 



191 



8.0 Designing Phase-Locked Loops 
and Voltage Controlled Oscillators 

The LM3900 can be connected to provide a low frequency 
(f < 10 kHz) phase-locked loop (PL 2 ). This is a useful circuit 
for many control applications. Tracking filters, frequency to 
DC converters, FM modulators and demodulators are appli- 
cations of a PL 2 . 

8.1 VOLTAGE CONTROLLED OSCILLATORS (VCO) 

The heart of a PL 2 is the voltage controlled oscillator (VCO). 
As the PL 2 can be used for many functions, the required 
linearity of the transfer characteristic (frequency out vs. DC 
voltage in) depends upon the application. For low distortion 
demodulation of an FM signal, a high degree of linearity is 
necessary whereas a tracking filter application would not 
require this performance in the VCO. 
A VCO circuit is shown in Figure 50. Only two amplifiers are 
required, one is used to integrate the DC input control volt- 
aQ e . Vc and tne other is connected as a Schmitt-trigger 
which monitors the output of the integrator. The trigger cir- 
cuit is used to control the clamp transistor, Qi . When Q-| is 
conducting, the input current, I2, is shunted to ground. Dur- 
ing this one-half cycle the input current, l-i, causes the out- 
put voltage of the integrator to ramp down. At the minimum 
point of the triangle waveform (output 1), the Schmitt circuit 
changes state and transistor Q-| goes OFF. The current, I2, 
is exactly twice the value of I1 (R2 = R-|/2) such that a 
charge current (which is equal to the magnitude of the dis- 
charge current) is drawn through the capacitor, C, to provide 
the increasing portion of the triangular waveform (output 1). 
The output frequency for a given DC input control voltage 
depends on the trip voltages of the Schmitt circuit (Vh and 
VJ and the components R1 and C1 (as R2 = R-|/2). The 



time to ramp down from Vh to Vl corresponds to one-half 
the period (T) of the output frequency and can be found by 
starting with the basic equation of the integrator 



V 



-4/"- 



(D 



as I1 is a constant (for a given value of Vrj) which is given by 



I1 
equation (1 ) simplifies to 

AV = 
or 



R1 
I1 



(2) 



(At) 



AVo = _l 1 
At C 

Now the time, At, to sweep from Vh to Vl becomes 
(V H -V L )C 



(3) 



Ati 



or 



T^ 2(Vh : Vl)C and 



f-I- b . 

T 2(V H -V L )C 



(4) 



Therefore, once Vh, Vl, R1 and C are fixed in value, the 
output frequency, f, is a linear function of h (as desired for a 
VCO). 




OUTPUT 2 O* 



TL/H/7383-57 



FIGURE 50. A Voltage Controlled Oscillator 



192 



i — vw 




l — VW— <► 



TL/H/7383-58 

FIGURE 51. Adding Input Common-mode 
Biasing Resistors 

The circuit shown in Figure 50 will require Vq > Vbe to 
oscillate. A value of Vq = provides fouT = 0, which may 
or may not be desired. Two common-mode input biasing 
resistors can be added as shown in Figure 51 to allow 
fouT = f MIN for V C = °- ln general, if these resistors are a 
factor of 10 larger than their corresponding resistor (R^ or 
R2) a large control frequency ratio can be realized. Actually, 
Vq could range outside the supply voltage limit of V+ and 
this circuit will still function properly. 
The output frequency of this circuit can be increased by 
reducing the peak-to-peak excursion of the triangle wave- 
form (output 1) by design of the trip points of the Sen mitt 
circuit. A limit is reached when the triangular sweep output 
waveform exceeds the slew rate limit of the LM3900 (0.5 V7 
/ms). Note that the output of the Schmitt circuit has to move 
up only one Vbe to bring the clamp transistor, Q1, ON, and 
therefore output slew rate of this circuit is not a limit. 




> 

Z 
1 

ro 



TL/H/7383-59 

FIGURE 52. Reducing Temperature Drift 

To improve the temperature stability of the VCO, a PNP 
emitter follower can be used to give approximate compen- 
sation for the Vbe's at the inputs to the amplifier (see Figure 
52). Finally to improve the mark to space ratio accuracy 
over temperature and at low control voltages, an additional 
amplifier can be added such that both reference currents 
are applied to the same type of (inverting) inputs of the 
LM3900. The circuit to accomplish this is shown within dot- 
ted lines in Figure 53. 

8.2 PHASE COMPARATOR 

A basic phase comparator is shown in Figure 54. This circuit 
provides a pulse-width modulated output voltage waveform, 
Vo 1 , which must be filtered to provide a DC output voltage 
(this filter can be the same as the one needed in the PL 2 ). 
The resistor R2 is made smaller than R1 so the ( + ) input 
serves to inhibit the (-) input signal. The center of the 




TL/H/7383-60 



FIGURE 53. Improving Mark/Space Ratio 



193 



CM 



dynamic range is indicated by the waveforms shown on the 
figure (90° phase difference between f|N and fvco)- 

:7ft 

PULSE-WIDTH MODULATION 

O v o DC 
C 

FILTER 

RANGE OF V DC 

V+ 

— <. Vqdc ^ V+ 




KLTLTI 



vo'ir-LT" 

PHASE DIAGRAM 

TL/H/7383-61 

FIGURE 54. Phase Comparator 

The filtered DC output voltage will center at 3V+ /4 and can 
range from V+ 12. to V+ as the phase error ranges from 
degrees to 180 degrees. 

8.3 A COMPLETE PHASE-LOCKED LOOP 

A phase-locked loop can be realized with three of the ampli- 
fiers as shown in Figure 55. This has a center frequency of 
approximately 3 kHz. To increase the lock range, DC gain 
can be added at the input to the VCO by using the fourth 
amplifier of the LM3900. If the gain is inverting, the limited 
DC dynamic range out of the phase detector can be in- 



creased to improve the frequency lock range. With inverting 
gain, the input to the VCO could go to zero volts. This will 
cause the output of the VCO to go high (V+) and will latch if 
applied to the ( + ) input of the phase comparator. Therefore 
apply the VCO signal to the (-) input of the phase compar- 
ator or add the common-mode biasing resistors of Figure 
51. 

8.4 CONCLUSIONS 

One LM3900 package (4 amplifiers) can provide all of the 
operations necessary to make a phase-locked loop. In addi- 
tion, a VCO is a generally useful component for other sys- 
tem applications. 

9.0 Designing Digital and Switching 
Circuits 

The amplifiers of the LM3900 can be over-driven and used 
to provide a large number of low speed digital and switching 
circuit applications for control systems which operate off of 
single power supply voltages larger than the standard 
+ 5 Vqc digital limit. The large voltage swing and slower 
speed are both advantages for most industrial control sys- 
tems. Each amplifier of the LM3900 can be thought of as "a 
super transistor" with a of 1,000,000 (25 nA input current 
and 25 mA output current) and with a non-inverting input 
feature. In addition, the active pull-up and pull-down which 
exists at the output will supply larger currents than the sim- 
ple resistor pull-ups which are used in digital logic gates. 
Finally, the low input currents allow timing circuits which 
minimize the capacitor values as large impedance levels 
can be used with the LM3900. 



,-TLT 




Ov Q2 o 



_TLT 



TL/H/7383-62 



FIGURE 55. A Phase-locked Loop 



194 



9.1 AN "OR" GATE 

An OR gate can be realized by the circuit shown in Figure 
56. A resistor (150 kfl) from V+ to the (-) input keeps the 
output of the amplifier in a low voltage saturated state for all 
inputs A, B, and C at 0V. If any one of the input signals were 
to go high (= V+) the current flow through the 75 kft input 
resistor will cause the amplifier to switch to the positive out- 
put saturation state (Vo = V+). The current loss through 
the other input resistors (which have an input in the low 
voltage state) represents an insignificant amount of the total 
input current which is provided by the, at least one, high 
voltage input. More than three inputs can be OR'ed if de- 
sired. 




TL/H/7383-63 

FIGURE 56. An "OR" Gate 

The "fan-out" or logical drive capability is large (50 gates if 
each gate input has a 75 kfl resistor) due to the 10 mA 
output current capability of the LM3900. A NOR gate can be 
obtained by interchanging the inputs to the LM3900. 

9.2 AN "AND" GATE 

A three input AND gate is shown in Figure 57. This gate 
requires all three inputs to be high in order to have sufficient 
current entering the (+) input to cause the output of the 
amplifier to switch high. The addition of R2 causes a smaller 
current to enter the (+) input when only two of the inputs 
are high. (A two input AND gate would not require a resistor 




f = A»B»C 

TL/H/7383-64 



FIGURE 57. An "AND" Gate 



as R2). More than three inputs becomes difficult with this 
resistor summing approach as the (+) input is too close to 
having the necessary current to switch just prior to the last 
input going high. For a larger fan-in an input diode network 



(similar to DTL) is recommended as shown in Figure 58. 
Interchange the inputs for a NAND gate. 

v + 



10 




f = A»B»OD«E«F 



All Diodes 1 N914 or Equiv. 



TL/H/7383-65 



FIGURE 58. A Large Fan-in "AND" Gate 

9.3 A BI-STABLE MULTIVIBRATOR 

A bi-stable multivibrator (as asynchronous RS flip-flop) can 
be realized as shown in Figure 59. Positive feedback is pro- 
vided by resistor R4 which causes the latching. A positive 
pulse at the "set" input causes the output to go high and a 
"reset" positive pulse will return the output to essentially 
0V DC . 




TL/H/7383-66 



FIGURE 59. A Bi-stable Multivibrator 



195 



CM 



9.4 TRIGGER FLIP FLOPS 

Trigger flip flops are useful to divide an input frequency as 
each input pulse will cause the output of a trigger flip flop to 
change state. Again, due to the absence of a clocking signal 
input, this is for an asynchronous logic application. A circuit 
which uses only one amplifier is shown in Figure 60. Steer- 
ing of the differentiated positive input trigger is provided by 
the diode CR2. For a low output voltage state, CR2 shunts 
the trigger away from the (-) input and resistor R3 couples 
this positive input trigger to the (+) input terminal. This 
causes the output to switch high. The high voltage output 
state now keeps CR2 OFF and the smaller value of (R5 + 
R6) compared with R3 causes a larger positive input trigger 



to be coupled to the (-) input which causes the output to 
switch to the low voltage state. 

A second trigger flip flop can be made which consists of two 
amplifiers and also provides a complementary output. This 
connection is shown in Figure 61. 

9.5 MONOSTABLE MULTIVIBRATORS (ONE-SHOTS) 

Monostable multivibrators can be made using one or two of 
the amplifiers of the LM3900. In addition, the output can be 
designed to be either high or low in the quiescent state. 
Further, to increase the usefulness, a one-shot can be de- 
signed which triggers at a particular DC input voltage level 
to serve the dual role of providing first a comparator and 
then a pulse generator. 



V,nO 



C1 
100pF 



R3 
200K 

-VSAr 




R5 R6 

51K 51K 



R4 
1M 



ism 



ji_n_r t" 

to '1 tj _L 




jT CR1 ' 



TL/H/7383-67 



FIGURE 60. A Trigger Flip Flop 

0.001 /iF 0.001 (if 



OUTPUT 1 O— • 



1_TL 




O OUTPUT 2 



lOOpF 



T -nnr 



TL/H/7383-68 



FIGURE 61. A Two-amplifier Trigger Flip Flop 



196 



7LT 




„T1_ 



PW 2= 2 X 10C 
• Speeds Recovery 

FIGURE 62. A One-shot Multivibrator 



TL/H/7383-69 



9.5.1 A TWO-AMPLIFIER ONE-SHOT 

A circuit for a two-amplifier one-shot is shown in Figure 62. 
As the resistor, R2, from V+ to the (-) input is smaller than 
R 5 (from V+ to the (+) input), amplifier 2 will be biased to a 
low-voltage output in the quiescent state. As a result, no 
current is supplied to the (-) input of amplifier 1 (via R3) 
which causes the output of this amplifier to be in the high 
voltage state. Capacitor C<t therefore has essentially the full 
V+ supply voltage across it (V+ -2 Vbe)- Now when a dif- 
ferentiated trigger (due to C2) causes amplifier 1 to be driv- 
en ON (output voltage drops to essentially zero volts) this 
negative transient is coupled (via C1) to the (-) input of 
amplifier 2 which causes the output of this amplifier to be 
driven high (to positive saturation). This condition remains 
while C1 discharges via (R-t) from approximately V + to ap- 
proximately V+/2. This time interval is the pulse width 
(PW). After C1 no longer diverts sufficient current of R2 
away from the (-) input of amplifier 2 (i.e., C-| is discharged 
to approximately V+/2 V) the stable DC state is restored— 
amplifier 2 output low and amplifier 1 output high. 
This circuit can be rapidly re-triggered due to the action of 
the diode, CR-|. This re-charges C1 as amplifier 1 drives full 
output current capability (approximately 10 mA) through C1, 
CR1 and into the saturated (-) input of amplifier 2 to 
ground. The only time limit is the 10 mA available from am- 
plifier 1 and the value of C^ If a rapid reset is not required, 
CR1 can be omitted. 




Trips At V| N at 0.8 V + 
v * V| N must fall < 0.8 V+ prior to t 2 

TL/H/7383-70 

FIGURE 63. A One-shot Multivibrator 
with an Input Comparator 



9.5.2 A COMBINATION ONE-SHOT/COMPARATOR 
CIRCUIT 

In many applications a pulse is required if a DC input signal 
exceeds a predetermined value. This exists in free-running 
oscillators where after a particular output level has been 
reached a reset pulse must be generated to recycle the 
oscillator. This double function is provided with the circuit of 
Figure 63. The resistors R 5 and R6 of amplifier 1 provide the 
inputs to a comparator and, as shown, an input signal, V|n, 
is compared with the supply voltage, V+. The output volt- 
age of amplifier 1 is normally in a high voltage state and will 
fall and initiate the generation of the output pulse when Vin 
is R6/R5 V+ or approximately 80% of V+. To keep V| N 
from disturbing the pulse generation it is required that V|n 
fall to less than the trip voltage prior to the termination of 
the output pulse. This is the case when this circuit is used to 
generate a reset pulse and therefore this causes no prob- 
lems. 

9.5.3 A ONE-AMPLIFIER ONE-SHOT (POSITIVE PULSE) 

A one-shot circuit can be realized using only one amplifier 
as shown in Figure 64. 

The resistor R2 keeps the output in the low voltage state. A 
differentiated positive trigger causes the output to switch to 
the high voltage state and resistor R5 latches this state. The 
capacitor, C1, charges from essentially ground to approxi- 
mately V+ /4 where the circuit latches back to the quiescent 
state. The diode, CRi, is used to allow a rapid re-triggering. 




*o— |£-vvv 



TL/H/7383-71 

FIGURE 64. A One-amplifier One-shot (Positive Output) 



197 



9.5.4 A ONE-AMPLIFIER ONE-SHOT (NEGATIVE PULSE) 

A one-amplifier one-shot multivibrator which has a quies- 
cent state with the output high and which falls to zero volts 
for the pulse duration is shown in Figure 65. 




\TT 



10M 

v*0 WV 



)o— |£— VvV— 



TL/H/7383-72 

FIGURE 65. A One-Amplifier One-Shot 
(Negative Output) 

The sum of the currents through R2 and R3 keeps the (-) 
input at essentially ground. This causes Vrj to be in the high 
voltage state. A differentiated negative trigger waveform 
causes the output to switch to the low voltage state. The 
large voltage across C1 now provides input current via R1 to 
keep the output low until C-| is discharged to approximately 
V+/10. At this time the output switches to the stable high 
voltage state. 

If the R4C2 network is moved to the (-) input terminal, the 
circuit will trigger on a differentiated positive trigger wave- 
form. 

9.6 COMPARATORS 

The voltage comparator is a function required for most sys- 
tem operations and can easily be performed by the LM3900. 
Both an inverting and a non-inverting comparator can be 
obtained. 

9.6.1 A COMPARATOR FOR POSITIVE 
INPUT VOLTAGES 

The circuit in Figure 66 is an inverting comparator. To insure 
proper operation, the reference voltage must be larger than 




No Positive 
Voltage Limit 

TL/H/7383-73 

FIGURE 66. An Inverting Voltage Comparator 



Vbe, but there is no upper limit as long as the input resistor 
is large enough to guarantee that the input current will not 
exceed 200 joiA. 

9.6.2 A COMPARATOR FOR NEGATIVE 
INPUT VOLTAGES 

Adding a common-mode biasing network to the comparator 
in Figure 66 makes it possible to compare voltages between 
zero and one volt as well as the comparison of rather large 
negative voltages, Figure 67. When working with negative 
voltages, the current supplied by the common-mode net- 
work must be large enough to satisfy both the current drain 
demands of the input voltages and the bias current require- 
ment of the amplifier. 




TL/H/7383-74 

FIGURE 67. A Non-inverting Low-voltage Comparator 

9.6.3 A POWER COMPARATOR 

When used in conjunction with an external transistor, this 
power comparator will drive loads which require more cur- 
rent than the IC amplifier is capable of supplying. Figure 68 
shows a non-inverting comparator which is capable of driv- 
ing a 1 2V, 40 mA panel lamp. 




♦v*o— VSAr* 



TL/H/7383-75 

FIGURE 68. A Non-inverting Power Comparator 

9.6.4 A MORE PRECISE COMPARATOR 

A more precise comparator can be designed by using a sec- 
ond amplifier such that the input voltages of the same type 
of inputs are compared. The (-) input voltages of two am- 
plifiers are naturally more closely matched initially and track 
well with temperature changes. The comparator of Figure 
69 uses this concept. 



198 



+Vri, 




TL/H/7383-76 

FIGURE 69. A More Precise Comparator 

The current established by Vref at the inverting input of 
amplifier 1 will cause transistor Qi to adjust the value of Va 
to supply this current. This value of Va will cause an equal 
current to flow into the non-inverting input of amplifier 2. 
This current corresponds more exactly to the reference cur- 
rent of amplifier 1 . 

A differential input stage can also be added to the LM3900 
(see section 10.16) and the resulting circuit can provide a 
precision comparator circuit. 

9.7 SCHMITT TRIGGERS 

Hysteresis may be designed into comparators which use the 
LM3900 as shown in Figure 70. 



The lower switch point for the inverting Schmitt-Trigger is 
determined by the amount of current flowing into the posi- 
tive input with the output voltage low. When the input cur- 
rent, I3, drops below the level required by the current mirror, 
the output will switch to the high limit. With Vo high, the 
current demanded by the mirror is increased by a fixed 
amount, I2. As a result, the I3 required to switch the output 
increases this same amount. Therefore, the switch points 
are determined by selecting resistors which will establish 
the required currents at the desired input voltages. Refer- 
ence current (I1) and feedback current (l 2 ) are set by the 
following equation. 

V+ -<f> 
h = 



l 2 = 



Rb 

v O MAX ~ <t> 

Rf 



By adjusting the values of Rb, Rf. and Rin, the switching 
values of V|n may be set to any levels desired. 
The non-inverting Schmitt Trigger works in the same way 
except that the input voltage is applied to the ( + ) input. The 
range of Vin may be very large when compared with the 
operating voltage of the amplifier. 

10.0 Some Special Circuit 
Applications 

This section contains various special circuits which did not 
fit the order of things or which are one-of-a-kind type of 
applications. 

10.1 CURRENT SOURCES AND SINKS 

The amplifiers of the LM3900 can be used in feedback 
loops which regulate the current in external PNP transistors 
to provide current sources or in external NPN transistors to 
provide current sinks. These can be multiple sources or sin- 
gle sources which are fixed in value or made voltage vari- 
able. 





TL/H/7383-77 



(a) Inverting 





2 



TL/H/7383-78 



(b) Non-inverting 

FIGURE 70. Schmitt Triggers 



199 



10.1.1 A FIXED CURRENT SOURCE 

A multiple fixed current source is provided by the circuit of 
Figure 71. A reference voltage (1 Vqc) is established across 
resistor R3 by the resistive divider (R3 and R4). Negative 
feedback is used to cause the voltage drop across R-| to 
also be 1 Vqc- This controls the emitter current of transistor 
Q-\ and if we neglect the small current diverted into the (-) 
input via the 1M input resistor (13.5 jxA) and the base cur- 
rent of Q1 and Q2 (an additional 2% loss if the ^ of these 
transistors is 100), essentially this same current is available 
out of the collector of Q1. 

Larger input resistors can be used to reduce current loss 
and a Darlington connection can be used to reduce errors 
due to the 13 of Q1. 




TL/H/7383-79 

FIGURE 71. Fixed Current Sources 

The resistor, R2, can be used to scale the collector current 
of Q2 either above or below the 1 mA reference value. 

10.1.2 A VOLTAGE VARIABLE CURRENT SOURCE 

A voltage variable current source is shown in Figure 72. The 
transconductance is -(I/R2) as the voltage gain from the 
input terminal to the emitter of Q-| is - 1 . For a Vin = Vqc 
the output current is essentially zero mA DC. The resistors 
R1 and R6 guarantee that the amplifier can turn OFF tran- 
sistor Q^ 




♦v«o— W/Nr 



TL/H/7383-80 

FIGURE 72. A Voltage Controlled Current Source 

10.1.3 A FIXED CURRENT SINK 

Two current sinks are shown in Figure 73. The circuit of 
Figure 73(a) requires only one resistor and supplies an out- 



put current which is directly proportional to this R value. A 
negative temperature coefficient will result due to the 0.5 
Vqc reference being the base-emitter junction voltage of 
the (-) input transistor. If this temperature coefficient is ob- 
jectionable, the circuit of Figure 73(b) can be employed. 




TL/H/7383-81 



(a) A Simple Current Sink 




TL/H/7383-82 



(b) Reducing Temperature Drift Of Iq 



FIGURE 73. Fixed Current Sinks 

10.1.4 A VOLTAGE VARIABLE CURRENT SINK 

A voltage variable current sink is shown in Figure 74. The 
output current is 1 mA per volt of Vin (as R5 = 1 kft and the 
gain is + 1 ). This circuit provides approximately mA output 
current for Vin = Vqc- 



l * t idA/VOLT IV M ) 




TL/H/7383-83 

FIGURE 74. A Voltage Controlled Current Sink 

10.2 OPERATION FROM ± 15 V DC POWER SUPPLIES 

If the ground pin (no. 7) is returned to a negative voltage 
and some changes are made in the biasing circuits, the 
LM3900 can be operated from ±15 Vqc power supplies. 



200 



10.2.1 AN AC AMPLIFIER OPERATING WITH ± 15 Vdc 
POWER SUPPLIES 

An AC coupled amplifier is shown in Figure 75. The biasing 
resistor, Rq, is now returned to ground and both inputs bias 
at one Vbe above the -Vgg voltage (approximately -15 
Vdc)- 

Rl 

1M 

— vv\ 




TL/H/7383-84 

FIGURE 75. An AC Amplifier Operating With ± 15 Vdc 

With Rf = Rb, Vo will bias at approximately Vqc to allow a 
maximum output voltage swing. As pin 7 is common to all 
four of the amplifiers which are in the same package, the 
other amplifiers are also biased for operation off of ±15 
Vdc- 

10.2.2 A DC AMPLIFIER OPERATING WITH ± 15 Vdc 
POWER SUPPLIES 

Biasing a DC amplifier is more difficult and requires that the 
± power supplies be complementary tracking (i.e., 
I + Vccl ~ I _v eeI)- Tne operation of this biasing can be 
understood if we start by first considering the amplifier with- 
out including the feedback resistors, as shown in Figure 76. 
If Rt = R 2 = R3 + R4 = 1 Mil and | + V C cl = |— V EE I. 

+15Voc* 



V.N 



(INVERTING O + ^^— 
INPUT) 



'Complementary Tracking — I- 




Vos ADJUST 



then the current, I, will bias V|n at zero volts DC (resistor R 4 
can be used to adjust this). The diode, CR1, has been add- 
ed for temperature compensation of this biasing. Now, if we 
include these biasing resistors, we have a DC amplifier with 
the input biased at approximately zero volts. If feedback 
resistors are added around this biased amplifier we get the 
schematic shown in Figure 77. 



"in 
200K 

v.nO— VSAr 



i 



n 



+ yS Biased 

IS LM3900 From 

Figure 76 



TL/H/7383-86 

FIGURE 77. A DC Amplifier Operating with ± 15 Vdc 

This is a standard inverting DC amplifier connection. The 
(+) input is "effectively" at ground and the biasing shown in 
Figure 76 is used to take care of DC levels at the inputs. 

10.3 TACHOMETERS 

Many pulse averaging tachometers can be built using the 
LM3900. Inputs can be voltage pulses, current pulses or the 
differentiated transitions of squarewaves. The DC output 
voltage can be made to increase with increasing input fre- 
quency, can be made proportional to twice the input fre- 
quency (frequency doubling for reduced output ripple), and 
can also be made proportional to either the sum or the dif- 
ference between two input frequencies. Due to the small 
bias current and the high gain of the LM3900, the transfer 
function is linear between the saturation states of the ampli- 
fier. 

10.3.1 A BASIC TACHOMETER 

If an RC averaging network is added from the output to the 

(-) input, the basic tachometer of Figure 78 results. Current 

pulse inputs will provide the desired transfer function shown 

on the figure. Each input current pulse causes a small 

change in the output voltage. Neglecting the effects of R we 

have 

lAt 
AVo«- 

The inclusion of R gives a discharge path so the output 
voltage does not continue to integrate, but rather provides 
the time dependency which is necessary to average the in- 
put pulses. If an additional signal source is simply placed in 
parallel with the one shown, the output becomes proportion- 
al to the sum of these input frequencies. If this additional 
source were applied to the (-) input, the output voltage 
would be proportional to the difference between these input 
frequencies. Voltage pulses can be converted to current 
pulses by using an input resistor. A series isolating diode 
should be used if a signal is applied to the (-) input to 
prevent loading during the low voltage state of this input 
signal. 



TL/H/7383-85 

FIGURE 76. DC Biasing for ± 15 Vdc Operation 



201 




TL/H/7383-87 

FIGURE 78. A Basic Tachometer 
10.3.2 EXTENDING V UT (MINIMUM) TO GROUND 

The output voltage of the circuit of Figure 78 does not go to 
ground level but has a minimum value which is equal to the 
V B e of the (-) input (0.5 V D c). If it is desired that the output 
voltage go exactly to ground, the circuit of Figure 79 can be 
used. Now with Vin = V D c, Vo = Vdc due to the 
addition of the common-mode biasing resistors (1 80 kfl). 



It OK R 2MK 



TtPl 




TL/H/7383-88 

FIGURE 79. Adding Biasing to Provide V = V DC 

The diode, CRi, allows the output to go below Vqe SAT of 
the output, if desired (a load is required to provide a DC path 
for the biasing current flow via the R of the averaging net- 
work). 

10.3.3 A FREQUENCY DOUBLING TACHOMETER 

To reduce the ripple on the DC output voltage, the circuit of 
Figure 80 can be used to effectively double the input fre- 
quency. Input pulses are not required, a squarewave is all 
that is needed. The operation of the circuit is to average the 
charge and discharge transient currents of the input capaci- 
tor, C|n. The resistor, R|n, is used to convert the voltage 
pulses to current pulses and to limit the surge currents (to 
approximately 200 fxA peak — or less if operating at high 
temperatures). 

When the input voltage goes high, the charging current of 
C|N. 'chg enters the (+) input, is mirrored about ground and 
is drawn from the RC averaging network into the (-) input 
terminal. When the input voltage goes back to ground, the 



discharge current of Cin, (discharge will also be drawn 
from the RC averaging network via the now conducting di- 
ode, CR-|. This full wave action causes two current pulses to 
be drawn through the RC averaging network for each cycle 
of the input frequency. 




TL/H/7383-89 

FIGURE 80. A Frequency Doubling Tachometer 
10.4 A SQUARING AMPLIFIER 

A squaring amplifier which incorporates symmetrical hyster- 
esis above and below the zero output state (for noise immu- 
nity) is often needed to amplify the low level signals which 
are provided by variable reluctance transducers. In addition, 
a high frequency roll-off (low pass characteristic) is desir- 
able both to reduce the natural voltage buildup at high fre- 
quencies and to also filter high frequency input noise distur- 
bances. A simple circuit which accomplishes this function is 
shown in Figure 81. The input voltage is converted to 



run 




O V 



TL/H/7383-90 

FIGURE 81. A Squaring Amplifier with Hysteresis 

input currents by using the input resistors, R|n. Common- 
mode biasing is provided by Rbi and Rb2- Finally positive 
feedback (hysteresis) is provided by Rf. The large source 
resistance, Rjn, provides a low pass filter due to the "Miller- 
effect" input capacitance of the amplifier (approximately 
0.002 jliF). The amount of hysteresis and the symmetry 
about the zero volt input are controlled by the positive feed- 
back resistor, Rf, and Rbi and Rb2- With the values shown 
in Figure 81 the trip voltages are approximately ±150 mV 
centered about the zero output voltage state of the trans- 
ducer (at low frequencies where the low pass filter is not 
attenuating the input signal). 



202 



10.5 A DIFFERENTIATOR 

An input differentiating capacitor can cause the input of the 
LM3900 to swing below ground and actuate the input ciamp 
circuit. Again, common-mode biasing can be used to pre- 
vent this negative swing at the input terminals of the 
LM3900. The schematic of a differentiator circuit is shown in 
Figure 82. Common-mode biasing is provided by Rgi and 



A V = 




Hhr 



_n_n 



TL/H/7383-91 

FIGURE 82. A Differentiator Circuit 

Rb2- The feedback resistor, Rf, is one-half the value of Rin 
so the gain is 1/2. The output voltage will bias at V+/2 
which thereby allows both a positive and a negative swing 
above and below this bias point. The resistor, Rin, keeps 
the negative swing isolated from the (-) input terminal and 
therefore both inputs remain biased at + Vbe- 

10.6 A DIFFERENCE INTEGRATOR 

A difference integrator is the basis of many of the sweep 
circuits which can be realized using the LM3900 operating 
on only a single power supply voltage. This circuit can also 
be used to provide the time integral of the difference be- 
tween two input waveforms. The schematic of the differ- 
ence integrator is shown in Figure 83. 



im i r^ 

"i o— wv-4 — 




0.1 rf 



TL/H/7383-92 

FIGURE 83. A Difference Integrator 

This is a useful component for DC feedback loops as both 
the comparison to a reference and the integration take 
place in one amplifier. 



10.7 A LOW DRIFT SAMPLE AND HOLD CIRCUIT 

In sample and hold applications a very low input biasing 
current is required. This is usually achieved by using a FET 
transistor or a special low input current IC op amp. The 
existence of many matched amplifiers in the same package 
allows the LM3900 to provide some interesting low "equiva- 
lent" input biasing current applications. 

10.7.1 REDUCING THE "EFFECTIVE" INPUT BIASING 
CURRENT 

One amplifier can be used to bias one or more additional 
amplifiers as shown in Figure 84. 

Ib -effective- 




ADJUST Is -EFFECTIVE- 
R3 <~ ^ TO ZERO 

2M 



R1 = R2 



Auxilliary amp for 
biasing amp 1 



TL/H/7383-93 

FIGURE 84. Reducing l B "Effective" to Zero 

The input terminal of Amp. 1 will only need to supply the 
signal current if the DC biasing current, >bi> is accurately 
supplied via R-|. The adjustment, R3, allows a zeroing of "Ib 
effective" but simply omitting R3 and letting R-| = R2 (and 
relying on amplifier symmetry) can cause Ib "effective" to 
be less than Ib/10 (3 nA). This is useful in circuit applica- 
tions such as sample and hold, where small values of Ib 
"effective" are desirable. 

10.7.2 A LOW DRIFT RAMP AND HOLD CIRCUIT 

The input current reduction technique of the previous sec- 
tion allows a relatively simple ramp and hold circuit to be 
built which can be ramped up or down or allowed to remain 
at any desired output DC level in a "hold" mode. This is 
shown in Figure 85. If both inputs are at Vdc the circuit is 
in a hold mode. Raising either input will cause the DC output 
voltage to ramp either up or down depending on which one 
goes positive. The slope is a function of the magnitude of 
the input voltage and additional inputs can be placed in par- 
allel, if desired, to increase the input control variables. 



203 



CM 

I*- 




Vo 



FIGURE 85. A Low-Drift Ramp and Hold Circuit 



TL/H/7383-94 



10.7.3 SAMPLE-HOLD AND COMPARE WITH NEW + V| N 

An example of using the circuit of the previous section is 
shown in Figure 86 where clamping transistors, Q-\ and Q2, 
put the circuit in a hold mode when they are driven ON. 
When OFF the output voltage of Amp. 1 can ramp either up 
or down as needed to guarantee that the output voltage of 



Amp. 1 is equal to the DC input voltage which is applied to 
Amp. 3. Resistor R1 provides a fixed "down" ramp current 
which is balanced or controlled via the comparator, Amp. 3, 
and the resistor R 4 . When Q-\ and Q 2 are OFF a feedback 
loop guarantees that V i (from Amp. 1) is equal to + Vin (to 
Amp. 3). Amplifier 2 is used to supply the input biasing cur- 
rent to Amp. 1 . 




-Vo, = V M (H0LD) 
° HtRt,<;t<:t2 



TL/H/7383-95 



FIGURE 86. Sample-Hold and Compare with New + Vin 



204 



The stored voltage appears at the output, V01 of Amp. 1 , 
and as Amp. 3 is active, a continued comparison is made 
between Vqi and Vin and the output of Amp. 3 fully 
switches based on this comparison. A second loop could 
force Vin to be maintained at the stored value (V01) by mak- 
ing use of V02 as an error signal for this second loop. There- 
fore, a control system could be manually controlled to bring 
it to a particular operating condition; then, by exercising the 
hold control, the system would maintain this operating con- 
dition due to the analog memory provided by Voi- 

10.8 AUDIO MIXER OR CHANNEL SELECTOR 

The multiple amplifiers of the LM3900 can be used for audio 
mixing (many amplifiers simultaneously providing signals 
which are added to generate a composite output signal) or 
for channel selection (only one channel enabled at a time). 



Three amplifiers are shown being summed into a fourth am- 
plifier in Figure 87. 

If a power amplifier were available, all four amplifiers could 
feed the single input of the power amplifier. For audio mixing 
all amplifiers are simultaneously active. Particular amplifiers 
can be gated OFF by making use of DC control signals 
which are applied to the (+) inputs to provide a channel 
select feature. As shown on Figure 87, Amp. 3 is active (as 
sw 3 is closed) and Amps. 1 and 2 are driven to positive 
output voltage saturation by the 5.1 M which is applied to the 
( + ) inputs. The DC output voltage bias level of the active 
amplifier is approximately 0.8 Vdc and could be raised if 
larger signal levels were to be accommodated. Frequency 
shaping networks can be added either to the individual am- 
plifiers or to the common amplifier, as desired. Switching 
transients may need to be filtered at the DC control points if 
the output amplifier is active during the switching intervals. 



IS) 




TL/H/7383-96 



FIGURE 87. Audio Mixing or Selection 



205 



10.9 A LOW FREQUENCY MIXER 

The diode which exists at the ( + ) input can be used for non- 
linear signal processing. An example of this is a mixer which 
allows two input frequencies to produce a sum and differ- 
ence frequency (in addition to other high frequency compo- 
nents). Using the amplifier of the LM3900, gain and filtering 
can also be accomplished with the same circuit in addition 
to the high input impedance and low output impedance ad- 
vantages. The schematic of Figure 88 shows a mixer with a 
gain of 1 and a low pass single pole filter (1 M and 1 50 pF 
feedback elements) with a corner frequency of 1 kHz. With 
one signal larger in amplitude, to serve as the local oscilla- 
tor input (Vi), the transconductance of the input diode is 
gated at this rate (f|). A small signal (V2) can now be added 
at the second input and the difference frequency is filtered 
from the composite resulting waveform and is made avail- 
able at the output. Relatively high frequencies can be ap- 
plied at the inputs as long as the desired difference frequen- 
cy is within the bandwidth capabilities of the amplifier and 
the RC low pass filter. 



(«2-'l) 




TL/H/7383-97 

FIGURE 88. A Low Frequency Mixer 
10.10 A PEAK DETECTOR 

A peak detector is often used to rapidly charge a capacitor 
to the peak value of an input waveform. The voltage drop 
across the rectifying diode is placed within the feedback 
loop of an op amp to prevent voltage losses and tempera- 
ture drifts in the output voltage. The LM3900 can be used as 
a peak detector as shown in Figure 89. The feedback resis- 
tor, Rf, is kept small (1 Mn) so that the 30 nA base current 
will cause only a + 30 mV error in Vo- This feedback resis- 



tor is constantly loading C in addition to the current drawn 
by the circuitry which samples Vo These loading effects 
must be considered when selecting a value for C. 
The biasing resistor, Rq, allows a minimum DC voltage to 
exist across the capacitor and the input resistor, Rin, can be 
selected to provide gain to the input signal, 
v* 



1— \C— VVV i»+^>^ cm 

Q (i ^ LM3900 ^^ ► ! * 

I 1M 

I <VAA< I 



FIGURE 89. A Peak Detector 



"rx 



O Vo 



TL/H/7383-98 



10.11 POWER CIRCUITS 

The amplifier of the LM3900 will source a maximum current 
of approximately 1 mA and will sink maximum currents of 
approximately 80 mA (if overdriven at the (-) input). If the 
output is driven to a saturated state to reduce device dissi- 
pation, some interesting power circuits can be realized. 
These maximum values of current are typical values for the 
unit operating at 25°C and therefore have to be de-rated for 
reliable operation. For fully switched operation, amplifiers 
can be paralleled to increase current capability. 

10.11.1 LAMP AND/OR RELAY DRIVERS (<: 30 mA) 

Low power lamps and relays (as reed relays) can be directly 
controlled by making use of the larger value of sink current 
than source current. A schematic is shown in Figure 90 
where the input resistor, R, is selected such that Vin sup- 
plies at least 0.1 mA of input current. 



I| N £ 0.1mA 




OFF OFF 



20 mA 12V Lamp or 
14 mA 10V Lamp or 
Reed Relay Coil 



TL/H/7383-9 

FIGURE 90. Sinking 20 to 30 mA Loads 



206 




> 
z 

I 



Or Relay Load With Diode 
FIGURE 91. Boosting to 300 mA Loads 



TL/H/7383-A0 



10.1 1.2 LAMP AND/OR RELAY DRIVERS (<; 300 mA) 

To increase the power capability, an external transistor can 
be added as shown in Figure 91. The resistors Ri and R2 
hold Q1 OFF when the output of the LM3900 is high. The 
resistor, R2, limits the base drive when Q1 goes ON. It is 
required that pin 14 tie to the same power supply as the 
emitter of Q-| to guarantee that Q-i can be held OFF. If an 
inductive load is used, such as a relay coil, a backswing 
diode should be added to prevent large inductive voltage 
kicks during the switching interval, ON to OFF. 

10.1 1.3 POSITIVE FEEDBACK OSCILLATORS 

If the LM3900 is biased into the active region and a reso- 
nant circuit is connected from the output to the (+) input, a 
positive feedback oscillator results. A driver for a piezoelec- 
tric transducer (a warning type of noise maker) is shown in 
Figure 92. The resistors R1 and R2 bias the output voltage 
at V+/2 and keep the amplifier active. Large currents can 
be entered into the ( + ) input and negative currents (or cur- 
rents out of this terminal) are provided by the epi-substrate 
diode of the IC fabrication. 




•-oHLH-o- 1 

\ PIEZOELECTRIC 
R2 TRANSDUCER 

200K 



Audible output 
V (15Voc) warning sound 

TL/H/7383-A1 

FIGURE 92. Positive Feedback Power Oscillators 

When one of the amplifiers is operated in this large negative 
input current mode, the other amplifiers will be disturbed 
due to interaction. Multiple sounds may be generated as a 
result of using two or more transducers in various combina- 
tions, but this has not been investigated. Other two-terminal 
RC, RLC or piezoelectric resonators can be connected in 
this circuit to produce an oscillator. 



10.12 HIGH VOLTAGE OPERATION 

The amplifiers of the LM3900 can drive an external high 
voltage NPN transistor to provide a larger output voltage 
swing (as for an electrostatic CRT deflection system) or to 
operate off of an existing high voltage power supply (as the 
+ 98 Vqc rectified line). Examples of both types of circuits 
are presented in this section. 

10.12.1 A HIGH VOLTAGE INVERTING AMPLIFIER 

An inverting amplifier with an ouput voltage swing from es- 
sentially Vqc to + 300 Vqc is shown in Figure 93. The 
transistor, Q1, must be a high breakdown device as it will 
have the full HV supply across it. The biasing resistor R 3 is 
used to center the transfer characteristic and the gain is the 
ratio of R2 to R-|. The load resistor, R|_, can be increased, if 
desired, to reduce the HV current drain. 

+HV (+300Voc) 



OVo 




+5 +10 



V.N 

TL/H/7383-A2 

FIGURE 93. A High Voltage Inverting Amplifier 



207 



CM 

I*. 



V + (+15V oc ) 



+HV (+300V OC I 



R1 
330K 
+v, N o— -A/W 



■I- 




OVo 



FIGURE 94. A High Voltage Non-Inverting Amplifier 



TL/H/7383-A3 



10.12.2 A HIGH VOLTAGE NON-INVERTING AMPLIFIER 

A high voltage non-inverting amplifier is shown in Figure 94. 
Common-mode biasing resistors (R2) are used to allow Vin 
to go to Vdc- The output voltage, Vo, will not actually go 
to zero due to Rg, but should go to approximately 0.3 Vdc- 
Again, the gain is 30 and a range of the input voltage of from 
to +10 Vqc wi, l cause the output voltage to range from 
approximately to + 300 Vdc- 



10.12.3 A LINE OPERATED AUDIO AMPLIFIER 

An audio amplifier which operates off a +98 Vdc power 
supply (the rectified line voltage) is often used in consumer 
products. The external high voltage transistor, Q1 of Figure 
95, is biased and controlled by the LM3900. The magnitude 
of the DC biasing voltage which appears across the emitter 
resistor of Q1 is controlled by the resistor which is placed 
from the (-) input to ground. 




FIGURE 95. A Line Operated Audio Amplifier 



TL/H/7383-A4 



208 



10.13 TEMPERATURE SENSING 

The LM3900 can be used to monitor the junction tempera- 
ture of the monolithic chip as shown in Figure 96(a). Amp. 1 
will generate an output voltage which can be designed to 
undergo a large negative temperature change by design of 
Ri and R2. The second amplifier compares this temperature 
dependent voltage with the power supply voltage and goes 
high at a designed maximum Tj of the IC. 



For remote sensing, an NPN transistor, Q1 of Figure 96(b), 
is connected as an N Vbe generator (with R3 and R5) and 
biased via R1 from the power supply voltage, V+. The 
LM3900 again compares this temperature dependent volt- 
age with the supply voltage and can be designed to have 
Vo go high at a maximum temperature of the remote tem- 
perature sensor, Q1 . 



10 




T, SENSE 



COMPARATOR 



TL/H/7383-A6 



(a) IC Tj Monitor 




TL/H/7383-A7 



(b) Remote Temperature Sense 

FIGURE 96. Temperature Sensing 



209 




O V 



_n_r 



"c SWEEP 



v+O— VNAr-# 

FIGURE 97. A "Programmable Unijunction" 



TL/H/7383-A8 



10.14 A "PROGRAMMABLE UNIJUNCTION" 

If a diode is added to the Schmitt Trigger, a "programmable 
unijunction" function can be obtained as shown in Figure 
97. For a low input voltage, the output voltage of the 
LM3900 is high and CRI is OFF. When the input voltage 
rises to the high trip voltage, the output falls to essentially 
0V and CRI goes ON to discharge the input capacitor, C. 
The low trip voltage must be larger than approximately 1 V to 
guarantee that the forward drop of CRI added to the output 
voltage of the LM3900 will be less than the low trip voltage. 
The discharge current can be increased by using smaller 
values for R2 to provide pull-down currents larger than the 
1 .3 mA bias current source. The trip voltages of the Schmitt 
Trigger are designed as shown in section 9.7. 

10.15 ADDING A DIFFERENTIAL INPUT STAGE 

A differential amplifier can be added to the input of the 
LM3900 as shown in Figure 98. This will increase the gain 
and reduce the offset voltage. Frequency compensation 
can be added as shown. The BVebo limit of the input tran- 
sistors must not be exceeded during a large differential in- 
put condition, or diodes and input limiting resistors should 
be added to restrict the input voltage which is applied to the 
bases of Q1 and Q2 to +V D . 



The input common-mode voltage range does not go exactly 
to ground as a few tenths of a volt are needed to guarantee 
that Q1 or Q2 will not saturate and cause a phase change 
(and a resulting latch-up). The input currents will be small, 
but could be reduced further, if desired, by using FETS for 
Q1 and Q2. This circuit can also be operated off of ± 1 5 Vqc 
supplies. 




TL/H/7383-A9 

FIGURE 98. Adding a Differential Input Stage 



210 



LM139/LM239/LM339 
A Quad of Independently 
Functioning Comparators 



National Semiconductor 
Application Note 74 




INTRODUCTION 

The LM139/LM239/LM339 family of devices is a monolithic 
quad of independently functioning comparators designed to 
meet the needs for a medium speed, TTL compatible com- 
parator for industrial applications. Since no antisaturation 
clamps are used on the output such as a Baker clamp or 
other active circuitry, the output leakage current in the OFF 
state is typically 0.5 nA. This makes the device ideal for 
system applications where it is desired to switch a node to 
ground while leaving it totally unaffected in the OFF state. 
Other features include single supply, low voltage operation 
with an input common mode range from ground up to ap- 
proximately one volt below Vqc- The output is an uncommit- 
ted collector so it may be used with a pull-up resistor and a 
separate output supply to give switching levels from any 
voltage up to 36V down to a Vqe sat above ground (approx. 
100 mV), sinking currents up to 15 mA. In addition it may be 
used as a single pole switch to ground, leaving the switched 
node unaffected while in the OFF state. Power dissipation 
with all four comparators in the OFF state is typically 4 mW 
from a single 5V supply (1 mW/comparator). 

CIRCUIT DESCRIPTION 

Figure 1 shows the basic input stage of one of the four 
comparators of the LM1 39. Transistors Qi through Q4 make 
up a PNP Darlington differential input stage with Q5 and Q6 
serving to give single-ended output from differential input 
with no loss in gain. Any differential input at Q-| and Q4 will 
be amplified causing Q6 to switch OFF or ON depending 




o— I^QtS rwJ-O 



Q5 ] » [06 



TO OUTPUT 
STAGE 



on input signal polarity. It can easily be seen that operation 
with an input common mode voltage of ground is possible. 
With both inputs at ground potential, the emitters of Q1 and 
Q4 will be at one Vbe above ground and the emitters of Q2 
and Q3 at 2 Vbe- For switching action the base of Q5 and 
Q6 need only go to one Vbe above ground and since Q2 
and Q3 can operate with zero volts collector to base, 
enough voltage is present at a zero volt common mode in- 
put to insure comparator action. The bases should not be 
taken more than several hundred millivolts below ground, 
however, to prevent forward biasing a substrate diode which 
would stop all comparator action and possibly damage the 
device, if very large input currents were provided. 
Figure 2 shows the comparator with the output stage added. 
Additional voltage gain is taken through Q7 and Q% with the 
collector of Qe left open to offer a wide variety of possible 
applications. The addition of a large pull-up resistor from the 
collector of Qs to either + Vcc or any other supply up to 
36V both increases the LM139 gain and makes possible 
output switching levels to match practically any application. 
Several outputs may be tied together to provide an ORing 
function or the pull-up resistor may be omitted entirely with 
the comparator then serving as a SPST switch to ground. 




FIGURE 1. Basic LM139 Input Stage 



TL/H/7385-2 

FIGURE 2. Basic LM139 Comparator 

Output transistor Q$ will sink up to 1 5 mA before the output 
ON voltage rises above several hundred millivolts. The out- 
put current sink capability may be boosted by the addition of 
a discrete transistor at the output. 



211 



The complete circuit for one comparator of the LM139 is 
shown in Figure 3. Current sources I3 and I4 are added to 
help charge any parasitic capacitance at the emitters of Q1 
and Q4 to improve the slew rate of the input stage. Diodes 
D1 and D2 are added to speed up the voltage swing at the 
emitters of Q1 and Q2 for large input voltage swings. 




TL/H/7385-3 

FIGURE 3. Complete LM139 Comparator Circuit 

Biasing for current sources l-| through I4 is shown in Figure 
4. When power is first applied to the circuit, current flows 
through the JFET Q13 to bias up diode D 5 . This biases tran- 
sistor Q12 which turns ON transistors Qg and Q10 by allow- 
ing a path to ground for their base and collector currents. 







CURRENT SOURCES 



TL/H/7385-4 

FIGURE 4. Current Source Biasing Circuit 

Current from the left hand collector of Qg flows through di- 
odes D3 and D4 bringing up the base of On to 2 Vbe above 
ground and the emitters of Q1 1 and Q12 to one Vbe- Q12 will 
then turn OFF because its base emitter voltage goes to 
zero. This is the desired action because Qg and Q10 are 
biased ON through Q11, D3 and D4 so Q12 is no longer 
needed. The "bias line" is now sitting at a Vbe below + Vcc 
which is the voltage needed to bias the remaining current 
sources in the LM139 which will have a constant bias re- 
gardless of +Vcc fluctuations. The upper input common 
mode voltage is Vcc minus the saturation voltage of the 
current sources (appoximately 100 mV) minus the 2 Vbe of 
the input devices 61 and Q2 (or Q3 and Q4). 



COMPARATOR CIRCUITS 

Figure 5 shows a basic comparator circuit for converting low 
level analog signals to a high level digital output. The output 
pull-up resistor should be chosen high enough so as to 
avoid excessive power dissipation yet low enough to supply 
enough drive to switch whatever load circuitry is used on the 
comparator output. Resistors R1 and R2 are used to set the 
input threshold trip voltage (Vref) at any value desired with- 
in the input common mode range of the comparator. 



-AA 




■jut: 



TL/H/7385-5 

FIGURE 5. Basic Comparator Circuit 

COMPARATORS WITH HYSTERESIS 

The circuit shown in Figure 5 suffers from one basic draw- 
back in that if the input signal is a slowly varying low level 
signal, the comparator may be forced to stay within its linear 
region between the output high and low states for an unde- 
sireable length of time. If this happens, it runs the risk of 
oscillating since it is basically an uncompensated, high gain 
op amp. To prevent this, a small amount of positive feed- 
back or hysteresis is added around the comparator. Figure 6 




TL/H/7385-6 

FIGURE 6. Comparator with Positive Feedback to 
Improve Switching Time 

shows a comparator with a small amount of positive feed- 
back. In order to insure proper comparator action, the com- 
ponents should be chosen as follows: 

r pull-up < r load and 

R 1 > ^PULL-UP 

This will insure that the comparator will always switch fully 
up to +Vcc and not be pulled down by the load or feed- 
back. The amount of feedback is chosen arbitrarily to insure 
proper switching with the particular type of input signal 



212 



used. If the output swing is 5V, for example, and it is desired 
to feedback 1 % or 50 mV, then R-| ~ 100 R2. To describe 
circuit operation, assume that the inverting input goes 
above the reference input (V|n > Vref)- This will drive the 
output, Vo, towards ground which in turn pulls Vref down 
through R-). Since Vref is actually the noninverting input to 
the comparator, it too will drive the output towards ground 
insuring the fastest possible switching time regardless of 
how slow the input moves. If the input then travels down to 
Vref. tr >e same procedure will occur only in the opposite 
direction insuring that the output will be driven hard towards 
+ V C c- 

Putting hysteresis in the feedback loop of the comparator 
has far more use, however, than simply as an oscillation 
suppressor. It can be made to function as a Schmitt trigger 
with presettable trigger points. A typical circuit is shown in 
Figure 7. Again, the hysteresis is achieved by shifting the 
reference voltage at the positive input when the output volt- 
age Vo changes state. This network requires only three re- 
sistors and is referenced to the positive supply + Vcc of the 
comparator. This can be modeled as a resistive divider, R1 
and R2, between +Vqc and ground with the third resistor, 
R3, alternately connected to +V<x or ground, paralleling 
either R^ or R2. To analyze this circuit, assume that the 
input voltage, Vin, at the inverting input is less than Va- With 
Vim <. Va the output will be high (Vo = + Vcc)- The upper 
input trip voltage, Vai, is defined by: 

w _ +VccF»2 
Vai 



V A 1 = 



(R1 II R3) + R 2 



+VccR2(Ri + R3) 
Ri R2 + R1 R3 + R2 R3 



(D 



When the input voltage Vin, rises above the reference volt- 
age (Vin > Vai), voltage, Vo, will go low (Vo = GND). The 
lower input trip voltage, Va2, is now defined by: 

+ VCCR2IIR3 



> 



V A 2 = 



V A 2 



R1 + R2 II R3 



+V0CR2R3 



(2) 



R-l R 2 + R1 R3 + R 2 R3 
When the input voltage, Vin, decreases to Va2 or lower, the 
output will again switch high. The total hysteresis, AVa, pro- 
vided by this network is defined by: 

AV A = V A 1 - V A2 
or, subtracting equation 2 from equation 1 
+ V C cRi R2 



AV A A- 



(3) 



R1 R2 + R1 R3 + R2 R3 
To insure that Vo will swing between +Vcc and ground, 
choose: 

Rpull-up < Rload and (4) 

R3 > Rpull-up (5) 

Heavier loading on Rpull-up ('- e - smaller values of R3 or 
Rload) simply reduces the value of the maximum output 
voltage thereby reducing the amount of hysteresis by lower- 
ing the value of Vai . For simplicity, we have assumed in the 
above equations that Vo high switches all the way up to 
+ V CC . 

To find the resistor values needed for a given set of trip 
points, we first divide equation (3) by equation (2). This 
gives us the ratio: 



AVa 
V A 2 



R1 R1 

1 + — + — 

R3 R2 

l+^ + S 1 
R 2 R1 



(6) 



RpUU-UP 
3 Ml 




►«* 



a " 



5 10 

V|N 



■*««- 



VgHIQH 

♦V cc 



V IOW 



R2 ? < R3 



TL/H/73B5-7 



FIGURE 7. Inverting Comparator with Hysteresis 



213 



If we let R-i = n R3, equation (6) becomes: 



(7) 



We can then obtain an expression for R2 from equation (1) 
which gives 

R1 II R3 



R 2 = 



+Vcc 

V A 1 



(8) 



- 1 



The following design example is offered: 

Given: V+ = +15V 

R LOAD = 100 kft 

V A1 = +10V 

V A2 = +5V 

To find: R^ R 2 , R3, Rpull-UP 

Solution: 

From equation (4) Rpull-UP < Rload 

R PULL-UP < 100 kft 

so let RpuLL-UP = 3 kft 

From equation (5) R3 > Rload 

R 3 > 100 kft 

so let R 3 = 1 Mft 

.• ,-» AV A 1 °-5 
From equation (7) n = — - = 

Va2 5 



= 1 



and since 
this gives 



From equation (8) R 2 



R1 = n R 3 
Ri = 1 R 3 = 1 Mft 
500 kft 



15 

1 

10 



= 1 Mft 



These are the values shown in Figure 7. 

The circuit shown in Figure 8 is a non-inverting comparator 

with hysteresis which is obtained with only two resistors, R1 



Vref= +7.5V 



Rpuu-up 
3Kfl 



330 Kn I ~ 

I *VA/ 




V HIGH 

+Vcc 



R2 

> v A = v REF 

RI 



I V A = V REf V 













1 


' i 


k 




V|N2 




VlNl 



and R 2 . In contrast to the first method, however, this circuit 
requires a separate reference voltage at the negative input. 
The trip voltage, V A , at the positive input is shifted about 
Vref as Vo changes between + Vcc and ground. 
Again for analysis, assume that the input voltage, Vin, is low 
so that the output, Vo, is also low (V D = GND). For the 
output to switch, Vin must rise up to Vin 1 where V|n 1 is 
given by: 

Vref(Ri + R 2 ) 



V| N 1 = 



R 2 



O) 



As soon as Vo switches to + Vcc. V A will ste P t0 a value 
greater than Vref which is given by: 

(Vcc-V| N1 )R 1 



V A = V| N + 



(10) 



Ri + R 2 

To make the comparator switch back to its low state (Vo = 
GND) Vin must go below Vref before V A will again equal 
Vref. This lower trip point is now given by: 

Vref (Ri + R2)- V CC R1 



V|N2 = 



R 2 



(11) 



The hysteresis for this circuit, AVin, is the difference be- 
tween V|n 1 and Vin 2 an d is given by: 

AVin = V| N 1 - V tN 2 = 

Vref (Ri + R2) V REF (Ri + R 2 ) - V C c Ri 



R 2 



R 2 



AV| N 



VccRi 

R 2 



(12) 



As a design example consider the following: 
Given: R|_OAD = 100 kft 

V|N1 = 10V 

V|N2 = 5V 

+ V CC = 15V 
To find: Vref. Ri. R2 a nd R 3 
Solution: 

Again choose Rpull-up < Rload to minimize loading, so 
let 

RPULL-UP = 3 kft 
Ri _ AV| N 
R 2 Vcc 
R 1 _ 10-5 _ 1 

R 2 ~ 15 ~ 3 



From equation (12) ~^- 



11 



R2 
3 



From equation (9) Vref 



Vref 



10 



Ri 



V| N 



= 7.5V 



1+ 5 



V|N2 

TL/H/7385-8 

FIGURE 8. Non-Inverting Comparator with Hysteresis 



214 



To minimize output loading choose 

R 2 > RpuLL-UP 
or R 2 > 3 kft 

so let R 2 = 1 Mn 

The value of Ri is now obtained from equation (12) 
R 2 



Ri=^ 



330 kft 



1 Mfl 

These are the values shown in Figure 8. 

LIMIT COMPARATOR WITH LAMP DRIVER 

The limit comparator shown in Figure 9 provides a range of 
input voltages between which the output devices of both 
LM139 comparators will be OFF. 




TL/H/7385-9 

FIGURE 9. Limit Comparator with Lamp Driver 

This will allow base current for Q-, to flow through pull-up 
resistor R 4 , turning ON Qi which lights the lamp. If the input 
voltage, Vin, changes to a value greater than Va or less 
than Vg, one of the comparators will switch ON, shorting the 
base of Qi to ground, causing the lamp to go OFF. If a PNP 
transistor is substituted for Q-| (with emitter tied to + Vcc) 
the lamp will light when the input is above V A or below Vb- 
Va and Vb are arbitrarily set by varying resistors R-|, R 2 and 
R3- 

ZERO CROSSING DETECTOR 

The LM139 can be used to symmetrically square up a sine 
wave centered around zero volts by incorporating a small 
amount of positive feedback to improve switching times and 
centering the input threshold at ground (see Figure 10). 
Voltage divider R4 and R5 establishes a reference voltage, 
V1, at the positive input. By making the series resistance, R-| 
plus R 2 equal to R5, the switching condition, V1 = V 2 , will 
be satisfied when Vjn = 0. The positive feedback resistor, 



R6, is made very large with respect to R5 (R6 = 2000 R5). 
The resultant hysteresis established by this network is very 
small (AV1 < 10 mV) but it is sufficient to insure rapid output 
voltage transitions. Diode D1 is used to insure that 




TL/H/7385-10 

FIGURE 10. Zero Crossing Detector 

the inverting input terminal of the comparator never goes 
below approximately -100 mV. As the input terminal goes 
negative, D1 will forward bias, clamping the node between 
R1 and R 2 to approximately -700 mV. This sets up a volt- 
age divider with R 2 and R3 preventing V 2 from going below 
ground. The maximum negative input overdrive is limited by 
the current handling ability of D1 . 

COMPARING THE MAGNITUDE OF 
VOLTAGES OF OPPOSITE POLARITY 

The comparator circuit shown in Figure 11 compares the 
magnitude of two voltages, Vin 1 and Vin 2 which have op- 
posite polarities. The resultant input voltage at the minus 
input terminal to the comparator, Va, is a function of the 
voltage divider from Vin 1 and V|n 2 and the values of R1 
and R 2 . Diode connected transistor Qi provides protection 




TL/H/7385-11 

FIGURE 11. Comparing the Magnitude of 
Voltages of Opposite Polarity 

for the minus input terminal by clamping it at several hun- 
dred millivolts below ground. A 2N2222 was chosen over a 
1N914 diode because of its lower diode voltage. If desired, 
a small amount of hysteresis may be added using the tech- 
niques described previously. Correct magnitude comparison 
can be seen as follows: Let Vin 1 be the input for the posi- 
tive polarity input voltage and Vin 2 the input for the nega- 
tive polarity. If the magnitude of Vin 1 is greater than that 



215 



of V|n 2 the output will go low (Vqut = GND). If the magni- 
tude of Vin 1 is less than that of V|n 2. however, the output 
will go high (V ut = Vcc)- 

MAGNETIC TRANSDUCER AMPLIFIER 

A circuit that will detect the zero crossings in the output of a 
magnetic transducer is shown in Figure 12. Resistor divider, 
Ri and R2, biases the positive input at + Vcc/2, which is 
well within the common mode operating range. The minus 




TL/H/7385-12 

FIGURE 12. Magnetic Transducer Amplifier 

input is biased through the magnetic transducer. This allows 
large signal swings to be handled without exceeding the 
input voltage limits. A symmetrical square wave output is 
insured through the positive feedback resistor R 3 . Resistors 
R1 and R2 can be used to set the DC bias voltage at the 
positive input at any desired voltage within the input com- 
mon mode voltage range of the comparator. 

OSCILLATORS USING THE LM139 

The LM139 lends itself well to oscillator applications for fre- 
quencies below several megacycles. Figure 13 shows a 
symmetrical square wave generator using a minimum of 
components. The output frequency is set by the RC time 



constant of R4 and C-t and the total hysteresis of the loop is 
set by R1, R2 and R3. The maximum frequency is limited 
only by the large signal propagation delay of the comparator 
in addition to any capacitive loading at the output which 
would degrade the output slew rate. 
To analyze this circuit assume that the output is initially high. 
For this to be true, the voltage at the negative input must be 
less than the voltage at the positive input. Therefore, capac- 
itor C1 Is discharged. The voltage at the positive input, Vai, 
will then be given by: 

+ V C cR2 



V A 1 : 

where if R-| = R2 = R3 
then 



R2 + (R1 II Ra> 



V A 1 = 



2 Vcc 



(13) 



(14) 



Capacitor C1 will charge up through R4 so that when it has 
charged up to a value equal to Vai , the comparator output 
will switch. With the output Vo = GND, the value of Va is 
reduced by the hysteresis network to a value given by: 

+ Vcc 



V A2 = 



(15) 



using the same resistor values as before. Capacitor C<| must 
now discharge through R 4 towards ground. The output will 
return to its high state (Vo = + Vcc) when the voltage 
across the capacitor has discharged to a value equal to 
Va2- For the circuit shown, the period for one cycle of oscil- 
lation will be twice the time it takes for a single RC circuit to 
charge up to one half of its final value. The period can be 
calculated from: 

.. .. -VRC (16) 

V1 = V MA xe 

where 



V MAX 



2 Vcc 



and 



V1 



Vmax = Vcc 

2 3 



(17) 



(18) 




+ «cc 



Vc, v„ 










*» "" "~^ """" <" ""■* 








V 
^ 




t - 







1 

1 


— 



,v« , 



TL/H/7385-13 



FIGURE 13. Square Wave Generator 



216 



One period will be given by: 
1 
freq. 

or calculating the exponential gives 
1 



= 2tl 



freq. 



= 2 (0.694) R 4 C, 



(19) 



(20) 



Resistors R3 and R4 must be at least 10 times larger than 
R5 to insure that Vo will go all the way up to + V<x in the 
high state. The frequency stability of this circuit should 
strictly be a function of the external components. 

PULSE GENERATOR WITH VARIABLE DUTY CYCLE 

The basic square wave generator of Figure 13 can be modi- 
fied to obtain an adjustable duty cycle pulse generator, as 
shown in Figure 14, by providing a separate charge and 
discharge path for capacitor Ov One path, through R 4 and 
D<| will charge the capacitor and set the pulse width (t-|). The 
other path, R5 and D2, will discharge the capacitor and set 
the time between pulses fe). By varying resistor Rs, the 
time between pulses of the generator can be changed with- 



"fUU-UP 




__ji__tl: 



TL/H/7385-14 

FIGURE 14. Pulse Generator with Variable Duty Cycle 

out changing the pulse width. Similarly, by varying R4, the 
pulse width will be altered without affecting the time be- 
tween pulses. Both controls will change the frequency of 
the generator, however. With the values given in Figure 14, 
the pulse width and time between pulses can be found from: 
-WR4C1 ,_ % 

V1 = V M ax (1 - e ) risetime (21a) 

-WFUC1 

V1 =V MA xe falltime (21b) 

where 

Vmax = -ir* < 22 > 



and 



which gives 



w _ Vmax _ v cc 

Vi _ 1 — r 



t2 is then given by: 



1 -I1/R4C1 

2 = e 



1_ _ -t2/R 5 C 1 

2~ 6 



(23) 



(24) 



(25) 



These terms will have a slight error due to the fact that 
Vmax is not exactly equal to 2 / 3 Vcc but is actually reduced 
by the diode drop to: 



therefore 



and 



Vmax = g (Vcc 



1 



2 (1 - v BE ) 



1 



Vbe) 



-VR4C1 



-t 2 /R 5 Ci 



(26) 



(27) 



(28) 



2 (1 - V BE ) 
CRYSTAL CONTROLLED OSCILLATOR 

A simple yet very stable oscillator can be obtained by using 
a quartz crystal resonator as the feedback element. Figure 
15 gives a typical circuit diagram of this. This value of R1 




jtj~ix; w 



TL/H/7385-15 

FIGURE 15. Crystal Controlled Oscillator 

and R2 are equal so that the comparator will switch sym- 
metrically about +Vcc/2. The RC time constant of R3 and 
C1 is set to be several times greater than the period of the 
oscillating frequency, insuring a 50% duty cycle by maintain- 
ing a DC voltage at the inverting input equal to the absolute 
average of the output waveform. 

When specifying the crystal, be sure to order series reso- 
nant along with the desired temperature coefficient and load 
capacitance to be used. 

MOS CLOCK DRIVER 

The LM139 can be used to provide the oscillator and clock 
delay timing for a two phase MOS clock driver (see Figure 
16). The oscillator is a standard comparator square wave 
generator similar to the one shown in Figure 13. Two other 
comparators of the LM139 are used to establish the desired 
phasing between the two outputs to the clock driver. A more 
detailed explanation of the delay circuit is given in the sec- 
tion under "Digital and Switching Circuits." 

WIDE RANGE VCO 

A simple yet very stable voltage controlled oscillator using a 
mimimum of external components can be realized using 
three comparators of the LM1 39. The schematic is shown in 
Figure 17a. Comparator 1 is used closed loop as an integra- 
tor (for further discussion of closed loop operation see sec- 
tion on Operational Amplifiers) with comparator 2 used as a 
triangle to square wave converter and comparator 3 as the 
switch driving the integrator. To analyze the circuit, assume 



217 



that comparator 2 is its high state (Vsq = +V<x) which 
drives comparator 3 to its high state also. The output device 
of comparator 3 will be OFF which prevents any current 
from flowing through R2 to ground. With a control voltage, 
Vc, at the input to comparator 1, a current I1 will flow 
through R-j and begin discharging capacitor C1 , at a linear 
rate. This discharge current is given by: 

1 2Ri 
and the discharge time is given by: 



(29) 



r AV 
C1 M" 



(30) 



AV will be the maximum peak change in the voltage across 
capacitor C-) which will be set by the switch points of com- 



parator 2. These trip points can be changed by simply alter- 
ing the ratio of Rp to Rs. thereby increasing or decreasing 
the amount of hysteresis around comparator 2. With Rp = 
100 kfl and Rs = 5 kfi, the amount of hysteresis is approxi- 
mately ±5% which will give switch points of + Vcrj/2 ±750 
mV from a 30V supply. (See "Comparators with Hystere- 
sis"). 

As capacitor C1 discharges, the output voltage of compara- 
tor 1 will decrease until it reaches the lower trip point of 
comparator 2, which will then force the output of compara- 
tor 2 to go to its low state (Vsq = GND). 
This in turn causes comparator 3 to go to its low state where 
its output device will be in saturation. A current I2 can now 




TL/H/7385-16 



FIGURE 16. MOS Clock Driver 

+ Vcc - +30V 




nr: 



(a) 



•— Wr- O +Vcc 




t-Vcc/2 



TL/H/7385-18 



(b) 



FIGURE 17. Voltage Controlled Oscillator 



218 



flow through resistor R2 to ground. If the value of R2 is 
chosen as R-|/2 a current equal to the capacitor discharge 
current can be made to flow out of C1 charging it at the 
same rate as it was discharged. By making R2 = R1 12, 
current I2 will equal twice l-|. This is the control circuitry 
which guararantees a constant 50% duty cycle oscillation 
independent of frequency or temperature. As capacitor C1 
charges, the output of comparator 1 will ramp up until it trips 
comparator 2 to its high state (Vsq = + Vcc) and the cycle 
will repeat. 

The circuit shown in Figure 17a uses a +30V supply and 
gives a triangle wave of 1 .5V peak-to-peak. With a timing 
capacitor, C1 equal to 500 pF, a frequency range from ap- 
proximately 115 kHz down to approximately 670 Hz was 
obtained with a control voltage ranging from 50V down to 
250 mV. By reducing the hysteresis around comparator 2 
down to ±150 mV (R f = 100 kn, R$ = 1 kfl) and reducing 
the compensating capacitor C2 down to .001 fif, frequen- 
cies up to 1 MHz may be obtained. For lower frequencies (f 
<. 1 Hz) the timing capacitor, C-|, should be increased up to 
approximately 1 jmF to insure that the charging currents, h 
and I2, are much larger than the input bias currents of com- 
parator 1 . 

Figure 17b shows another interesting approach to provide 
the hysteresis for comparator 2. Two identical Zener diodes, 
Z] and Z2, are used to set the trip points of comparator 2. 
When the triangle wave is less than the value required to 
Zener one of the diodes, the resistive network, R-| and R2, 
provides enough feedback to keep the comparator in its 
proper state, (the input would otherwise be floating). The 
advantage of this circuit is that the trip points of comparator 
2 will be completely independent of supply voltage fluctua- 
tions. The disadvantage is that Zeners with less than one 
volt breakdown voltage are not obtainable. This limits the 
maximum upper frequency obtainable because of the larger 
amplitude of the triangle wave. If a regulated supply is avail- 
able, Figure 17a is preferable simply because of less parts 
count and lower cost. 

Both circuits provide good control over at least two decades 
in frequency with a temperature coefficient largely depen- 
dent on the TC of the external timing resistors and capaci- 
tors. Remember that good circuit layout is essential along 
with the 0.01 ju,F compensation capacitor at the output of 
comparator 1 and the series 10ft, resistor and 0.1 \iF ca- 
pacitor between its inputs, for proper operation. Comparator 



1 is a high gain amplifier used closed loop as an integrator 
so long leads and loose layout should be avoided. 

DIGITAL AND SWITCHING CIRCUITS 

The LM139 lends itself well to low speed (<1 MHz) high 
level logic circuits. They have the advantage of operating 
with high signal levels, giving high noise immunity, which is 
highly desirable for industrial applications. The output signal 
level can be selected by setting the Vcc t0 which the pull-up 
resistor is connected to any desired level. 

AND/NAND GATES 

A three input AND gate is shown in Figure 18. Operation of 
this gate is as follows: resistor divider R1 and R2 establishes 
a reference voltage at the inverting input to the comparator. 
The non-inverting input is the sum of the voltages at the 
inputs divided by the voltage dividers comprised of R3, R4, 




VoUT = A • B • C 



TL/H/7385-19 



FIGURE 18. Three Input AND Gate 

R5 and R6- The output will go high only when all three inputs 
are high, causing the voltage at the non-inverting input to go 
above that at inverting input. The circuit values shown work 
for a "0" equal to ground and a "1 " equal + 1 5V. The resis- 
tor values can be altered if different logic levels are desired. 
If more inputs are required, diodes are recommended to 
improve the voltage margin when all but one of the inputs 
are the "1" state. This circuit with increased fan-in is shown 
in Figure 19. 

To convert these AND gates to NAND gates simply inter- 
change the inverting and non-inverting inputs to the com- 
parator. Hysteresis can be added to speed up output tran- 
sitions if low speed input signals are used. 




VquT = A»B»C»D 



TL/H/7385-20 



FIGURE 19. AND Gate with Large Fan-In 



219 



OR/NOR GATES 

The three input OR gate (positive logic) shown in Figure 20 
is achieved from the basic AND gate simply by increasing 
Ri thereby reducing the reference voltage. A logic "1" at 
any of the inputs will produce a logic "1" at the output. 
Again a NOR gate may be implemented by simply reversing 
the comparator inputs. Resistor R$ may be added for the 
OR or NOR function at the expense of noise immunity if so 
desired. 




10OK 

*o— <wv— i 



V UT = A + B + C 



TL/H/7385-21 



FIGURE 20. Three Input OR Gate 




TL/H/7385-22 

FIGURE 21. Output Strobing Using a Discrete Transistor 

OUTPUT STROBING 

The output of the LM139 may be disabled by adding a 
clamp transistor as shown in Figure 21. A strobe control 
voltage at the base of Qi will clamp the comparator output 
to ground, making it immune to any input changes. 
If the LM139 is being used in a digital system the output may 
be strobed using any other type of gate having an uncom- 
mitted collector output (such as National's DM5401/ 
DM7401). In addition another comparator of the LM139 
could also be used for output strobing, replacing Qi in Fig- 
ure 21, if desired. (See Figure 22.) 




TL/H/7385-23 

FIGURE 22. Output Strobing with TTL Gate 
ONE SHOT MULTIVIBRATORS 

A simple one shot multivibrator can be realized using one 
comparator of the LM139 as shown in Figure 23. The out- 




_nr v 



TL/H/7385-24 

FIGURE 23. One Shot Multivibrator 

put pulse width is set by the values of C2 and R4 (with 
R4 > 10 R3 to avoid loading the output). The magnitude of 
the input trigger pulse required is determined by the resis- 
tive divider R1 and R2. Temperature stability can be 
achieved by balancing the temperature coefficients of R4 
and C2 or by using components with very low TC. In addi- 
tion, the TC of resistors R1 and R2 should be matched so as 
to maintain a fixed reference voltage of + Vcc/2. Diode D2 
provides a rapid discharge path for capacitor C2 to reset the 
one shot at the end of its pulse. It also prevents the non-in- 
verting input from being driven below ground. The output 
pulse width is relatively independent of the magnitude of the 
supply voltage and will change less than 2% for a five volt 
change in + Vcc- 

The one shot multivibrator shown in Figure 24 has several 
characteristics which make it superior to that shown in Fig- 
ure 23. First, the pulse width is independent of the magni- 
tude of the power supply voltage because the charging volt- 
age and the intercept voltage are a fixed percentage of 
+ V<x- In addition this one-shot is capable of 99% duty 
cycle and exhibits input trigger lock-out to insure that the 
circuit will not re-trigger before the output pulse has been 
completed. The trigger level is the voltage required at the 
input to raise the voltage at point A higher than the voltage 
at point B, and is set by the resistive divider R4 and R10 and 
the network R1, R 2 and R3. When the multivibrator has 
been triggered, the output of comparator 2 is high causing 
the reference voltage at the non-inverting input of compara- 
tor 1 to go to + Vcc- This prevents any additional input 
pulses from disturbing the circuit until the output pulse has 
been completed. 

The value of the timing capacitor, C-| , must be kept small 
enough to allow comparator 1 to completely discharge C1 
before the feedback signal from comparator 2 (through R10) 
switches comparator 1 OFF and allows C1 to start an expo- 
nential charge. Proper circuit action depends on rapidly dis- 
charging C1 to a value set by R6 and Rg at which time 
comparator 2 latches comparator 1 OFF. Prior to the estab- 
lishment of this OFF state, C-| will have been completely 
discharged by comparator 1 in the ON state. The time delay, 
which sets the output pulse width, results from C1 recharg- 
ing to the reference voltage set by R6 and Rg. When the 
voltage across C1 charges beyond this reference, the out- 
put pulse returns to ground and the input is again reset to 
accept a trigger. 

BISTABLE MULTIVIBRATOR 

Figure 25 is the circuit of one comparator of the LM139 
used as a bistable multivibrator. A reference voltage is pro- 
vided at the inverting input by a voltage divider comprised of 
R2 and R 3 . A pulse applied to the SET terminal will switch 
the output high. Resistor divider network R-), R4, and R5 



220 



_n_: 




FIGURE 24. Multivibrator with Input Lock-Out 

I 



TL/H/7385-25 



SETQ VW 




TL/H/7385-26 



FIGURE 25. Bistable Multivibrator 



now clamps the non-inverting input to a voltage greater than 
the reference voltage. A pulse now applied to the RESET 
Input will pull the output low. If both Q and Q outputs are 
needed, another comparator can be added as shown 
dashed in Figure 25. 

Figure 26 shows the output saturation voltage of the LM139 
comparator versus the amount of current being passed to 
ground. The end point of 1 mV at zero current along with an 
Rsat °f 60ft shows why the LM139 so easily adapts itself 
to oscillator and digital switching circuits by allowing the DC 
output voltage to go practically to ground while in the ON 
state. 

1400 

1200 

1000 

I BOO 

§ 600 



Isink (mA) 

TL/H/7385-27 

FIGURE 26. Typical Output Saturation Characteristics 



I 

AV 


60 


















M 
















































J l 


V 






IrnV® 






'a 












/]/ 
















4 












T A 

1 


25° 


C 

1 



TIME DELAY GENERATOR 

The final circuit to be presented "Digital and Switching Cir- 
cuits" is a time delay generator (or sequence generator) as 
shown in Figure 27. 

This timer will provide output signals at prescribed time in- 
tervals from a time reference to and will automatically reset 
when the input signal returns to ground. For circuit evalua- 
tion, first consider the quiescent state (Vin = O) where the 
output of comparator 4 is ON which keeps the voltage 
across C-| at zero volts. This keeps the outputs of compara- 
tors 1, 2 and 3 in their ON state (Vout = GND). When an 
input signal is applied, comparator 4 turns OFF allowing Ci 
to charge at an exponential rate through Ri. As this voltage 
rises past the present trip points Va, Vb, and Vc of compar- 
ators 1 , 2 and 3 respectively, the output voltage of each of 
these comparators will switch to the high state (Vout = 
+ Vcc)- A small amount of hysteresis has been provided to 
insure fast switching for the case where the Rq time con- 
stant has been chosen large to give long delay times. It is 
not necessary that all comparator outputs be low in the qui- 
escent state. Several or all may be reversed as desired sim- 
ply by reversing the inverting and non-inverting input con- 
nections. Hysteresis again is optional. 



221 




to U t 

INPUT GATING SIGNAL 



TL/H/7385-28 



FIGURE 27. Time Delay Generator 



LOW FREQUENCY OPERATIONAL AMPLIFIERS 

The LM139 comparator can be used as an operational am- 
plifier in DC and very low frequency AC applications 
(^100 Hz). An interesting combination is to use one of the 
comparators as an op amp to provide a DC reference volt- 
age for the other three comparators in the same package. 
Another useful application of an LM139 has the interesting 
feature that the input common mode voltage range includes 
ground even though the amplifier is biased from a single 
supply and ground. These op amps are also low power drain 
devices and will not drive large load currents unless current 
boosted with an external NPN transistor. The largest appli- 
cation limitation comes from a relatively slow slew rate 
which restricts the power bandwidth and the output voltage 
response time. 



The LM139, like other comparators, is not internally fre- 
quency compensated and does not have internal provisions 
for compensation by external components. Therefore, com- 
pensation must be applied at either the inputs or output of 
the device. Figure 28 shows an output compensation 
scheme which utilizes the output collector pull-up resistor 
working with a single compensation capacitor to form a 
dominant pole. The feedback network, Ri and R2 sets the 
closed loop gain at 1 + ^/^\ 2 or 101 (40 dB). Figure 29 
shows the output swing limitations versus frequency. The 






mil Mini i nil i 

RESPONSE FOR CIRCUIT 
SHOWN IN FIGURE 30 


Vcc = *5V 






















RESPONSE FOR' 

CIRCUIT SHOWN 

IN FIGURE 28 
















11 



R1 

A v = 1 + — = 



TL/H/7385-29 



FIGURE 28. Non-Inverting Amplifier 



1 10 tOO 1k 10k 100k 

FREQUENCY 

TL/H/7385-30 

FIGURE 29. Large Signal Frequency Response 

output current capability of this amplifier is limited by the 
relatively large pull-up resistor (15 kfl) so the output is 
shown boosted with an external NPN transistor in Figure 30. 
The frequency response is greatly extended by the use of 
the new compensation scheme also shown in Figure 30. 
The DC level shift due to the Vbe of Qi allows the output 
voltage to swing from ground to approximately one volt less 
than +Vcc- A voltage offset adjustment can be added as 
shown in Figure 31. 



222 



+ V,nO 




TL/H/7385-31 

FIGURE 30. Improved Operational Amplifier 



OFFSET 
ADJUST 



+V,nO 




A v s 100 TL/H/7385-32 

FIGURE 31. Input Offset Null Adjustment 
DUAL SUPPLY OPERATION 

The applications presented here have been shown biased 
typically between +V<x and ground for simplicity. The 
LM139, however, works equally well from dual (plus and 
minus) supplies commonly used with most industry standard 
op amps and comparators, with some applications actually 
requiring fewer parts than the single supply equivalent. 
The zero crossing detector shown in Figure 10 can be im- 
plemented with fewer parts as shown in Figure 32. Hystere- 
sis has been added to insure fast transitions if used with 




slowly moving input signals. It may be omitted if not needed, 
bringing the total parts count down to one pull-up resistor. 
The MOS clock driver shown in Figure 16 uses dual supplies 
to properly drive the MM0025 clock driver. 
The square wave generator shown in Figure 13 can be used 
with dual supplies giving an output that swings symmetrical- 
ly above and below ground (see Figure 33). Operation is 
identical to the single supply oscillator with only change be- 
ing in the lower trip point. 




n_r 



TL/H/7385-34 

FIGURE 33. Squarewave Generator Using Dual Supplies 

Figure 34 shows an LM139 connected as an op amp using 
dual supplies. Biasing is actually simpler if full output swing 
at low gain settings is required by biasing the inverting input 
from ground rather than from a resistive divider to some 
voltage between + Vqc and ground. 
All the applications shown will work equally well biased with 
dual supplies. If the total voltage across the device is in- 
creased from that shown, the output pull-up resistor should 
be increased to prevent the output transistor from being 
pulled out of saturation by drawing excessive current, there- 
by preventing the output low state from going all the way to 
-Vcc- 




TL/H/7385-35 

FIGURE 34. Non-Inverting Amplifier Using Dual Supplies 



TL/H/7385-33 

FIGURE 32. Zero Crossing Detector Using Dual Supplies 



223 



MISCELLANEOUS APPLICATIONS 

The following is a collection of various applications intended 
primarily to further show the wide versatility that the LM139 
quad comparator has to offer. No new modes of operation 
are presented here so all of the previous formulas and cir- 
cuit descriptions will hold true. It is hoped that all of the 
circuits presented in this application note will suggest to the 
user a few of the many areas in which the LM139 can be 
utilized. 

REMOTE TEMPERATURE SENSOR/ALARM 

The circuit shown in Figure 35 shows a temperature over- 
range limit sensor. The 2N930 is a National process 07 sili- 
con NPN transistor connected to produce a voltage refer- 
ence equal to a multiple of its base emitter voltage along 
with temperature coefficient equal to a multiple of 2.2 mv7°C. 
That multiple is determined by the ratio of Ri to R2- The 
theory of operation is as follows: with transistor Qi biased 
up, its base to emitter voltage will appear across resistor Ri . 
Assuming a reasonably high beta (/3 > 100) the base cur- 
rent can be neglected so that the current that flows through 
resistor Ri must also be flowing through R2. The voltage 
drop across resistor R2 will be given by: 

<R1 = lR2 
and 



Vri = V be = Iri Ri 



VR2 = lR2 R 2 



R 2 

Iri «2 = V be ■£ 
"1 



(31) 



As stated previously this base-emitter voltage is strongly 
temperature dependent, minus 2.2 mV/°C for a silicon tran- 
sistor. This temperature coefficient is also multiplied by the 
resistor ratio R1/R2. 

This provides a highly linear, variable temperature coeffi- 
cient reference which is ideal for use as a temperature sen- 
sor over a temperature range of approximately -65°C to 



+ 150°C. When this temperature sensor is connected as 
shown in Figure 35 it can be used to indicate an alarm con- 
dition of either too high or too low a temperature excursion. 
Resistors R3 and R4 set the trip point reference voltage, Vb, 
with switching occuring when Va = Vb- Resistor R5 is used 
to bias up Q1 at some low value of current simply to keep 
quiescent power dissipation to a minimum. An Iq near 1 juA 
is acceptable. 

Using one LM139, four separate sense points are available. 
The outputs of the four comparators can be used to indicate 
four separate alarm conditions or the outputs can be OR'ed 
together to indicate an alarm condition at any one of the 
sensors. For the circuit shown the output will go HIGH when 
the temperature of the sensor goes above the preset level. 
This could easily be inverted by simply reversing the input 
leads. For operation over a narrow temperature range, the 
resistor ratio R 2 /Ri should be large to make the alarm more 
sensitive to temperature variations. To vary the trip points a 
potentiometer can be substituted for R3 and R4. By the ad- 
dition of a single feedback resistor to the non-inverting input 
to provide a slight amount of hysteresis, the sensor could 
function as a thermostat. For driving loads greater than 
1 5 mA, an output current booster transistor could be used. 

FOUR INDEPENDENTLY VARIABLE, TEMPERATURE 
COMPENSATED, REFERENCE SUPPLIES 

The circuit shown in Figure 36 provides four independently 
variable voltages that could be used for low current supplies 
for powering additional equipment or for generating the ref- 
erence voltages needed in some of the previous compara- 
tor applications. If the proper Zener diode is chosen, these 
four voltages will have a near zero temperature coefficient. 
For industry standard Zeners, this will be somewhere be- 
tween 5.0 and 5.4V at a Zener current of approximately 
1 mA. An alternative solution is offered to reduce this 50 
mW quiescent power drain. Experimental data has shown 
that any of National's process 21 transistors which have 
been selected for low reverse beta (/Jr <.25) can be used 



REMOTE 
SENSOR 




v + 
9 



| LOAD | 

< — wv— £" < — VW "~C 



X 



TL/H/7385-36 



FIGURE 35. Temperature Alarm 



224 



+ VCC 



> 

I 



10/iF 




10/nF 



TL/H/7385-37 



FIGURE 36. Four Variable Reference Supplies 



quite satisfactorily as a zero T.C. Zener. When connected 
as shown in Figure 37, the T.C. of the base-emitter Zener 
voltage is exactly cancelled by the T.C. of the forward bi- 
ased base-collector junction if biased at 1 .5 mA. The diode 
can be properly biased from any supply by adjusting Rs to 
set lq equal to 1 .5 mA. The outputs of any of the reference 
supplies can be current boosted by using the circuit shown 
in Figure 30. 



LEAVE BASE 
LEAD OPEN 





TL/H/7385-39 

FIGURE 38. Magnetic Tape Reader with TTL Output 



: National Process 21 
Selected for Low 
Reverse fi 



TL/H/7385-38 



FIGURE 37. Zero T.C. Zener 



DIGITAL TAPE READER 

Two circuits are presented here-a tape reader for both 
magnetic tape and punched paper tape. The circuit shown 
in Figure 38, the magnetic tape reader, is the same as Fig- 
ure 12 with a few resistor values changed. With a 5V supply, 
to make the output TTL compatible, and a 1 Mft feedback 
resistor, ±5 mV of hysteresis is provided to insure fast 
switching and higher noise immunity. Using one LM139, four 
tape channels can be read simultaneously. 




df | 



TL/H/7385-40 

FIGURE 39. Paper Tape Reader With TTL Output 



225 



The paper tape reader shown in Figure 39 is essentially the 
same circuit as Figure 38 with the only change being in the 
type of transducer used. A photo-diode is now used to 
sense the presence or absence of light passing through 
holes in the tape. Again a 1 Mil feedback resistor gives 
±5 mV of hysteresis to insure rapid switching and noise 
immunity. 

PULSE WIDTH MODULATOR 

Figure 40 shows the circuit for a simple pulse width modula- 
tor circuit. It is essentially the same as that shown in Figure 
13 with the addition of an input control voltage. With the 
input control voltage equal to + V<x/2, operation is basical- 
ly the same as that described previously. If the input control 
voltage is moved above or below +Vcc/2, however, the 
duty cycle of the output square wave will be altered. This is 
because the addition of the control voltage at the input has 
now altered the trip points. These trip points can be found if 
the circuit is simplified as in Figure 41. Equations 1 3 through 
20 are still applicable if the effect of Re is added, with equa- 
tions 1 7 through 20 being altered for condition where Vc =/*= 
+ V CC /2. 

Pulse width sensitivity to input voltage variations will be in- 
creased by reducing the value of Re from 10 kfl and alter- 
nately, sensitivity will be reduced by increasing the value of 
Re- The values of Ri and Ci can be varied to produce any 
desired center frequency from less than one hertz to the 
maximum frequency of the LM139 which will be limited by 
+ Vcc and the output slew rate. 




4 >— O V UT 



TL/H/7385-41 



FIGURE 40. Pulse Width Modulator 





V A = UPPER TRIP POINT 



V B = LOWER TRIP POINT 
TL/H/7385-42 

FIGURE 41. Simplified Circuit For 
Calculating Trip Points of Figure 40 



POSITIVE AND NEGATIVE PEAK DETECTORS 

Figures 42 and 43 show the schematics for simple positive 
or negative peak detectors. Basically the LM139 is operated 
closed loop as a unity gain follower with a large holding 
capacitor from the output to ground. For the positive peak 
detector a low impedance current source is needed so an 
additional transistor is added to the output. When the output 



V,nO 




-Ov 



TL/H/7385-43 



FIGURE 42. Positive Peak Detector 

of the comparator goes high, current is passed through Qi 
to charge up C^ . The only discharge path will be the 1 Mil 
resistor shunting C-| and any load that is connected to 
v out- The decay time can be altered simply by changing 
the 1 Mil resistor higher or lower as desired. The output 
should be used through a high impedance follower to avoid 
loading the output of the peak detector. 



VinO 




Ov 



TL/H/7385-44 



FIGURE 43. Negative Peak Detector 

For the negative peak detector, a low impedance current 
sink is required and the output transistor of the LM139 
works quite well for this. Again the only discharge path will 
be the 1 Mil resistor and any load impedance used. Decay 
time is changed by varying the 1 Mil resistor. 

CONCLUSION 

The LM139 is an extremely versatile comparator package 
offering reasonably high speed while operating at power lev- 
els in the low mW region. By offering four independent com- 
parators in one package, many logic and other functions 
can now be performed at substantial savings in circuit com- 
plexity, parts count, overall physical dimensions, and power 
consumption. 

For limited temperature range application, the LM239 or 
LM339 may be used in place of the LM139. 
It is hoped that this application note will provide the user 
with a guide for using the LM139 and also offer some new 
application ideas. 



226 



IC Preamplifier Challenges 
Choppers on Drift 



National Semiconductor 
Application Note 79 




Since the introduction of monolithic IC amplifiers there has 
been a continual improvement in DC accuracy. Bias cur- 
rents have been decreased by 5 orders of magnitude over 
the past 5 years. Low offset voltage drift is also necessary in 
a high accuracy circuits. This is evidenced by the popularity 
of low drift amplifier types as well as the requests for select- 
ed low-drift op amps. However, until now the chopper stabi- 
lized amplifier offered the lowest drift. A new monolithic IC 
preamplifier designed for use with general purpose op amps 
improves DC accuracy to where the drift is lower than many 
chopper stabilized amplifiers. 

INTRODUCTION 

Chopper amplifiers have long been known to offer the low- 
est possible DC drift. They are not without problems, howev- 
er. Most chopper amps can be used only as inverting ampli- 
fiers, limiting their applications. Chopping can introduce 
noise and spikes into the signal. Mechanical choppers need 
replacement as well as being shock sensitive. Further, 
chopper amplifiers are designed to operate over a limited 
power supply, limited temperature range. 
Previous low-drift op amps do not provide optimum perform- 
ance either. Selected devices may only meet their specified 
voltage drift under restrictive conditions. For example, if a 
741 device is selected without offset nulling, the addition of 
a offset null pot can drastically change the drift. Low drift op 
amps designed for offset balancing have another problem. 
The resistor network used in the null circuit is designed to 
null the drift when the offset voltage is nulled. The mecha- 
nism to achieve nulled drift depends on the difference in 
temperature coefficient between the internal resistors and 
the external null pot. Since the internal resistors have a non- 
linear temperature coefficient and may vary device to device 
as well as between manufacturers, it can only approximately 
null offset drift. The problem gets worse if the external null 
pot has a TC other than zero. 

A new IC preamplifier is now available which can give drifts 
as low as 0.2 jhV/°C. It is used with conventional op amps 
and eliminates the problems associated with older devices. 
As well as improving the DC input characteristics of the op 
amp, loop-gain is increased when an LM121 is used. This 
further improves overall accuracy since DC gain error is de- 
creased. 

The LM121 preamp is designed to give zero drift when the 
offset voltage is nulled to zero. The operating current of the 
LM121 is programmable by the value of the null network 



resistors. The drift is independent of the value of the nulling 
network so it can be used over a wide range of operating 
currents while retaining low drift. The operating current can 
be chosen to optimize bias current, gain, speed, or noise 
while still retaining the low drift. Further, since the drift is 
independent of the match between external and internal re- 
sistors when the offset is nulled, lower and more predictable 
drifts can be expected in actual use. The input is fully differ- 
ential, overcoming many of the problems with single ended 
chopper-amps. The device also has enough common mode 
rejection ratio to allow the low drift to be fully utilized. 

CIRCUIT DESCRIPTION 

The LM121 is a well matched differential amplifier utilizing 
super-gain transistors as the input devices. A schematic is 
shown in Figure 1. The input signal is applied to the bases of 
Q3 and Q4 through protection resistors R1 and R 2 . Q3 and 
Q4 have two emitters to allow offset balancing which will be 
explained later. The operating current for the differential am- 
plifier is supplied by current sources Q-| and Q-|-|. The oper- 
ating current is externally programmed by resistors connect- 
ed from the emitters of Q10 arid Q1 1 to the negative supply. 
Input transistors Q3 and 64 are cascoded by transistors Q5 
and Q6 to keep the collector base voltage on the input 
stage equal to zero. This eliminates leakage at high operat- 
ing temperatures and keeps the common mode input volt- 
age from appearing across the low breakdown super-gain 
input transistors. Additionally, the cascode improves the 
common mode rejection of the differential amplifier. Q1 and 
Q2 protect the input against large differential voltages. 
The ouput signal is developed across resistive loads R3 and 
R4. The total collector current of the input is then applied to 
the base of a fixed gain PNP, Q7. The collector current of 
Q7 sets the operating current of Qs, Q12. and Q13. These 
transistors are used to set the operating voltage of the cas- 
code, Q5 and Qe- By operating the cascode biasing transis- 
tors at the same operating current as the input stage, it is 
possible to keep collector base voltage at zero; and there- 
fore, collector-base leakage remains low over a wide cur- 
rent range. Further, this minimizes the effects of Vbe varia- 
tions and finite transistor current gain. At high operating cur- 
rents the collector base voltage of the input stage is in- 
creased by about 100 mV due to the drop across R15 and 
R-I6- This prevents the input transistors from saturating un- 
der worst case conditions of high current and high operating 
temperature. 



227 




*Pin connections shown on diagram and typical applications are for TO-5 

FIGURE 1. Schematic Diagram of the LM121 



The rest of the devices comprise the turn-on and regulator 
circuitry. Transistors Q14. Q15. and Q16 form a 1.2V regula- 
tor for the bases of the input stage current source. By fixing 
the bases of the current sources at 1 .2V, their ouput current 
changes proportional to absolute temperature. This com- 
pensates for the temperature sensitivity of the input stage 
transconductance. Temperature compensating the trans- 
conductance makes the preamp more useful in some appli- 
cations such as an instrumentation amplifier and minimizes 
bandwidth variations with temperature. The regulator is 
started by Q-is and its operating current is supplied by Q17 
and Qg, Figure 2 shows the LM121 chip. 

OFFSET BALANCING 

The LM121 was designed to operate with an offset balanc- 
ing network connected to the current source transistors. 
The method of balancing the offset also minimizes the drift 
of the preamp. Unlike earlier devices such as the LM725, 



the LM121 depends only upon the highly predictable emitter 
base voltages of transistors to achieve low drift. Devices 
like the LM725 depend on the match between internal resis- 
tor temperature coefficient and the external null pot as well 
as the input stage transistors characteristics for drift com- 
pensation. 

The input stage of the LM121 is actually two differential 
amplifiers connected in parallel, each having a fixed offset. 
The offset is due to different areas for the transistor emit- 
ters. The offset for each pair is given by: 

AVBE-£m£ 
q A 2 

where k is Boltzmann's constant T is absolute temperature, 



228 




TL/H/7387-2 

FIGURE 2. LM121 Chip 

q is the charge on an electron, and A^ and Ag are emitter 
areas. Because of the offset, each pair has a fixed drift. 
When the pairs are connected in parallel, if they match, the 
offsets and drift cancel. However, since matching is not per- 
fect, the emitters of the pairs are not connected in parallel, 
but connected to independent current sources to allow off- 
set balancing. The offset and drift effect of each pair is pro- 
portional to its operating current, so varying the ratio of the 
current from current sources will vary both the offset and 
drift. When the offset is nulled to zero, the drift is nulled to 
below 1 ju,V/°C. 

The offset balancing method used in the LM121 has several 
advantages over conventional balancing schemes. Firstly, 
as mentioned earlier, it theoretically zeros the drift and off- 
set simultaneously. Secondly, since the maximum balancing 
range is fixed by transistor areas, the effect of null network 
variations on offset voltage is minimized. Resistor shifts of 
one percent only cause a 30 /wV shift in offset voltage on 
the LM1 21 , while a one percent shift in collector resistors on 
a standard diff amp causes a 300 /xV offset change. Finally, 
it allows the value of the null network to set the operating 
current. 

ACHIEVING LOW DRIFT 

A very low drift amplifier poses some uncommon application 
and testing problems. Many sources of error can cause the 
apparent circuit drift to be much higher than would be pre- 
dicted. In many cases, the low drift of the op amp is com- 
pletely swamped by external effects while the amplifier is 
blamed for the high drift. 

Thermocouple effects caused by temperature gradient 
across dissimilar metals are perhaps the worst offenders. 
Whenever dissimilar metals are joined, a thermocouple re- 
sults. The voltage generated by the thermocouple is propor- 
tional to the temperature difference between the junction 
and the measurement end of the metal. This voltage can 
range between essentially zero and hundred of microvolts 
per degree, depending on the metals used. In any system 



using integrated circuits a minimum of three metals are 
found: copper, solder, and kovar (lead material of the IC). 
Nominally, most parts of a circuit are at the same tempera- 
ture. However, a small temperature gradient can exist 
across even a few inches — and this is a big problem with 
low level signals. Only a few degrees gradient can cause 
hundreds of microvolts of error. The two places this shows 
up, generally are the package-to printed circuit board inter- 
face and temperature gradients across resistors. Keeping 
package leads short and the two input leads close together 
help greatly. 

For example, a very low drift amplifier was constructed and 
the output monitored over a 1 minute period. During the 1 
minute it appeared to have input referred offset variations of 
± 5 ju.V. Shielding the circuit from air currents reduced this 
to ±0.5 juV. The 10 ju.V error was due to thermal gradients 
across the circuit from air currents. 
Resistor choice as well as physical placement is important 
for minimizing thermocouple effects. Carbon, oxide film and 
some metal film resistors can cause large thermocouple er- 
rors. Wirewound resistors of evenohm or managanin are 
best since they only generate about 2 ju.V/°C referenced to 
copper. Of course, keeping the resistor ends at the same 
temperature is important. Generally, shielding a low drift 
stage electrically and thermally will yield good results. 
Resistors can cause other errors besides gradient generat- 
ed voltages. If the gain setting resistors do not track with 
temperature a gain error will result. For example a gain of 
1000 amplifier with a constant 10 mV input will have a 10V 
output. If the resistors mistrack by 0.5% over the operating 
temperature range, the error at the output is 50 mV. Re- 
ferred to input, this is a 50 jaV error. Most precision resistors 
use different material for different ranges of resistor values. 
It is not unexpected that resistors differing by a factor of 
1 000, do not track perfectly with temperature. For best re- 
sults insure that the gain fixing resistors are of the same 
material or have tracking temperature coefficients. 
Testing low drift amplifiers is also difficult. Standard drift 
testing techniques such as heating the device in an oven 
and having the leads available through a connector, thermo- 
probe, or the soldering iron method — do not work. Thermal 
gradients cause much greater errors than the amplifier drift. 
Coupling microvolt signals through connectors is especially 
bad since the temperature difference across the connector 
can be 50°C or more. The device under test along with the 
gain setting resistor should be isothermal. The circuit in Fig- 
ure 3 will yield good results if well constructed. 



>- 




Vqs X 1000 



1 



AMBIENT 

TL/H/7387-3 



*Op amp shown in Figure 9. 

FIGURE 3. Drift Measurement Circuit 



229 



PERFORMANCE 

It is somewhat difficult to specify the performance of the 
LM121 since it is programmable over a wide range of oper- 
ating currents. Changing the operating current varies gain, 
bias current, and offset current — three critical parameters 
in a high accuracy system. However, offset voltage and drift 
are virtually independent of the operating current. 
Typical performance at an operating current of 20 ju.A is 
shown in Table I. Figures 4 and 5 show how the bias cur- 
rent, offset current, and gain change as a function of pro- 
gramming current. Drift is guaranteed at 1 /u,V/"C indepen- 
dent of the operating current. 

TABLE I. Typical Performance at an Operating 
Current of 10 jxA Per Side 

Offset Voltage Nulled 

Bias Current 7 nA 

Offset Current 0.5 nA 

Offset Voltage Drift 0.3 jxV/°C 

Common Mode Rejection Ratio 1 25 dB 

Supply Voltage Rejection Ratio 1 25 dB 

Common Mode Range ± 1 3V 

Gain 20 V/V 

Supply Current 0.5 mA 
100 



k I" 

















































































































SE 














"OFF 




















































































LI i 


I. „ 


I 

1 



£ i 



.1 

3 S 10 30 50 100 2 

SET CURRENT/SIDE (pA) 

TL/H/7387-4 

FIGURE 4. Bias and Offset Current vs Set Current 



300 



Z 10 ° 

































































































































































































































































s = ±15 

























































12 5 10 20 50 100 

COLLECTOR CURRENT/SIDE M) 

TL/H/7387-5 

FIGURE 5. Gain vs Set Current 

Over a temperature range of -55°C to + 125°C the LM121 
has less than 1 jutV/°C offset voltage drift when nulled. It is 
important that the offset voltage is accurately nulled to 
achieve this low drift. The drift is directly related to the offset 
voltage with 3.8 ]iN/°C drift resulting from every millivolt of 



offset. For example, if the offset is nulled to 100 ju,V, about 
0.4 ju,V/°C will result — or twice the typically expected drift. 
This drift is quite predictable and could even be used to 
cancel the drift elsewhere in a system. Figure 6 shows drift 
as a function of offset voltage. For critical applications se- 
lected devices can achieve 0.2 ju,V/°C. 
Figures 7 and 8 show the bias current, offset current, and 
gain variation over a -55°C to + 125°C temperature range. 
These performance characteristics do not tell the whole sto- 
ry. Since the LM121 is used with an operational amplifier, 
the op amp characteristics must be considered for over-all 
amplifier performance. 

5 

















































V s = 


±15V 



.2 .4 .6 .8 1.0 

OFFSET VOLTAGE On VI 



TL/H/7387-6 



FIGURE 6. Drift vs Offset Voltage 

100 











— ~ 4 








— 




















— I — 






































































































































flFFSFT 















































































.1 

-55-35-15 5 25 45 65 85 105 125 
TEMPERATURE (°C) 

TL/H/7387-7 

FIGURE 7. Bias and Offset Current vs Temperature 

1.4 
2 1.3 

i 1.2 

cc 
o 

z 

\ u 

< 

< 

o -3 

> 

.8 
-55 -35 -15 5 25 45 65 85 105 125 

TEMPERATURE (°C) 

TL/H/7387-8 

FIGURE 8. Gain vs Temperature for the LM121 









































































































Vs 

f = 


= ±1 
300 


bV 
Hz 



230 



OP AMP EFFECTS 

The LM121 is nominally used with a standard type of opera- 
tional amplifier. The op amp functions as the second and 
ensuing stages of the amplifying system. When the LM121 
is connected to an op amp, the two devices may be treated 
(and used) just as a single op amp. The inputs of the combi- 
nation are the inputs of the LM121 and the output is from 
the op amp. Feedback, as with any op amp, is applied back 
to the inputs. Figure 9 shows the general configuration of an 
amplifier using the LM121. 

The offset voltage and drift of the op amp used have an 
effect on overall performance and must be considered. (The 
bias and offset currents of today's op amp are low enough 
to be ignored.) Although the exact effects of the op amp 
stage are difficult and tedious to calculate, a few approxima- 
tions will show the sources of drift. 
Op amp drift is perhaps the most important source of error. 
Drift of the op amp is directly reduced by the gain of the 
LM121. The drift referred to the input is given by: 

op amp drift 
input drift = , [* K . + LM121 drift. 
LM121 gain 

If the op amp has a drift of 10 /u.V7°C and the LM121 is 
operated at a gain of Ay = 50, there will be a 0.2 jxvVC 
component of the total drift due to the op amp. It is there- 
fore important that the LM121 be operated at relatively high 
gain to minimize the effects of op amp drift. Lower gains for 
the LM121 will give proportionately less reduction in op amp 
drift. Of course, a moderately low drift op amp such as the 
LM108A eases the problem. 

Op amp offset voltage also has an effect on total drift. For 
purpose of analysis assume the LM121 to be perfect with 
no offset or drift of its own. Then any offset seen when the 
LM121 is connected to an op amp is due to the op amp 
alone. The offset is equal to: 

op amp offset 

offset voltage = — — 

LM121 gain 

or the offset is reduced by the gain of the LM121 . For exam- 
ple, with a gain of 50 for the LM121, 2 mV of offset on the 
op amp appears as 40 jaV of offset at the LM121 input. 
Unlike offset due to a mismatch in the LM121, this 40 /xV of 
offset does not cause any drift. However, when the system 
is nulled so the offset at the input of the LM121 is zero, 40 
ju,V of imbalance has been inserted into the LM121. The 
imbalance caused by nulling the offset induced by the op 



amp will cause a drift of about 0.14 ju.V/°C. With the system 
nulled the drift due to op amp will cause a drift of about 
0.15 ju,V7 C. With the system nulled the drift due to op amp 
offset can be expressed as: 

op amp offset (mV) 



drift (jwV/°C) 



(3.6 juV/°C). 



LM121 gain 

In actual operation, drift due to op amp offsets will usually 
be better than predicted. This is because offset voltage and 
drift are not independent. With the LM121 there is a strong, 
predictable, correlation between offset and drift. Also, there 
is a correlation with op amps, but it is not as strong. The drift 
of the op amp tends to cancel the drift induced in the LM1 21 
when the system is nulled. 

In the previous example the drift due to the op amp offset 
was 0.15 pM/°C. If the op amp has a drift of 3.6 ju,V/°C per 
millivolt of offset (like the LM121) it will have a drift of 
7.2 juVVC. This drift is reduced by the gain of the LM121 
(A v = 50) to 0.14 juV/ C. This 0.14 juV/°C will cancel the 
0.14 jaV/°C drift due to balancing the LM121. Since op 
amps do not always have a strong correlation between off- 
set and drift, the cancellation of drifts is not total. Once 
again, high gain for the LM121 and a low offset op amp 
helps achieve low drifts. 

FREQUENCY COMPENSATION 

The additional gain of the LM121 preamplifier when used 
with an operational amplifier usually necessitates additional 
frequency compensation. This is because the additional 
gain introduced by the LM121 must be rolled-off before the 
phase shift through the LM121 and op amp reaches 180°. 
The additional compensation depends on the gain of the 
LM121 as well as the closed loop gain of the system. Two 
frequency compensation techniques are shown here that 
will operate with any op amp that is unity gain stable. 
When the closed loop gain of the op amp with the LM121 is 
less than the gain of the LM121 alone, more compensation 
is needed. The worst case situation is when there is 1 00% 
feedback — such as a voltage follower or integrator — and 
the gain of the LM121 is high. When high closed loop gains 
are used — for example Av = 1 000 — and only an addition- 
al gain of 100 is inserted by the LM121, the frequency com- 
pensation of the op amp will usually suffice. 
The basic circuit of the LM121 in Figure 9 shows two com- 
pensation capacitors connected to the op amp (disregard- 
ing the 30 pF frequency compensation for the op 



231 







OUTPUT 



RsET(kn) 



FIGURE 9. General Purpose Amplifier Using the LM121 



amp alone). The capacitor from pin 6 to pin 2 around the op 
amp acts as an integrating capacitor to roll off the gain. 
Since the output of the LM121 is differential, a second ca- 
pacitor is needed to roll off pin 3 of the op amp. These 
capacitors are Cd and Cc2 ' n Figure 9. 
With capacitors equal, the circuit retains good AC power 
supply rejection. The approximate value of the compensa- 
tion capacitors is given by: 

8 
Cc = -rri — s — farads 

106A CL R S ET 

where Rset is tne current set resistor from each current 
source and where Acl is closed loop gain. Table II shows 
typical capacitor values. 



An alternate compensation scheme was developed for ap- 
plications requiring more predictable and smoother roll off. 
This is useful where the amplifier's gain is changed over a 
wide range. In this case Cci is made large and connected 
to V+ rather than ground. The output of the LM121 is ren- 
dered single ended by a 0.01 /nF bypass capacitor to V + . 
Overall frequency compensation then is achieved by an in- 
tegrating capacitor around the op amp: 

12 
Bandwidth at unity gain 



for 0.5 MHz bandwidth C = 



2ttRsetC 

4 
106 R S et 



TABLE II. Typical compensation capacitors for various 

operating currents and closed loop gains. Values given 

apply to LM101A, LM108, and LM741 type amplifiers. 



Closed 




Current Set Resistor 




Loop 
Gain 








120 kn 


60 kn 


30 kn 


12 kn 


6kn 


A v = 1 


68 pF 


130pF 


270 pF 


680 pF 


1300pF 


A v = 5 


15 pF 


27 pF 


50 pF 


130 pF 


270 pF 


A v = 10 


10 pF 


15 pF 


27 pF 


68 pF 


130pF 


A v = 50 


1pF 


3pF 


5pF 


15 pF 


27 pF 


A v = 100 




1pF 


3pF 


5pF 


10 pF 


A v = 500 






1pF 


1pF 


3pF 


A v = 1000 













232 



For use with higher frequency op amps such as the LM1 18 
the bandwidth may be increased to about 2 MHz. If closed 
loop gain is greater than unity "C" may be decreased to: 
4 



C = 



106A CL RsET 



APPLICATIONS 

No attempt will be made to include precision op amp appli- 
cations as they are well covered in other literature. The pre- 
vious sections detail frequency compensation and drift 
problems encountered in using very low drift op amps. The 
circuit shown in Figure 9 will yield good results in almost any 
op amp application. However, it is important to choose the 
operating current properly. From the curves given it is rela- 
tively easy to see the effects of current changes. High cur- 
rents increase gain and reduce op amp effects on drift. Bias 
and offset current also increase at high current. When the 
operating source resistance is relatively high, errors due to 
high bias and offset current can swamp offset voltage drift 
errors. Therefore, with high source impedances it may be 
advantageous to operate at lower currents. 
Another important consideration is output common mode 
voltage. This is the voltage between the outputs of the 
LM121 and the positive power supply. Firstly, the output 
common mode voltage must be within the operating com- 
mon mode range of the output op amp. At currents above 
10 /iA there is no problems with the LM108, LM101, and 
LM741 type devices. Higher currents are needed for devic- 
es with more limited common mode range, such as the 
LM118. As the operating current is increased, the positive 
common mode limit for the LM121 is decreased. This is 
because there is more voltage drop across the internal 50k 
load resistors. The output common mode voltage and posi- 
tive common mode limits are about equal and given by: 

Output common / 0.65X50kn\ 

mode voltage positive ~ V+ - I 0.6V + I 

\ nsET / 



common mode limit 



If it is necessary to increase the common mode output volt- 
age (or limit), external resistors can be connected in parallel 
with the internal 50 kCl resistors. This should only be done 
at high operating currents (80 /xA) since it reduces gain and 
diverts part of the input stage current from the internal bias- 



ing circuitry. A reasonable value for external resistors is 
50 kfi. 

The external resistors should be of high quality and low drift, 
such as wirewound resistors, since they will affect drift if 
they do not track well with temperature. A 20 ppm/°C differ- 
ence in external resistor temperature coefficient will intro- 
duce an additional 0.3 ^V/°C drift. 
An unusually simple gain of 1000 instrumentation amplifier 
can be made using the LM121. The amplifier has a floating, 
full differential, high impedance input. Linearity is better than 
1 %, depending upon input signal level with maximum error 
at maximum input. Gain stability, as shown in Figure 10, is 
about ±2% over a -55"C to +125°C temperature range. 
Finally, the amplifier has very low drift and high CMRR. 



3 1-02 



























































































































v s 


= ±15V 














f* 


300 Hz 

I 



.96 
-56 -35 -15 5 25 45 65 85 105 125 

TEMPERATURE <°C) TL/H/7387-10 

FIGURE 10. Instrumentation Amplifier 
Gain vs Temperature 

Figure 1 1 shows a schematic of the instrumentation amplifi- 
er. The LM121 is used as the input stage and operated 
open-loop. It converts an input voltage to a differential out- 
put current at pins 1 and 8 to drive an op amp. The op amp 
acts as a current to voltage converter and has a single-end- 
ed output. 

Resistors Ri and R2 with null pot R3 set the operating cur- 
rent of the LM121 and provide offset adjustment. R4 is a 
fine trim to set the gain at 1000. There is very little interac- 
tion between the gain and null pots. 



INPUT 



OUTPUT 




JEtetter than 1% linearity for input 
signals up to ±10 mV gain stability 
typical ±2% from -55"C to 
+ 125°CCMRR 110 dB. 



TL/H/7387-11 



FIGURE 11. Gain of 1000 Instrumentation Amplifier 



233 



CD 



This instrumentation amplifier is limited to a maximum input 
signal of ± 1 mV for good linearity. At high signal levels the 
transfer characteristic of the LM121 becomes rapidly non- 
linear, as with any differential amplifier. Therefore, it is most 
useful as a high gain amplifier. 

Since feedback is not applied around the LM121, CMRR is 
not dependent on resistor matching. This eliminates the 
need for precisely matched resistor as with conventional 
instrumentation amplifiers. Although the linearity and gain 
stability are not as good as conventional schemes, this am- 
plifier will find wide application where low drift and high 
CMRR are necessary. 

A precision reference using a standard cell is shown in Fig- 
ure 12. The low drift and low input current of the LM121A 
allow the reference amplifier to buffer the standard cell with 
high accuracy. Typical long term drift for the LM121 operat- 



ing at constant temperature is less than 2 ju,V per 1000 
hours. 

To minimize temperature gradient errors, this circuit should 
be shielded from air currents. Good single-point wiring 
should also be used. When power is not applied, it is neces- 
sary to disconnect the standard cell from the input of the 
LM121 or it will discharge through the internal protection 
diodes. 

CONCLUSIONS 

A new preamplifier for operational amplifiers has been de- 
scribed. It can achieve voltage drifts as low as many chop- 
per amplifiers without the problems associated with chop- 
ping. Operating current is programmable over a wide range 
so the input characteristics can be optimized for the particu- 
lar application. Further, using a preamp and a conventional 
op amp allows more flexibility than a single low-drift op amp. 




• OUTPUTS 



TL/H/7387-12 



FIGURE 12. 10V Reference 



234 



LM125 

Precision Dual 
Tracking Regulator 



National Semiconductor 
Application Note 82 




00 

10 



INTRODUCTION 

The LM125 is a precision, dual, tracking, monolithic voltage 
regulator. It provides separate positive and negative regulat- 
ed outputs, thus simplifying dual power supply designs. Op- 
eration requires few or no external components depending 
on the application. Internal settings provide fixed output 
voltages at ± 1 5 V. 

Each regulator is protected from excessive internal power 
dissipation by a thermal shutdown circuit which turns off the 
regulator whenever the chip reaches a preset maximum 
temperature. Other features include both internal and exter- 
nal current limit sensing for device protection while operat- 
ing with or without external current boost. For applications 
requiring more current than the internal current limit will al- 
low, boosted operation is possible with the addition of a one 
NPN pass transistor per regulator. External resistors sense 
load current for controlling the limiting circuitry. Internal fre- 
quency compensation is provided on both positive and neg- 
ative regulators. The internal voltage reference pins is 
brought out to facilitate noise filtering when desired. 



CIRCUIT DESCRIPTION 

Figure 1 shows a block diagram of the basic dual tracking 
regulator. A voltage reference establishes a fixed dc level, 
independent of supply or temperature variations, at the non- 
inverting input to the negative regulator Error Amplifier. The 
Error Amplifier drives the Output Control Circuit which in- 
cludes the high current output transistors, current limiting, 
and thermal shutdown circuitry. 

The negative regulator output voltage is established by 
comparing the Voltage Reference against a fraction of the 
output as set by Ra and Rb- To achieve the desired tracking 
action of the positive regulator, a voltage established be- 
tween the positive and negative regulator outputs by resis- 
tors Re and Rq is compared to ground by the positive regu- 
lator Error Amplifier. This insures that the positive regulator 
output voltage will always equal the negative regulator out- 
put voltage multiplied by the unity ratio of Re to Rp. The 
positive regulator Output Control Circuit is essentially the 
same as that in the negative regulator. 
The current limit and thermal shutdown circuitry sense the 
output load current and die temperature respectively and 

POSITIVE 

UNREGULATED 

INPUT 

o 




POSITIVE 

■O REGULATED 

OUTPUT 



i i—AAAf 




u rf 



i_: 



NEGATIVE 

-O REGULATED 

OUTPUT 



I 



NEGATIVE 

UNREGULATED 

INPUT 



TL/H/7390-1 



FIGURE 1. Block Diagram for the Basic Dual Tracking Regulator 



235 



VOLTAGE 
REFERENCE 



(I ►! VSAr 



I 



"1 



I' 



'R13 



— I Q19 Q20 I— •-^^V 



81" " 



30 pF 



024 ] 4-T Q26 

n 




O-V 



-V,N 



TL/H/7390-2 



FIGURE 2. Simplified Negative Regulator 



switch off all output drive capability upon reaching their pre- 
determined limits. 

Figure 2 gives a more detailed picture of the negative regu- 
lator circuitry. The temperature compensated reference 
voltage appears at the non-inverting input of the differential 
amplifier, Q19 and Q20, while an error signal proportional 



+VinO 




+VOUT 



TL/H/7390-3 

FIGURE 3. Simplified Positive Regulator 

to any change in output voltage is applied to the other input. 
This error signal is amplified by the differential amplifier, 
Q19 and Q20, and by the triple Darlington Q21 , Q22, Q23 to 
produce a current change through R13 and R17 which 
brings the output voltage back to its original value. Loop 
gain is high, typically 88 dB at low output currents, so a 
30 pF compensating capacitor is used to guarantee stability. 
Since -Vout is the output of a high gain feedback amplifi- 
er, high supply rejection is ensured. 
Figure 3 shows the basic positive regulator. This is actually 
an inverting operational amplifier. The negative regulated 
voltage (-Vout) is applied to the current summing input 
through R14 while the output ( + Vqut) is fed-back via R9. 
Then +Vqut 'S simply — (R9/R14) (-Vout)- Anv change 



in the positive regulator output will create an error signal at 
the base of Q10 which will be amplified and sent to the 
voltage follower, Q4 and Q5, forcing the output voltage to 
track the input voltage. Here the loop gain is on the order of 
66 dB so a compensating capacitor of approximately 20 pF 
is used to ensure amplifier stability. 
The circuitry used for regulator start up, biasing, tempera- 
ture sensing, and thermal shutdown is shown in Figure 4. 
The field effect transistor Q28, is initially ON allowing the 
negative input voltage to force current through zener diode 
Q34. When enough current flows to fully establish the zener 
voltage, transistor Q29, Q30 and Q31 turn on and bias up all 
current sources. The zener voltage also decreases the gate 
to source voltage of the FET, pinching it off to a lower cur- 
rent value to reduce quiescent power dissipation. 
The thermal sensing and shutdown circuitry is comprised of 
Q34, Q29, Q35, Q32, Q37, Q38, R27, R29, R30, R31, and 
R33. The voltage divider made up of R29 and R30 provides 
a relatively fixed bias voltage Vi at the bases of Q35 and 
Q36, holding them in the OFF state. When the chip temper- 
ature increases to a maximum permissible level, the base to 
emitter voltage of Q35 and/or Q36 will have decreased suf- 
ficiently so that Vi is now high enough to turn them ON. This 
causes a voltage drop across R27 sufficient to turn on Q32 
which switches Q37 and Q38 to a conducting state shunting 
all output drive current to -Vin. The regulator output volt- 
ages are then clamped to zero. Transistors Q35 and Q36 
are located on the chip near the regulator output devices so 
they will see the maximum temperatures reached on the 
chip, ensuring that neither regulator will ever see more than 
this preset maximum temperature. The collectors of Q35 
and Q36 are tied together so that if either regulator reaches 
the thermal shutdown temperature, both regulators will 
shutdown. This ensures that the device can never be de- 
stroyed because of excessive internal power dissipation in 
either regulator. 

Figure 5 shows the current limiting circuitry used in the posi- 
tive regulator; the negative regulator current limiter is identi- 
cal. The internal current limiter is comprised of Q8 and R5; 
the external current limiter is comprised of Q1 1 and an ex- 
ternal resistor Rql- Both operate in a similar manner. As the 



236 




OB 



FIGURE 4. Start-up, Biasing and Thermal Shutdown Circuitry 



output current through Q5 increases, the voltage drop 
across resistor R5 eventually turns ON Q8 and shunts all 
base drive away from the output devices, Q4 and Q5. The 
maximum load current available with this circuit is approxi- 
mately 250 mA at Tj = 25°C (see Figure 9). 
The external current limiting circuit works in a similar man- 
ner. Here the output current is sensed across the external 
resistor Rcl- When the voltage drop across Rql is sufficient 
to turn ON transistor Q11, the output drive current is 




EXTERNAL PASS 
TRANSISTOR FOR 
BOOSTED OPERATION 



switched away from the output devices Q4 and Q5. This 
externally set current limit is particularly valuable when used 
with an external current boosting pass transistor where the 
current limit could be set to protect that transistor from ex- 
cessive power dissipation. 

The constant voltage reference circuit is shown in Figure 6. 
Zener diode Z<| has a positive temperature coefficient of 
known value. Vbe of Q18 (negative temperature coefficient) 
is multiplied by the ratio of R18 and R19 and added to the 
positive TC of Zi to produce a near zero TC voltage refer- 
ence. Current source I2 is used only during start-up. 




Ov REf 



►| Wr» to -Vout 



TL/H/7390-5 

FIGURE 5. Positive Regulator Current Limiting Circuitry 



TL/H/7390- 

FIGURE 6. Voltage Reference Circuitry 



237 



CM 
CO 



Figure 7 shows the complete schematic of the LM125 dual 
regulator. Diodes Q12 and Q17 protect the output transis- 
tors, plus any external pass devices used, from breakdown 
in the event the positive and negative regulated outputs be- 
come shorted. Transistors Q6 and Q7 offer full differential 
voltage gain with the convenience of single ended output. 
Transistors Q13 and Q33 insure that operation with ±30V 
input is possible. Q24 and Q26 in the negative regulator 
amplifier provide single ended output from a differential in- 
put with no loss in gain. 



APPLICATIONS 

The basic dual regulator is shown connected in Figure 8. 
The only connections required other than plus and minus 
inputs, outputs, and ground are to complete the output cur- 
rent paths from + Rql to + Vout a nd from _R CL t0 _v in- 
These may be a direct shorts if the internal preset current 
limit is desired, or resistors may be used to set the maximum 
current at some level less than the internal current limit. The 
internal 300fl resistors from pins 3 to 1 and pins 8 to 6 
should be shorted as shown when no external pass transis- 
tors are used. To improve line ripple rejection and transient 
response, filter capacitors may be added to the inputs, out- 




R21 R23 

2.0k 2.0k 



iX* y/* 3.0k [X tX • V| 

" — fe — tr*^'-— tr — \™ "ij 

> R3 ° i \ $ R33 n n r 

1 r 1 1 l 5 l 1 [ ,. 



R34 
1.0k 

-vs/v- 



R3S 
300 



-O -Rcl 



Note: Pin numbers apply to metal can package only. 
FIGURE 7. LM 125 



TL/H/7390-7 



238 




Note: Pin numbers for metal can package only. 

FIGURE 8. Basic Dual Regulator 



TL/H/7390-8 



puts, or both, depending on the unregulated input available. 
If a very low noise output voltage is desired, a capacitor may 
be connected from the reference voltage pin to ground. 
Thus shunting noise generated by the reference zener. Fig- 
ure 9 shows the internal current limiting characteristics for 
the basic regulator circuit of Figure 8. 

HIGH CURRENT REGULATOR 

For applications requiring more supply current than can be 
delivered by the basic regulator, an external NPN pass tran- 
sistor may be added to each regulator. This will increase the 
maximum output current by a factor of the external transis- 
tor beta. The circuit for current boosted operation is shown 
in Figure 10. 

In the boosted mode, current limiting is often a necessary 
requirement to insure that the external pass device is not 
overheated or destroyed. Experience shows this to be the 
usual cause of IC regulator failure. If the regulator output is 
grounded the pass device may fail and short, destroying the 
regulator. To limit the maximum output current, a series re- 
sistor (Rql in Figure 10) is used to sense load current. The 
regulator will current limit when the voltage drop across Rql 



1.00 

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ca 
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s5 



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V 




T 




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> s 




Tj - -5S°C ^ 


V 


"" llltr 1 - 




Tj ' +25°C 




1 1 1 T~T 




T 4 -+125°G 




tTI 1 1 




Tj«+150°C 




triiil 





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Tj-+150°C r 


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100 200 300 400 

'load -* ™* TL/H/7390-9 

(a) 

FIGURE 9. Internal Current Limiting Characteristics 



100 200 300 400 

iLOAD^mA TL/H/7390-10 

(b) 




TL/H/7390-11 



FIGURE 10. Boosted High Current Regulator 



239 



CM 
CO 



equals the current limit sense voltage found in Figure 11. 
Figure 12 shows the external current limiting characteristics 
unboosted and Figure 13 shows the external current limiting 
characteristics in the boosted mode. 
To ensure circuit stability at high currents in this configura- 
tion, it may he necessary to bypass each input with low 
inductance, tantalum capacitors to prevent forming reso- 
nant circuits with long input leads. A C > 1 ju,F is recom- 
mended. The same problem can also occur at the regulator 
output where aCs 10 ju,F tantalum will ensure stability and 
increase ripple rejection. 

-0.900 

S 0.800 

o 0.700 

z 0.600 

ui 

us 

t 0.500 

s 

k 0.400 

z 

£ 0.300 

" 0.200 

-SO -25 25 50 75 100 125 150 175 

JUNCTION TEMPERATURE (°C) 

TUH/7390-12 

FIGURE 11. Current Limit Sense Voltage for a 0.1% 
Change In Regulated Output Voltage 



























P( 


JSITIVE REG 
ENSE VOLTA 


JLA 
iE_ 


OR 




















































-N 


EGA 


rive 

SEI 


RE 
USE 


JUL 
i/OL 


kTO 
rAG 


E 







The 2N3055 pass device is low in cost and maintains a 
reasonably high beta at collector currents up to several 
amps. The devices 2N3055 may be of either planar or alloy 
junction construction. The planar devices, have a high fj 
providing more stable operation due to low phase shift. The 
alloy devices, with ij typically less than 1.0 MHz, may re- 
quire additional compensation to guarantee stability. The 
simplest of compensation for the slower devices is to use 
output filter capacitor values greater than 50 ju,F (tantalum). 
An alternative is to use an RC filter to create a leading 
phase response to cancel some of the phase lag of the 
devices. The stability problem with slower pass transistors, 
if it occurs at all, is usually seen only on the negative regula- 
tor. This is because the positive regulator output stage is a 
conventional Darlington while the negative output stage 
contains three devices in a modified triple Darlington con- 
nection giving slightly more internal phase shift. Additional 
compensation may be added to the negative regulator by 
connecting a small capacitor in the 100 pF range from the 
negative boost terminal to the internal reference. Since the 
positive regulator uses the negative regulator output for a 
reference, this also offers some additonal indirect compen- 
sation to the positive regulator. 

7 AMP REGULATOR 

In Figure 14 the single external pass transistor has been 
replaced by a conventional Darlington using a 2N3715 and 



p< 






1.0 
0.9 
0.8 
0.7 
0.6 
0.5 
0.4 
0.3 
0.2 
0.1 



1.0 
0.9 
0.8 
0.7 
0.6 
0.5 
0.4 
0.3 
0.2 
0.1 



1 1 ' 


\\ 




\ 




Tj = -55° C - 


4-1 




\ 




Tj = +25°C - 


-TT— 


^T~ 




Tj = +125°C v 


\\ 






T,=+150°Cv 


- n 












i 














\ 














\ 










+ - 1 




1 
















i 




_ 



S3 



> = 



1.0 
0.9 
0.8 
0.7 
0.6 
0.5 
0.4 
0.3 
0.2 
0.1 



1 1 w 


"1 T 


Tj = -55C JLJ 






Tj = +25" C 4\-\-L— 






Tj = +12'5 C N [\ \| 






T J = +150°c4 i \*jj 












A 












\ 














\ 


\ 












\ 


\ 












I 





60 70 

TL/H/7390-14 



it 



20 30 40 50 60 70 10 20 30 40 50 

'load (mA) TL7H/7390-13 Load (mA) 

(a) (b) 

FIGURE 12. External Current Limiting Characteristics-Unboosted 

1.0 
0.9 
0.8 
0.7 
0.6 
0.5 
0.4 
0.3 
0.2 
0.1 



0.40 0.60 0.80 1.00 1.20 1.40 o 0.20 0.40 0.6O 0.80 1.00 1.20 1.40 

■ LOAD (AMPS) TL/H/7390-15 I load (AMPS) TL/H/7390-16 

< a > (b) 

FIGURE 13. External Current Limiting Characteristics-Boosted 



I I 


w 


^ 




Tj = -55° C -- 




\ 




Tj = +25' C - 


V 


T 




Tj = +125"C\ 


^ 


Tj = +150°C x 


\l A 






















































Re 


l -0 








, ,. 



1 l> 


\ 


> 


1 


Tj = -55° C - 


1 \ 




L_J 


Tj = +25°C — 


TT 




\ 


Tj = +125°C x 


\\ 




\ 




Tj = +150°C x 


w 




\ 










v» 


\ 










\ 




\ 










\ 




\ 










I 




\ 










1 




I 



240 



• I • 4 +V, N -20V 

yS ST>> 1mF tantalum 
[2N3715 y> J_ 

■ • T 2N3772 



O +V ut = 15 




= -20V 



TL/H/7390-17 



FIGURE 14. High Current Regulator Using a Darlington Pair for Pass Elements 



a 2N3772. With this configuration the output current can 
reach values to 10A with very good stability. The external 
Darlington stage increases the minimum input-output volt- 
age differential to 4.5V. When current limit protection resis- 
tor is used, as in Figure 14, the maximum output current is 
limited by power dissipation of the 2N3772 (150W at 25°C). 
During normal operation this is (V|n - Vout) 'out (W), but it 
increases to Vin Isc (W) under short circuit conditions. The 
short circuit output current is then: 

. Pmax(T C = 25°C) 

isc = - 



Vin 



150W 



7.5A max. 



20V (min) 

l[_ could be increased to 10A or more only if Isc < 'l- A 
foldback current limit circuit will accomplish this. The typical 
load regulation is 40 mV from no load to a full load. (Tj = 
25°C, pulsed load with 20 ms toN and 250 ms toFF)- 

FOLDBACK CURRENT LIMITING 

In many regulator applications, the normal operation power 
dissipation in the pass device can easily be multiplied by a 
factor of ten or more when the output is shorted. This may 
destroy the pass device, and possibly the regulator, unless 
the heat sink is oversized to handle this fault condition. A 
foldback current limiting circuit reduces short circuit output 
current to a fraction of the full load output current thus 



avoiding the need for larger heat sink. Figure 15 shows a 
foldback current limiting circuit on both positive and nega- 
tive regulators. 

The foldback current limiting, a fraction of the output voltage 
must be used to oppose the voltage across the current limit 
sense resistor. Current limiting does not occur until the volt- 
age across the sense resistor is higher than this opposing 
voltage by the amount shown in Figure 1 1. When the output 
is grounded, the opposing voltage is no longer present so 
current limiting occurs at a lower level. This is accomplished 
in Figure 15 by using a programmable current source to give 
a constant voltage drop across R5 for the negative regula- 
tor, and by a simple resistor divider for the positive regula- 
tor. The reason for the difference between the two is that 
the negative regulator current limiting circuit is located be- 
tween the output pass transistor and the unregulated input 
while the positive regulator current limiter is between the 
output pass transistor and the regulated output. 
The operation of the positive foldback circuit is similar to 
that described in NSC application note AN-23. A voltage 
divider R1 and R2 from Ve to ground creates a fixed voltage 
drop across R1 opposite in polarity to the drop across 
RrjL + - When the load current increases to the point where 
the drop across Rci_ + " s equal to the drop across R1 plus 
the current limit sense voltage given in Figure 1 1, the posi- 
tive regulator will begin to current limit. As the positive out- 
put begins to drop, the voltage across R1 will also decrease 
so that it now requires less load current to produce the cur- 



241 



CM 
CO 



h* — vw 




^ WSr 




+v IN 



CI — JUi- I^F 

«^TN TANTALUM 



O + Vout 




02 -03: 2N2640 



FIGURE 15. Foldback Current Limiting Circuit 



TL/H/7390-18 



rent limit sense voltage. With the regulator output fully short- 
ed to ground (+Vout = 0) the current limit will be set by 
the value of + Rcl alone. 



If 



Isc 



then the following equations can be used for calculating the 
positive regulator foldback current limiting resistors. 

+ = V SENSE 



Rcl" 



•so 



where Vsense is f rom Figure 1 1. 

At the maximum load current foldback point: 

V RCL + = lFBRCL + 

Vri = Vrcl + - Vsense 
Vri = IfbRcl + _ Vsense 



Then 



and 



R1 = 



Vri 



R2 



_ + Vqut + Vsense 



0) 

(2) 
0) 

(4) 

(5) 
(6) 



The only point of caution is to ensure that the total current 
(li) through R2 is much greater than the current contribution 
from the internal 300ft resistor. This can be checked by: 

Ifb Rcl + 



300 



<<li 



(7) 



Note: The current from the internal 300ft resistor is V3.1/ 

300ft, but V3.1 = V B e +Vrcl - Vsense + assuming V B e 

~ Vsense + at t ne foldback point, V3.1 ~ Vrcl + = 'fb 

Rcl + - 

Design example: 2 amp regulator LM125 positive foldback 

current limiting (see Figure 15). 

Given: 

'foldback = 2 - 0A 

ISHORT-CIRCUIT = 500 mA 

Vsense (See Figure 1 1) 

+ V| N = 25V 

+ V UT = 15V 

^PASS DEVICE = 70 

e JA = 150°c/w 

T A = 50°C 
With a beta of 70 in the pass device and a maximum output 
current of 2.0A the regulator must deliver: 

2A 

/3 

The LM125 power dissipation will be calculated ignoring any 
negative output current for this example. 

PLM125 =(V|n - Vout) 'OUT 

= (25 - 15) 29 mA 

= 290 mW 

Trise @ 0ja = 150°C/W = 150°C X 0.29 = 44°C 

Tj = T A + Trise = 50°C + 44°C = 94°C 



2A 

— = 29 mA 

70 



242 



From Figure 1 1: 

VsenSE @ (Tj = 94°C) = 520 mW 
From equation (1) 

VsENSE 520 mV 



Rcl h 



= 1ft 



Isc 500 mA 

From equation (2) 

Vrcl + = Ifb Hcl + = (2A)(m) = 2V 
From equation (3) 

VR1 = V RC L + - VsENSE 
V R1 = 2V - 520 mV = 1.480V 
A value for \-\ can now be found from equation (7) 
l FB R CL+= 2Axin 
300 3oon 

So set li = 10 X 6.6 mA = 66 mA 
From equations (5) and (6) 

V R1 1.480V 

R1= i7 = i6^r 22ft 

R2 = +VQUT + VSENSE.. 15 + 0-520 a24Qn 
li 66 mA 

The foldback limiting characteristics are shown in Figure 16 
for the values calculated above at various operating temper- 
atures. 

16 
14 



> 


12 


UJ 




ca 

< 


10 






-X 




o 
> 


8.0 


i- 






6.0 


3 




o 


4.0 




2.0 



















































































Ti = +1?5° 


c/// 




























L/ T i = 


-55°C 


























25° C 








V 







0.5 



2.0 



2.5 



1.0 1.5 
Iout (AMPS) 

TL/H/7390-19 

FIGURE 16. Positive Regulator Foldback 
Current Limiting Characteristics 

The negative regulator foldback current limiting works es- 
sentially the same way as the positive side. Q1 forces a 
constant current, I2, determined by -Vout and R3, through 
Q2. Transistors Q2 and Q3 are matched so a current identi- 
cal to I3 will flow through Q3. With the output short-circuited 
(-Vout = 0), Q1 will be OFF, setting l 2 = 0. The load 
current will be limited when V-j increases sufficiently due to 
load current to make V2 higher than -Vin by the current 
limit sense voltage. 
The short circuit current is: 



'sc = 



Vsense 
Rcl" 



(8) 



For calculating the maximum full load current with the out 
put still in regulation, current I2 

Vout _ Vbeqi 



l 2 = 



R3 



0) 



At the point of maximum load current, Ifb. where the regula- 
tor should start folding back: 

V1 = -V| N + i FB R CL - do) 

and 

v 2 = -V| N + Vsense flD 

The current through Q2 (and Q3) will have increased from l 2 
by the amount of I4 due to the voltage V-| increasing above 
its no-load quiescent value. Since the voltage across Q2 is 
simply the diode drop of a base-emitter junction: 

. [V1 - (-Vin)] - Vbe 

' 4 = fm 

Substituting in equation (10) gives: 

, _ 'fbRcl" - V BE 



R4 



'fb Rcl - v BE 



(12) 



300ft 
The current through Q2 is now 

l 3 = l 2 + l 4 (13) 

and the current through Q3 is: 

l 3 = l 5 + ie - I? (14) 

The drop across R5 is found from: 

V! - v 2 = (-V| N + i FB R CL -) - [Vsense + (-Vin)1; 
simplifying, 

V1 - v 2 = Ifb Rcl" - Vsense (15) 
Since Vsense ' s tne base to emitter voltage drop of the 
internal limiter transistor, the Vsense in equation (1 5) very 
nearly equals the Vbe in equation (12). Therefore the drop 
across R5 approximately equals the drop across R4. The 
current through R5, I5, can now be determined as: 

'fb r cl - - Vsense 



l 5 = 



R5 



(16) 



Summing the currents through Q3 is now possible assuming 
the base-emitter drop of the 2N3055 pass device can be 
given by V B e ~ Vsense: 

V 3 -V 2 



' 6 = 300 
where V3 = v-\ + Vbe ~ v 1 + Vsense 
V1 + Vsense - v 2 



(17) 



<6 

Substituting in equation (15) 



300 



. = 'fb r cl" 
6 300 

v 2 ~ (-Vin) 
R6 



(18) 



Vsense 
R6 



243 



Equating equation (13) with equation (14) and inserting re- 
sistor values shown in Figure 15, 

l 2 + l 4 = Is + le ~ I? 

'fB RCL~ ~ VSENSE _ 



300 
>FB R CL - V SENSE 



(19) 



300 



300 



'2 + 
I5 + 

Canceling, we find: 

"2 = Is (20) 

This is the key to the negative foldback circuit. Current 
source Q1 forces current I2 to flow through resistor R5. The 
voltage drop across R5 opposes the normal current limit 
sense voltage so that the regulator will not current limit until 
the drop across Rcl - due to load current, equals the con- 
trolled drop across R5 plus Vsense (given in Figure 11). 
This can be written as: 

Vsense +I2R5 



Ifb = 



Ifb 



Rcl- 

VSENSE + 200 l 2 



(21) 



Rcl- 

A design example is now offered: 
Given: 

'FOLDBACK = 2.5A 
'short-circuit = 750 mA 
Vsense ( Se e Figure 11) 
-V| N = 25V 
-V UT= -15V 
0PASS DEVICE = 90 
JA = 150°C/W 
T A = 25°C 
The same calculations are used here to figure Vsense as 
with the positive regulator foldback example maximum regu- 
lator output current is calculated from: 
2.5A 
90 

P LM125 = (V|N ~ Vo) 'OUT 

= 10V X 28 mA 

= 280 mW 

Trise = 150°C/W X 0.28W = 42°C 

Tj = T A + Trise = 25°C + 42°C = 67°C 

From Figure 1 1: 

Vsense = 500 mv 
From equation (8): 

500 mV 



'OUT 



28 mA 



Rcl - = 



750 mA 
From equation (21): 

, _ Ifb Rcl" _ Vsense 



= o.68n 



200ft 



= 6.0 mA 



From equation (9): 



R3 = 



Vqut _ Vbeqi 



R3 = 



14.3 
6.0 mA 



= 2.4k 




o 4.0 



0.5 1.0 1.5 2.0 2.5 3.0 

Iout (A) 

TL/H/7390-20 

FIGURE 17. Negative Regulator Foldback 
Current Limiting Characteristics 

Figure /6and 77 show the measured foldback characteris- 
tics for the values derived in the design examples. The val- 
ue of R5 is set low so that the magnitude of I5 for foldback is 
greater than I4 through l6- This reduces the foldback point 
sensitivity to the TC of the internal 300ft resistor and any 
mismatch in the TC of Q2, Q3 or the pass device. 
R6 can be computed from equation (1 8): 

Vsense - _ Vsense - 



R6 = 

17 
combining (13) and (20). 

Vsense" 



R6 



le-U 



Is + 'e ~ 'a 



Vsense" 



Ifb Rcl 



\300 R4/ 



Yje 
R4 



(22) 



Setting Vbe = Vsense a nd R4 = 300 to match the internal 
300ft (22) becomes: 

R6 = R4 

Also setting — = ► R5 = 200 

Is 3 

A 10 AMP REGULATOR 

Figure 18 illustrates the complete schematic of a 10A regu- 
lator with foldback current limiting. The design approach is 
similar to that of the 2A regulator. However, in this design, 
the current contribution from the internal 300ft resistor is 
greater due to the 2 Vbe drop across the Darlington pair. 
Expression (7) becomes: 

Ifb Rcl + + Vbe ... 

300 n (23) 

and, for the negative regulator, expression (22) becomes: 
Vsense ~ 



R6 = 



lFBRcL "[i55-Rl] +VBE [3^0 + Rl] 



(24) 



244 



z 

do 




TL/H/7390-22 



FIGURE 18. 10A Regulator with Foldback Current Limiting 



The disagreement between the theoretical and experimen- 
tal values for the negative regulator is not alarming. In fact 
Rcl was based on equation (8), which is correct if for zero 
Vqut. '5 is zer0 as wel1 - Tnis implies: 



V S ENSE(atSC) = 



VBEQ4 + VBEQ5 



(at SC) 



which is a first order approximation. 
Figure 19 illustrates the power dissipation in the external 
power transistor for both sides. Maximum power dissipation 
occurs between full load and short circuit so the heat sink 
for the 2N3772 must be designed accordingly, remembering 
that the 2N3772 must be derated according to 0.86W/°C 
above 25°C. This corresponds to a thermal resistance junc- 
tion to case of 1.1 7°C/W. 



150 

120 

K 90 























T A = 


25° C 
























V IN = 22V 
Vout^15V 
Ifb = 10A 
Isc" = 2.9A 
Isc* = 2.9A 

























































































































































































































































































































5.0 10 

Vout 



TL/H/7390-21 



FIGURE 19. Power Dissipation in the 
External Pass Transistor (Q5, Q7) 



245 



Example 



Positive Side 



IFB = 10A 

ISC = 2.5A 

V, N = 22V 

V OU T= 15V 

y3 = £1 /82 = 15 X 50 = 750 min 

T A = 25°C 



Theoretical Value 



l 12 5 = 13 mA 
PLM125= 150mW 
Rcl + = 0.26ft 
R1 = 21ft 
R2 = 130ft 
VsENSE + = 650 mV 



Experimental Results 



l FB = 9.8A 
ISC = 2.9A 
R C L + = 0.26ft 
Readjusted to 20ft 
R2: adjusted to 120ft 



Negative Side Theoretical Value 

lFB = 10A R CL - = 0.22ft 

Isc = 2.5A R4 = 300ft 

V| N = 22V R5 = 200ft 

V UT=15V R6= 150ft 

P = 800 R3 = 1.6 kft 

T A = 25° V S ENSE~ = 550 mV 

"5 3 
Note: For this example, in designing each side, the power dissipation of the opposite side has not been taken into the account. 



Experimental Results 



Ifb = 10A 

ISC = 2.9A 
Rcu adjusted to 0.3ft 
R6: adjusted to 130ft 
R3: adjusted 900ft 



POSITIVE CURRENT DEPENDENT SIMULTANEOUS 
CURRENT LIMITING 

The LM125 uses the negative output as a reference for the 
positive regulator. As a consequence, whenever the nega- 
tive output current limits, the positive output follows tracks 
to within 200-800 mV of ground. If, however, the positive 
regulator should current limit the negative output will remain 
in full regulation. This imbalance in output voltages could be 
a problem in some supply applications. 
As a solution to this problem, a simultaneous limiting 
scheme, dependent on the positive regulator output current, 
is presented in Figure 20. The output current causes an l-R 
drop across R1 which brings transistor Q1 into conduction. 
As the positive load current increases l-j increases until the 
voltage drop across R2 equals the negative current limit 
sense voltage. The negative regulator will then current limit, 
and positive side will closely follow the negative output 
down to a level of 700-800 mV. For Vout + to drop the 
final 700-800 mV with small output current change, Rcl + 
should be adjusted so that the positive current limit is slight- 
ly larger than the simultaneous limiting. Figure 21 illustrates 
the simultaneous current limiting of both sides. 



The following design equations may be used: 
R1 l CL + = R3 U + V BEQ1 

■ _ V SENSE~ 
ll ""~ R2~~ 
Combining (25) and (26), 



with 



ICL H 



Rci/ 



R3 

^V S ENSE~ + V B EQ1 

Si 



V SENSE" 



(25) 
(26) 



(27) 



(28) 



1.1I CL + 

The negative current limit (independent of Icl + ) can be set 
at any desired level. 

vsense~ + v diode 
Rcl- 

Transistor Q2 turns off the negative pass transistor during 
simultaneous current limiting. 



ICL" 



(29) 



246 



+V IN 



^* VW- 



^* VSAr 




LM125 



> 

z 

I 
00 

ro 



— I— \nf 
^TN TANTALUM 




TANTALUM 



-V,n 

FIGURE 20. Positive Current Dependent Simultaneous Current Limiting 



TL/H/7390-23 



16 
14 
12 
10 
8.0 
6.0 
4.0 
2.0 



0.5 1.0 1.5 2.0 2.5 

POSITIVE OUTPUT CURRENT (AMPS) 

TL/H/7390-24 

FIGURE 21. Positive Current Dependent 
Simultaneous Shutdown 

ELECTRONIC SHUTDOWN 

In some regulated supply applications it is desirable to shut- 
down the regulated outputs (±Vo = 0) without having to 
shutdown the unregulated inputs (which may be powering 
additional equipment). Various shutdown methods may be 











+ 3(1«- 




\ 


\ 


\ 


-R«. + = 0.68O- 

ri = i.on 






i 


A 


















1 








T 










^ 




















r l 










' T, 


- 55°r 




















I 












\ 












\ 








v 


\ 








\ 


\ 







used. The simplest is to insert a relay, a saturated bipolar 
device, or some other type switch in series with either the 
regulator inputs or outputs. The switch must be able to open 
and close under maximum load current which, may be sev- 
eral amps. 

As an alternate solution, the internal reference voltage of 
the regulator may be shorted to ground. This will force the 
positive and negative outputs to approximately +700 mV 
and + 300 mV respectively. Both outputs are fully active so 
the full output current can still be supplied into a low imped- 
ance load. If this is unacceptable, another solution must be 
found. 

The circuit in Figure 22 provides complete electronic shut- 
down of both regulators. The shutdown control signal is in- 
compatible but by adjusting R8 and R9 the regulator may be 
shutdown at any desired level above 2 Veg, calculated as 
follows: 

[R8 R9l 
+ — V B E + 2 V BE (30) 
R3/3Q4 R3J bfc Bt ; 

Positive and negative shutdown operations are similar. 
When a shutdown signal Vj is applied, Q4 draws current 
through R3 and D2 establishing a voltage Vr which starts 



247 



CM 
00 




2.2k V T SHUTD owN 
CONTROL 
'A) INPUT 



C2 

1 - IOmF 

TANTALUM 



30V +I7 TANTALUM 

•For higher values of C1 increase R6 to limit the peak current through Q5 to a safe value. 

FIGURE 22. Electronic Shutdown for the Boosted Regulator 



TL/H/7390-25 



248 



the current sources Q1 and Q2. Assuming that Q1 and Q2 
are matched, and making R1 = R2 = R3, the currents l-|, 
I2, I3 are equal and both sides of the regulator shutdown 
simultaneously. 

The current I3 creates a drop across R5, which equals or 
exceeds the limit sense voltage of the positive regulator, 
causing it to shutdown. Since I3 has no path to ground ex- 
cept through the load, a fixed load is provided by Q5, which 
is turned on by the variable current source Q4, C1 also dis- 
charges through Q5 and current limiting resistor R6. Resis- 
tor R4 prevents Q3 turn on during shutdown, which could 
otherwise occur due to the drop across R5 plus the internal 
300ft resistor. Diode D3 prevents I3 from being shunted 
through Rql- 

C2 discharges through the load. Q7 shares the total supply 
voltage with Q2, thus limiting power dissipation of Q2. An- 
other power dissipation problem may occur when the design 
is done for Vt = 2.0V for example, and Vt is increased 
above the preset threshold value. I1 is increased and Q4 
has to dissipate (V| N - 3 V B e - V T ) H (W). The simplest 
solution is to increase R8. If this is insufficient, a set of di- 
odes may be added between nodes A and B to clamp, l-| to 
a reasonable value. This is illustrated in Figure 23: 
V BE - [Vt ~ 2 V BE ] _ Vbe 
R9 



' 1 ~ -R9 = ~~ 



R9 




Vr9 ^ Vt ~ Vbe - (Vt - 2 Vbe) _ Vbe 
R9 R9 R9 



TL/H/7390-26 



FIGURE 23 



So I1 is made independent of Vt and by setting a minimum 
value of 10 mA (R9 = 70ft). The regulator will shutdown at 
any desired level above 3 Vbe. without overheating transis- 



tor Q4. Also using Figure 23 the diode D1 in Figure 22 may 
be omitted. The shutdown characteristics of Figure 22 are 
shown in Figure 24. 



20 




























































lb 




"N 




\ \ 














T 








"T; =+125°C 




I 




















10 



























^ Tj = +Z3 u_ 














1 










































Tj = -55°C 


9.0 


































































, 




1 


■ 





1.0 



4.0 



5.0 



2.0 3.0 

V T (V) 

TL/H/7390-27 

FIGURE 24. Electronic Shutdown Characteristics 



Id 



(31) 



The normal current limiting current is set by equation (31) 
VSENSE + VpiODE 

Rcl 

The same approach is used with the unboosted regulator 
shown in Figure 25. In this case the voltage sense resistor is 
the internal 300ft one. Since output capacitors are no long- 
er required Q3 is just used as a current sink and its emitter 
load has been removed. 

POWER DISSIPATION 

The power dissipation of the LM125 is: 

Pd = (V| N + - V UT + ) IOUT+ + (V| N - 

- VoUT - ) 'OUT - + V| N + l S + + V IN - l S - 

where Is is the standby current. 

Ex: ±1A regulator using 2N3055 pass transistors. Assum- 
ing a = 100, and ±25V supply, 

P d = 400 mW. 
The temperature rise for the TO-5 package will be: 

Trise = 0.4 X 150°C/W = 60°C 
Therefore the maximum ambient temperature is Tamax = 
Tjmax _ T RISE = 90 ° c - ,f tne device is to operate at Ta 
above 90°C then the TO-5 package must have a heat sink. 
Trise ' n tn ' s case wi " De: 

Trise = Pd («j-c + «c-s + s-a)- 



00 
10 



249 



V,n - 27V 




LM125 





i — °-* — r 

10 k. 

O— i QfN 

„„ -i" 2N2102 J 
g REF - #4 



-O -Vout = -15 V 



u 



'D2 
.1N914 



D1 
1N914 




ImF' 
TANTALUM" 



-► -V 1N = -27V 



TL/H/7390-28 



FIGURE 25. Electronic Shutdown for the Basic Regulator 



250 



Comparing the High Speed Z^^T° r WA 
Comparators lnterface JlA 

Development Group ^Bi^^H 

INTRODUCTION 

Several integrated circuit voltage comparators exist which timum device for the intended usage. Optimized parameters 
were designed with high speed and complementary TTL include speed, input accuracy and impedance, supply volt- 
outputs as the main objectives. The more common applica- age range, fanout, and reliability. The LM160/LM260/ 
tions for these devices are high speed analog to digital (A to LM360 are replacement devices for the jaA760, while the 
D) converters, tape and disk-file read channels, fast zero- LM161/LM261/LM361 replace the SE/NE529. Tables I and 
crossing detectors, and high speed differential line receiv- II compare the critical parameters of the National commer- 
ers. This note compares the National Semiconductor devic- cial range devices to their respective counterparts, 
es to similar devices from other manufacturers. SPEED 

The product philosophy at National was to create pin-for-pin Th hout the unjverse the subject of s d must be ap _ 
replacement circurfs that could be considered as second- erf ^ c ^ same hQ|ds ^ here s d 
sources to the other comparators, wh.le simultaneously f tion del time) is a function of the measurement 
containing the improvements necessary to make a more op- 

TABLE I. LM360/juA760C Comparison 0°C < T A <; + 70°C,V + = +5.0V,V~ = -5.0V 


Parameter 


LM360 


IXA760C 


Units 


Input Offset Voltage 


5.0 


6.0 


mVmax 


Input Offset Current 


3.0 


7.5 


jxAmax 


Input Bias Current 


20 


60 


jLtAmax 


Input Capacitance 


4.0 


8.0 


pFtyp 


Input Impedance 


17 


5.0 


kfi typ @ 1 MHz 25°C 


Differential Voltage Range 


±5.0 


±5.0 


Vtyp 


Common Mode Voltage Range 


±4.0 


±4.0 


Vtyp 


Gain 


3.0 


3.0 


V/mV typ 25° 


Fanout 


4.0 


2.0 


74 Series TTL Loads 


Propagation Delays: 








(1) 30 mVp-p 10 MHz Sinewave in 


25 


30 


ns max 25° 


(2) 2.0 Vp-p 10 MHz Sinewave in 


20 


25 


ns max 25° 


(3) 1 00 mV Step + 5.0 mV Overdrive 


14 


22 


ns typ 25° 


TABLE II. LM261/NE529 Comparison 0°C^T A ^ + 70°C,V+ = + 10V,V~ = -10V,V C c= +5.0V 


Parameter 


LM261 


NE529 


Units 


Input Offset Voltage 


3.0 


10 


mVmax 


Input Offset Current 


3.0 


15 


jaAmax 


Input Bias Current 


20 


50 


juAmax 


Input Impedance 


17 


5.0 


kft typ @ 1 MHz 25°C 


Differential Voltage Range 


±5.0 


±5.0 


Vtyp 


Common Mode Voltage Range 


±6.0 


±6.0 


Vtyp 


Gain 


3.0 


4.0 


V/mV typ 25° 


Fanout 


4.0 


6.0 


74 Series TTL Loads 


Propagation Delay - 50 mV Overdrive 


20 


22 


ns max 25° 





251 



technique. The earlier "standard" of using a 100 mV input 
step with 5.0 mV overdrive has given way to seemingly end- 
less variations. To be meaningful, speed comparisons must 
be made with identical conditions. It is for this reason that 
the speed conditions specified for the National parts are the 
same as those of the parts replaced. 
Probably the most impressive speed characteristic of the six 
National parts is the fact that propagation delay is essential- 
ly independent of input overdrive (Figure /); a highly desir- 



18 










r 


mini 




iiiii 




1 




V 


=e = +5V 


16 








LOAD = 2.0 kn 








T 


3\ 


'cc 


+ 1 


SpF 


Tl 


3T/i 


kL 


14 














































12 














































10 















































1.0 3.0 10 30 100 300 1000 
DIFFERENTIAL INPUT OVERDRIVE (mV) 

TL/H/7407-1 

FIGURE 1. Delay vs Overdrive 

able characteristic in A to D applications. Their delay typical- 
ly varies only 3 ns for overdrive variations of 5.0 mV to 500 
mV, whereas the other parts have a corresponding delay 
variation of two to one. As can be seen in Tables I and II, 
the National parts have an improved maximum delay speci- 
fication. Further, the 20 ns maximum delay is meaningful 
since it is specified with a representative load: a 2.0 kfi 
resistor to + 5.0V and 1 5 pF total load capacitance. Figure 
2 shows typical delay variation with temperature. 





24 
20 
16 
12 


n 


















g 


_ LOAD = 2.0 kfi 
TO V cc +15pFT0T/ 








>- 
< 


a 








a 


Vi 


N - 
















z 
a 




















i- 
< 


































tr- 


io 




a. 



































25 

T A <°C> 



125 



TL/H/7407-2 



FIGURE 2. Delay vs Temperature 

INPUT PARAMETERS 

The A to D, level detector, and line receiver applications of 
these devices require good input accuracy and impedance. 
In all these cases the differential input voltage is relatively 



large, resulting in a complete switch of input bias current as 
the input signal traverses the reference voltage level. This 
effect can give rise to reduced gain and threshold inaccura- 
cy, dependent on input source impedances and comparator 
input bias currents. Tables I and II show that the National 
parts have a substantially lower maximum bias current to 
ease this problem. This was done without resorting to Dar- 
lington input stages whose price is higher offset voltages 
and longer delay times. The lower bias currents also raise 
input resistance in the threshold region. Lower input capaci- 
tance and higher input resistance result in higher input im- 
pedance at high frequencies. 

Even with low source impedances, input accuracy is still 
dependent on offset voltage. Since none of the devices un- 
der discussion has internal offset null capability, ultimate ac- 
curacy was improved by designing and specifying lower 
maximum offset voltage. Refer to Figure 3 for typical offset 
voltage drift with temperature. 



> 0.8 

E 

Z °- 6 

« 0.4 
= 0.2 
t 

Urn 

S -°-2 
5 -0.4 
5 -0.6 
































































































































s» 





































-55 



-15 



65 



125 



25 

Ta <°C) 

TL/H/7407-3 

FIGURE 3. Offset Temperature Coefficient 

OTHER PERFORMANCE AREAS 

In the case of the LM160/LM260/LM360, fanout was dou- 
bled over the previous device. For the LM161/LM261/ 
LM361, operating supply voltage range was extended to 

7.0 




9.0 11 

V + OR V" (iV) 

TL/H/7407-4 

FIGURE 4. LM161 Common Mode Range 

±15V op amp supplies which are often readily available 
where such a comparator is used. Figure 4 reveals the com- 
mon mode range of the latter device. 



252 



The performance improvements previously mentioned were 
a result of circuit design (Figures 5 and 6) and device pro- 
cessing. Schottky clamping, which can give rise to reliability 
problems, was not used. Gold doping, which results in pro- 
cessing dependent speeds and low transistor beta, was not 
used. Instead a non-gold-doped process with high break- 
down voltage, high beta, and high fj (~1.5 GHz) was se- 



lected which produced remarkably consistent performance 
independent of normal process variation. The higher break- 
down voltage allows the LM161/LM261/LM361 to operate 
on ±15V supplies and results in lower transistor capaci- 
tance; higher beta provides lower input bias currents; and 
higher fj helps reduce propagation time. 



00 



v + o 



-INPUT 2 O- 




O OUTPUT 2 



v-O- 



S=2 



TL/H/7407-5 



FIGURE 5. LM161 Schematic Diagram 



253 



r^ 

CO 



NON- 
O INVERTING 
OUTPUT 1 



V + Q » 



- INPUT 2 O 



V"0 




TL/H/7407-6 



FIGURE 6. LM160 Schematic Diagram 



APPLICATIONS 

Typical applications have been mentioned previously. The 
LM160 and LM161 may be combined as in Figure 7 to cre- 
ate a fast, accurate peak detector for use in tape and disk- 
file read channels. A 3-bit A to D converter with 21 ns typical 
conversion time is shown in Figure 8. Although primarily in- 



tended for interfacing to TTL logic, direct connection may 
be made to ECL logic from the LM161 by the technique 
shown in Figure 9. When used this way the common mode 
range is shifted from that of the TTL configuration. Finally 
level detectors or line receivers may be implemented with 
hysteresis in the transfer characteristic as seen in Figure 10. 



254 




u 



T 



00 





_bOcJ-^v 



> > ' LM16 
£ Rl < H2 I 



FIGURE 7. Peak Detector 




i- 




R9 I 

WV ' 





RIO I 






^> 



, — TD^ 



jj3^.. 



CM 



Oi 



TL/H/7407-7 



TL/H/7407-8 



FIGURE 8. High Speed 3-bit A to D Converter 



255 



i-i\i<y CM <+2\i) i 




1 



1 >2k >2k 



£& 



DM10101 



■ *^— o 



-10V -5.2 

FIGURE 9. Direct Interfacing to ECL 



TL/H/7407-9 




OUT 



V, 



TL/H/7407-10 



v ut = Voh(^)-Vol(^) 

V L T = V OL (^)-Vo H (g) 

FIGURE 10. Level Detector with Hysteresis 



256 



CMOS Linear Applications 



National Semiconductor 
Application Note 88 



a 



PNP and NPN bipolar transistors have been used for many 
years in "complementary" type of amplifier circuits. Now, 
with the arrival of CMOS technology, complementary 
P-channel/N-channel MOS transistors are available in 
monolithic form. The MM74C04 incorporates a P-channel 
MOS transistor and an N-channel MOS transistor connect- 
ed in complementary fashion to function as an inverter. 
Due to the symmetry of the P- and N-channel transistors, 
negative feedback around the complementary pair will 
cause the pair to self bias itself to approximately 1/2 of the 
supply voltage. Figure 1 shows an idealized voltage transfer 
characteristic curve of the CMOS inverter connected with 
negative feedback. Under these conditions the inverter is 
biased for operation about the midpoint in the linear seg- 
ment on the steep transition of the voltage transfer charac- 
teristics as shown in Figure 1. 



5 75 



^ 


V CC = '5V 




^ 



7.5 



INPUT VOLTAGE - V,„ 

TL/F/6020-1 

FIGURE 1. Idealized Voltage Transfer 
Characteristics of an MM74C04 Inverter 

Under AC Conditions, a positive going input will cause the 
output to swing negative and a negative going input will 
have an inverse effect. Figure 2 shows 1/6 of a MM74C04 
inverter package connected as an AC amplifier. 
The power supply current is constant during dynamic opera- 
tion since the inverter is biased for Class A operation. When 
the input signal swings near the supply, the output signal will 
become distorted because the P-N channel devices are 
driven into the non-linear regions of their transfer character- 




TL/F/6020-2 

FIGURE 2. A 74CMOS Inverter Biased for 
Linear Mode Operation 

istics. If the input signal approaches the supply voltages, the 
P- or N-channel transistors become saturated and supply 
current is reduced to essentially zero and the device be- 
haves like the classical digital inverter. 

15 





^s) 


\ 




v cc 


= 15V 






\ 








1 


>S"r \ 


55°C 

/ 


55°C 

/ 






n! 


\ 








N 


55°C 

/ 


\ 


v 






s 

1Z5°C 


^ 


\ 


v 


^ 


*■*_ 



2.5 5.0 7.5 10 12.5 15 

INPUT VOLTAGE - V |W 

TL/F/6020-3 

FIGURE 3. Voltage Transfer Characteristics for an 
Inverter Connected as a Linear Amplifier 

Figure 3 shows typical voltage characteristics of each in- 
verter at several values of the Vcc- Tne shape of these 
transfer curves are relatively constant with temperature. 
Temperature affects for the self-biased inverter with supply 
voltage is shown in Figure 4. When the amplifier is operating 
at 3 volts, the supply current changes drastically as a func- 
tion of supply voltage because the MOS transistors are op- 
erating in the proximity of their gate-source threshold volt- 
ages. 



257 



00 
00 




-75 -50 -25 



50 75 100 125 



TEMPERATURE 

TL/F/6020-4 

FIGURE 4. Normalized Amplifier Supply Current 
Versus Ambient Temperature Characteristics 

Figure 5 shows typical curves of voltage gain as a function 
of operating frequency for various supply voltages. 
Output voltages can swing within millivolts of the supplies 
with either a single or a dual supply. 





50 




V CC =3.0V 














40 
30 




V cc = 5.0 V 




J^ 


v cc = '» v \ \ 


u 




< 




v cc 


+16V \ \\ 


o 
> 


20 
10 




1 1 


i i \ i \ YV i 



10 2 



10' 



10» 



10 3 10 4 10 s 

OPERATING FREQUENCY -Hi 

TL/F/6020-5 

FIGURE 5. Typical Voltage Gain Versus Frequency 
Characteristics for Amplifier Shown in Figure 2 

APPLICATIONS 

Cascading Amplifiers for Higher Gain 

By cascading the basic amplifier block shown in Figure 2 a 
high gain amplifier can be achieved. The gain will be multi- 
plied by the number of stages used. If more than one invert- 
er is used inside the feedback loop (as in Figure 6) a higher 
open loop gain is achieved which results in more accurate 
closed loop gains. 



'" 1MS2 



FIGURE 6. Three CMOS Inverters 
Used as an X10 AC Amplifier 




Post Amplifier for Op Amps 

A standard operational amplifier used with a CMOS inverter 
for a Post Amplifier has several advantages. The operation- 
al amplifier essentially sees no load condition since the in- 
put impedance to the inverter is very high. Secondly, the 
CMOS inverters will swing to within millivolts of either sup- 
ply. This gives the designer the advantage of operating the 
operational amplifier under no load conditions yet having 
the full supply swing capability on the output. Shown in Fig- 
ure 7 is the LM4250 micropower Op Amp used with a 74C04 
inverter for increased output capability while maintaining the 
low power advantage of both devices. 



v in O— VW- 




P D = 500 nW 

FIGURE 7. MM74C04 Inverter Used as a Post 
Amplifier for a Battery Operated Op Amp 

The MM74C04 can also be used with single supply amplifier 
such as the LM324. With the circuit shown in Figure 8, the 
open loop gain is approximately 1 60 dB. The LM324 has 4 
amplifiers in a package and the MM74C04 has 6 amplifiers 
per package. 



v ,« O 




TL/F/6020-8 

FIGURE 8. Single Supply Amplifier Using a CMOS 
Cascade Post Amplifier with the LM324 

CMOS inverters can be paralleled for increased power to 
drive higher current loads. Loads of 5.0 mA per inverter can 
be expected under AC conditions. 

Other 74C devices can be used to provide greater comple- 
mentary current outputs. The MM74C00 NAND Gate will 
provide approximately 1 mA from the Vcc supply while the 



258 



MM74C02 will supply approximately 10 mA from the nega- 
tive supply. Shown in Figure 9 is an operational amplifier 
using a CMOS power post amplifier to provide greater than 
40 mA complementary currents. 



Phase Shift Oscillator Using MM74C04 



10 K 
v ih O-VAr- 




'OUT ~ 50 mA 
V UT = 6.0 Vpp 
TL/F/6020-9 

FIGURE 9. MM74C00 and MM74C02 Used as a Post 
Amplifier to Provide Increased Current Drive 

Other Applications 

Shown in Figure 10 is a variety of applications utilizing 
CMOS devices. Shown is a linear phase shift oscillator and 
an integrator which use the CMOS devices in the linear 
mode as well as a few circuit ideas for clocks and one 
shots. 

Conclusion 

Careful study of CMOS characteristics show that CMOS de- 
vices used in a system design can be used for linear build- 
ing blocks as well as digital blocks. 
Utilization of these new devices will decrease package 
count and reduce supply requirements. The circuit designer 
now can do both digital and linear designs with the same 
type of device. 



^^>o-\v^-r><>-^vvv-»--p>< 



00 
00 



<HWrH» 



I 



TL/F/6020-10 



Integrator Using Any Inverting CMOS Gate 
c 

HI- 




TL/F/6020-11 



Square Wave Oscillator 




1.4 RC 
TL/F/6020-12 



One Shot 




T = 1.4 RC 
TL/F/6020-13 



Staircase Generator 




TL/F/6020-14 



FIGURE 10. Variety of Circuit Ideas 
Using CMOS Devices 



259 



Versatile Timer Operates 
from Microseconds to 
Hours 



National Semiconductor 
Application Note 97 




INTRODUCTION 

Timing functions, until recently, have been somewhat ne- 
glected by integrated circuit manufacturers. The primary 
reason was the extremely wide range of input and output 
signals currently incorporated in discrete designs. In addi- 
tion, power supply voltages varied over a ten to one range 
and timing periods were as short as microseconds and as 
long as hours. 

The LM122 timer has been designed to operate over a very 
wide range of input/output signal levels, supply voltages, 
and timing periods. It will replace most discrete designs with 
improved performance and reliability. This new timer over- 
comes many of the problems incurred in discrete or early IC 
designs. 

First, it locks out trigger signals during the timing period to 
guarantee a precise output regardless of trigger level — 
while maintaining the ability to be retriggered almost imme- 
diately following the end of the timing pulse. (Duty cycles up 
to 99.9% can be achieved.) Secondly, the timing period is 
free from jitter caused by supply fluctuations because the 
timing components are driven from an internal regulated 
source. Supply voltage for the timer can vary from 4.5V to 
40V even during the timing period! An additional feature is 
the ±40V excursion allowed on the trigger input and the 
40V/50 mA drive capability of the output transistor. These 
two specifications allow the LM122 to interface directly to 
present designs without level shift or power boosting prob- 
lems. Finally, the LM122 will generate stable timing periods 
from several microseconds to hours — a useful range of 
eight decades. Worst case guarantees on comparator bias 
current and threshold level allow the user to easily select 
timing components for maximum accuracy. 

CIRCUIT DESCRIPTION 

The LM122 circuitry can be divided into five separate sec- 
tions: output stage, bias network, voltage regulator, compar- 
ator, and logic. These sections are grouped on the sche- 
matic in Figure 1 to simplify understanding of the timer. 
The floating transistor output stage of the LM1 22 consists of 
Q32 through Q36. Q36 is the actual output transistor and is 
driven by emitter follower, Q33. Q34 and Q35 are antisatu- 
ration clamps to reduce stored charge in Q36 and to limit 
current through Q33. Q32 acts as a current limiter with the 
limit set at about 1 20 mA. 

The regulator built into the LM1 22 is a Vbe/AVbe* type with 
a typical output voltage of 3.15V at up to 5.0 mA load cur- 
rent. Q18 and Q19 generate a 100 juA current through Q19 
which has a positive temperature coefficient of 0.33%/°C. 
This generates 1.2V and +4 mV/°C TC across R21. When 
added to the base emitter diode voltages of Q20 and Q21 , a 
2.4V, zero TC reference is established at the base of Q21. 
R1 8 and R1 9 form a divider to raise the regulated voltage to 
3.15V. (This particular voltage was chosen because it can 
be operated off a single 5.0V supply and because one RC 
time constant is exactly 2.0V out of 3.1 5V.) Q23 buffers Q21 
from supply fluctuations and sets up the currents for the 
bias section of the timer. Q20 is a single stage of voltage 

•See AN-42, "On Card Regulator for Logic Circuits" 



gain for the regulator. It is buffered by the series pass tran- 
sistor, Q24. Q25, Q26, R25, and R26 are included for start- 
ing purposes and do not affect operation once current is 
flowing in the regulator section. 

The function of the comparator is to cause an output 
change of state when the timing capacitor has charged to 
one RC time constant. Q11 through Q17 perform this func- 
tion. Q14, Q15, Q16, and Q17 are a Darlington differential 
stage driving an active load formed by Q12 and Q13. Q1 1 is 
a second stage operating as a common emitter amplifier 
with R14 as its load resistor. For long timing intervals, the 
Darlington is run with no bleed current from Q30. Operating 
current for Q1 5 and Q1 6 is about 5 juA per side. The spe- 
cially processed lateral PNP's have hpE's of about 200, so 
operating current for Q14 and Q17 is typically 25 nA. At 
these current levels, the substrate PNP's have Ive's of 80, 
giving comparator input currents of 300 pA! One side of the 
comparator is tied to a divider (R16 and R17) which is set at 
63.2% of the reference voltage — one RC time constant. 
The other side is connected to the external timing resistor 
and capacitor. 

The logic section of the LM122 performs four functions: 
first, it provides a latching action to make the circuitry im- 
mune to retriggering during the timing interval; second, it 
simulates the action of an exclusive OR gate to generate a 
logic reverse function; additionally, it translates the low level 
output from the comparator to the high level swing needed 
to drive the floating transistor output; and finally, it drives the 
discharge transistor to reset the timing capacitor. Q2 and 
Q3 makeup the TTL compatible trigger input to the logic 
section. Q3 is a lateral PNP with 60V reverse emitter-base 
breakdown voltage, allowing negative inputs are high as 
-40V without harm to the chip. R5 is an epitaxial resistor 
which pinches off at 30V and has a breakdown of 80V. This 
allows positive input voltages of up to 40V on the trigger 
terminal even when operating the timer from a supply volt- 
age of only 5.0V. Typical current drawn by the trigger termi- 
nal is 40 ju,A at 2.0V and 600 jaA at 40V. Q4 and Q6 form a 
latch which self-limits at about 400 /mA and can be turned off 
by Q2. Q5 and Q7 interface the latch to the comparator so 
that the comparator can fire the latch at the end of the 
timing period. Q8, Q9, and Q10 perform the level shifting 
required to drive the output transistor and double as an ex- 
clusive OR gate, with the emitters of Q8 and Q9 as one 
input and the collectors of Q5 and Q1 1 as the second input. 
Grounding the Q8 and Q9 emitters reverses the effect of a 
signal appearing at the collector of Q1 1 . 
Biasing for the various circuits in the timer is generated by a 
string of PNP current sources consisting of Q27 through 
Q31. Current levels are established by the constant current 
source, Q23, driving diode connected Q28. The current from 
Q23 is 400 jitA, setting the drop across the emitter resistor, 
R28 plus R29, at 200 mV. Q29 delivers 10 juA to the com- 
parator and Q31 supplies a total of 100 juA to the output 
transistor and logic circuitry. Part of Q29's collector is re- 
turned to Q27 to avoid having to use a large value resistor 
for R30. Q30 is completely off when using the timer for long 
timing periods. Shorting the boost terminal of V+ adds 



260 



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about 5 jwA bleed current at the emitters of Q14 and Q17. 
This extra current is needed to slew the emitters of the com- 
parator for timing periods less than 1 ms. 

DESCRIPTION OF PIN FUNCTIONS 

One of the main features of the LM1 22 is its great versatility. 
Since this device is unique, a description of the functions 
and limitations of each pin is in order. This will make it much 
easier to follow the discussion of the various applications 
presented in this note. 

V+ is the positive supply terminal of the LM122. When us- 
ing a single supply, this terminal may be driven by any volt- 
age between 4.5V and 40V. The effect of supply variations 
on timing period is less than 0.005%/V, so supplies with 
high ripple content may be used without causing pulse width 
changes. Supply bypassing on V+ is not generally needed 
but may be necessary when driving highly reactive loads. 
Quiescent current drawn from the V+ terminal is typically 
2.5 mA, independent of the supply voltage. Of course, addi- 
tional current will be drawn if the reference is externally 
loaded. 

The Vref pin is the output of a 3.15V series regulator refer- 
enced to the ground pin. Up to 5.0 mA can be drawn from 
this pin for driving external networks. In most applications 
the timing resistor is tied to Vref. but it need not be in 
situations where a more linear charging current is required. 
The regulated voltage is very useful in applications where 
the LM122 is not used as a timer; such as switching regula- 
tors, variable reference comparators, and temperature con- 
trollers. Typical temperature drift of the reference is less 
than 0.01 %/°C. 

The trigger terminal is used to start timing. Threshold is typi- 
cally 1 .6V at + 25°C and has a temperature dependence of 
-5.0 mV/°C. Current drawn from the trigger source is typi- 
cally 20 jj.A at threshold, rising to 600 ju-A at 30V, then level- 
ing off due to FET action of the series resistor, R5. For 
negative input trigger voltages, the only current drawn is 
leakage in the nA region. 

If the trigger terminal is held high as the timing period ends, 
the output pulse will appear normally, but the timing capaci- 
tor will not be discharged. This is a necessary circuit action 
to prevent repetitive cycles when the trigger is held high. 
After the timing period, the capacitor is discharged when the 
trigger decreases below the threshold, without affecting the 
output. 

The R/C pin is tied to the uncommitted side of the compara- 
tor and to the collector of the capacitor discharge transistor. 
Timing ends when the voltage on this pin reaches 2.0V 
(1 RC time constant referenced to the 3.15V regulator). The 
internal discharge transistor turns on only if the trigger volt- 
age has dropped below threshold. In comparator or regula- 
tor applications of the timer, the trigger is held permanently 
high and the R/C pin acts just like the input to an ordinary 
comparator. The maximum voltages which can be applied to 
this pin are + 5.5V and -0.7V. Input current to the R/C pin 
is typically 300 pA when the voltage is negative with respect 
to the Vadj terminal. For higher voltages, the current drops 
to leakage levels. In the boosted mode, input current is 
30 nA. Gain of the comparator is very high, 200,000 or more 
depending on the state of the logic reverse pin and the con- 
nection of the output transistor. 

The ground pin of the LM122 need not necessarily be tied 
to system ground. It can be connected to any positive or 
negative voltage as long as the supply is negative with re- 
spect to the V+ terminal. Level shifting may be necessary 



for the input trigger if the trigger voltage is referred to sys- 
tem ground. This can be done by capacitive coupling or by 
actual resistive or active level shifting. One point must be 
kept in mind; the emitter output must not be held above the 
ground terminal with a low source impedance. This could 
occur, for instance, if the emitter were grounded when the 
ground pin of the LM122 was tied to a negative supply. 
The terminal labeled Vadj is tie d t0 one side of the compar- 
ator and to a voltage divider between Vref and ground. The 
divider voltage is set at 63.2% of Vref witn respect to 
ground — exactly one RC time constant. The impedance of 
the divider is increased to about 30k with a series resistor to 
present a minimum load on external signals tied to Vadj- 
This resistor is a pinched type with a typical variation in 
absolute value of ±100% and a TC of 0.7%/°C. For this 
reason, external signals (typically a pot between Vref ancl 
ground) connected to Vadj should have a source resistance 
as low as possible. For small changes in Vadj. u P t0 several 
kft is all right, but for large variations 25011 or less should 
be maintained. This can be accomplished with a 1 .0k pot, 
since the maximum impedance from the wiper is 250fl. If a 
voltage is forced on Vadj f rom a hard source, voltage 
should be limited to -0.5, and +5.0V, or current limited to 
±1.0 mA. This includes capacitively coupled signals be- 
cause even small values of capacitors contain enough ener- 
gy to degrade the input stage if the capacitor is driven with a 
large, fast slewing signal. The Vadj Pin may be used to 
abort the timing cycle. Grounding this pin during the timing 
period causes the timer to react just as if the capacitor volt- 
age had reached its normal RC trigger point; the capacitor 
discharges and the output charges state. An exception to 
this occurs if the trigger pin is held high when the Vadj P' n is 
grounded. In this case, the output changes state, but the 
capacitor does not discharge. If the trigger drops with Vadj 
is being held low, discharge will occur immediately and the 
cycle will be over. If the trigger is still high when Vadj ' s 
released, the output may or may not change state, depend- 
ing the voltage across the timing capacitor. For voltages 
below 2.0V across the timing capacitor, the output will 
change state immediately, then once more as the voltage 
rises past 2.0V. For voltages above 2.0V, no change will 
occur in the output. 

In noisy environments or in comparator-type applications, a 
bypass capacitor on the Vadj terminal may be needed to 
eliminate spurious outputs because it is high impedance 
point. The size of the cap will depend on the frequency and 
energy content of the noise. A 0.1 ju,F will generally suffice 
for spike suppression, but several ju,F may be used if the 
timer is subjected to high level 60 Hz EMI. 
The emitter and the collector outputs of the timer can be 
treated just as if they were an ordinary transistor with 40V 
minimum collector-emitter breakdown voltage. Normally, the 
emitter is tied to the ground pin and the signal is taken from 
the collector, or the collector is tied to V+ and the signal is 
taken from the emitter. Variations on these basic connec- 
tions as possible. The collector can be tied to any positive 
voltage up to 40V when the signal is taken from the emitter. 
However, the emitter will not be pulled higher than the sup- 
ply voltage on the V+ pin. Connecting the collector to a 
voltage less than the V+ voltage is allowed. The emitter 
should not be connected to a hard source other than that to 
which the ground pin is tied. The transistor has built-in cur- 
rent limiting with a typical knee current of 1 20 mA. Tempo- 
rary short circuits are allowed; even with collector-emitter 
voltages up to 40V. The power time product, however, must 



262 



not exceed 15 watt«seconds for power levels above the 
maximum rating of the package. A short to 30V, for in- 
stance, can not be held for more than 4 seconds. These 
levels are based on a 40°C maximum initial chip tempera- 
ture. When driving inductive loads, always use a clamp di- 
ode to protect the transistor from inductive kick-back. 
A boost pin is provided on the LM122 to increase the speed 
of the internal comparator. The comparator is normally op- 
erated at low current levels for lowest possible input current. 
For short time intervals where low input current is not need- 
ed, comparator operating current can be increased several 
orders of magnitude for fast operation. Shorting the boost 
terminal to V+ increases the emitter current of the vertical 
PNP drivers in the differential stage from 25 nA to 5.0 juA. 
With the timer in the unboosted state, timing periods are 
accurate down to about 1 ms. In the boosted mode, loss of 
accuracy due to comparator speed is only about 800 ns, so 
timing periods of several microseconds can be used. 
The "Logic" pin is used to reverse the signal appearing at 
the output transistor. An open or "high" condition on the 
logic pin programs the output transistor to be "off" during 
the timing period and "on" all other times. Grounding the 
logic pin reverses the sequence to make the transistor "on" 
during the timing period. Threshold for the logic is typically 
1 50 mV with 1 50 ju.A flowing out of the terminal. If an active 
drive to the logic pin is desired, a saturated transistor drive 
is recommended, either with a discrete transistor or the 
open collector output of integrated logic. A maximum Vsat 
of 75 mV of 200 juA is required. A typical example of active 
drive to the logic pin is the pulse width discriminator shown 
in Figure 16. 

CALCULATING WORST CASE TIMING ERROR 

Timing errors for the LM122 come from the following sourc- 
es: 

1 . Timing ratio error 

2. Capacitor saturation voltage 

3. Internal switching delays 

4. Comparator bias current 

5. External resistor and capacitor tolerance 

6. Capacitor and board leakage 

In general, errors 1 and 5 are the most significant, so they 
will be treated first. 

For most applications, the major contribution to timing error 
from the LM122 itself is variation in timing ratio, which is the 
ratio of the comparator threshold voltage (typically 2.0V) to 
the voltage at the Vref P' n - A 1 % err or in this ratio results in 
a 1.8% initial timing error. Timing ratio error comes from 
variations in the internal divider ratio and from offset 



voltage in the comparator. The LM122 is specified to have a 
timing ratio from 0.626 to 0.638 at + 25°C, giving a ±1.8% 
worst case contribution to initial timing period error. Over 
temperature, the worst case figures doubles to ±3.6%. If 
the initial error is trimmed out externally however, timing er- 
ror drift due to timing ratio will generally be less than ± 0.5% 
over temperature. 

Adding all the contributions to timing error from the LM122 
itself will usually give a figure in the 2% to 3% range at 
+ 25°C. External timing components (Rt and Ct) will nor- 
mally contribute much more error than this unless selected 
components are used. ±5% tolerance on Rt and Ct will 
increase the worst case error to 12% to 13%. By trimming 
out initial component errors, an exact initial timing period 
can be obtained, but temperature drift then becomes the 
limiting factor. For most applications, the contributions to 
timing period drift due to the LM122 itself will be in the 
0.005%/°C to 0.02%/°C range. 

If accurate timing over temperature is required, low drift 
components must be used for Rt and Ct. Capacitors are 
available with temperature coefficients of 100 to 200 
ppm/°C. Resistors, at least in the lower ranges, are avail- 
able with TC's much better than this. Above 1 Mft, however, 
care must be used in the selection of a low TC resistor. 
Units are available up to 100 Mfl with less than 100 ppm/°C 
drift. 

Capacitor saturation voltage is the voltage still remaining on 
the timing capacitor after it has been reset to as near 
ground as the internal discharge transistor can drive it. For 
timing resistors 1 Mfl or greater, this remaining voltage is 
typically 2.5 mV. For smaller timing resistors, the capacitor 
saturation voltage can be calculated by the following: 
formula: 

V c ^2.5mV + (VREF) ; (80a) 
Rt 

*V REF = 3.15V 

The effect of Vq on timing period is linear at 0.03%/mV. 
Temperature dependence of Vq is typically + 0.2%/°C for 
R t < 300 kfl, rising to 0.4%/°C for R t = 10 kfi. This gives a 
typical temperature coefficient of timing error due to Vc of 
(0.002) (2.5 mV) (0.03%/mV) = 0.001 5%/°C for R t > 
1 Mil and (0.004) (24 mV) (0.03%/mV) = 0.003%/°C for 
R t = 10 kfl. Since most applications can use timing resis- 
tors in the range of 100 kft and up, error from capacitor 
saturation voltage rarely exceeds 0.15% initially, with 
±0.05% variation over the full temperature range. 
Internal switching delays cause errors which tend to be a 
fixed time rather than a percentage of the timing period. In 
the boosted mode this delay is typically 800 ns, and with the 
boost off; the delay is about 25 jus. These times can be 



263 



added directly to the calculated timing period for worst case 
analysis. For timing periods longer than 25 ms, the 25 jus 
delay gives an error of 0.1 % or less. In the range of 1 or 25 
ms, error due to delays is 0.1% or less for the boosted 
mode, rising to a maximum of 4.0% in the unboosted mode. 
At r = 1 jus, delay is the major contribution to timing error 
(~ 8%). 

Comparator bias current contributes a negligible timing error 
for all but very long time timing periods. Error can be calcu- 
lated with a simple formula: 

Error (%) = -50 x R t x l b (Note sign) 

lb = Comparator Bias Current 

R t = Timing Resistor 
For R t = 100 Mil and lb = 0.3 nA (typical) a 1.5% reduc- 
tion in timing period is incurred. For worst case calculations 
at +25°C, an l b of 1 nA maximum is specified in the un- 
boosted mode and 100 nA in the boosted mode. At temper- 
atures below +25°C, these numbers still hold. At +125°C, 
lb increases due to leakage to a maximum of ±5 nA un- 
boosted. For worst case calculations below +125°C, the 
leakage error (5 nA) can be assumed to halve for each 10°C 
drop below +125°C. At +95°C for instance, the leakage 
component of lb would be (5 nA/8) ~ 0.6 nA for a total lb of 
1 .6 nA worst case. For the commercial LM322 and LM3905, 
worst case l b is 2 nA at + 75°C, and for the LM2905 lb is 
2 nA maximum at +85°C. For temperatures between 
-25°C and +85°C, the TC of lb is typically 5 pA/°C in the 
unboosted mode and 100 pA/°C in the boosted mode. For 
a 100 Mil R t , this 5 pA/°C contributes -0.025%/°C to tim- 
ing period drift. 

Error (%/°C) = (-50) (Al b /AT)(Rt) 
For worst case calculations a Alb/AT (-25 <■ Ta £ 
+ 85°C) of 12 pA/°C may be used for the LM122/LM222 
and 20 pA/°C for the LM322 and LM2905/LM3905. 
External leakage paths may cause timing errors for large 
values of R t and high board temperatures. Connections 
made to the R/C pin should be kept free of dust, moisture, 
and soldering flux if long time intervals are to be kept accu- 
rate. All package types have the R/C pin located between 
Vref ap d the ground pin to minimize these leakages. 

DESIGN HINTS 

ELIMINATING TIMING CYLCE UPON INITIAL 
APPLICATION OF POWER 

The LM122 will start a timing cycle automatically (with no 
trigger input) when V+ is first turned on. If this characteristic 
is undesirable, it can be defeated by tying the timing capaci- 
tor to Vref instead of ground as shown in Figure 2. This 
connection does not affect operation of the timer in any 
other way. If an electrolytic timing capacitor is used, be sure 
the negative end is tied to the R/C pin and the positive end 
to Vref. A 1 .0 kfl resistor should be included in series with 
the timing capacitor to limit the surge current load on Vref 
when the capacitor is discharged. 



v + 



TRIGGER 
INPUT 




TRIGGER 
LOGIC 



BOOST 



COLLECTOR 



R/C EMITTER 

Vadj GND 



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T* 



TL/H/7408-2 

FIGURE 2. Eliminating Initial Timing Cycle 

USING ELECTROLYTIC TIMING CAPACITORS 

Electrolytic capacitors are not usually recommended for tim- 
ing because of their unstable capacitance and high leakage. 
For long timing periods (> 10 seconds) at moderate tem- 
peratures (0°C to 50°C) however, an electrolytic may be at- 
tractive because of its low cost per microfarad. Solid tanta- 
lum capacitors such as the Kemet* C series T310 (molded 
epoxy) or T1 1 (hermetic) are recommended. These units 
have long term stabilities of 2% to 3% and a temperature 
coefficient of +0.2%/°C. Selected units are available for 
timing use with very low leakage. 

RESET TIME 

The timing capacitor used with the L.M122 is reset with an 
internal transistor which has a collector offset voltage of 2.5 
mV @ 1 jxA with approximately 80ft of collector resistance. 
The time required to reset this capacitor determines the 
minimum time between timing pulses. An approximate for- 
mula for reset time is: 

Reset Time = (80ft) (Ctf) (5) 

tCt = External timing capacitor. 

NOISY ENVIRONMENTS 

The LM122 is relatively insensitive to noise on supply lines 
and to radiated energy. In extremely noisy environments 
however, it may be necessary to configure the LM1 22 differ- 
ently, both to eliminate false triggering and to prevent pre- 
mature end of a timing period. The circuit "a" shown in Fig- 
ure 3 has been set up for maximum noise rejection. C1 by- 
passes the Vadj Pi n because of the relatively high imped- 
ance ( a 30 kft) of this point. Negative spikes on the Vadj 
pin will cause premature end of the timing period. C2 by- 
passes the supply for rejection of fast transients. R1 sets up 
the trigger pin to a "normally high" condition. This prevents 
extremely high electromagnetic fields from triggering the in- 
ternal flip-flop during a timing period. The input trigger signal 
is capacitively coupled through C3. Triggering occurs on the 
negative edge of the trigger pulse as shown in the waveform 
sketch next to Figure 21. 



'Manufactured by Union Carbide 



264 



If the output voltage from the LM122 can be set up to go 
"high" during the timing cycle, the alternate connection 
shown in "b" can be used. Here, the trigger is held high by 
D2 during the timing period. When the output goes low after 
the timing period is over, the circuit may be retriggered im- 
mediately via D1. R1 and C3 suppress unwanted spikes at 
the trigger input. 




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FIGURE 3. Maximum Noise Immunity 

ABORTING A TIMING CYCLE (Figure 4) 
The LM122 does not have an input specifically allocated to 
a stop-timing function. If such a function is desired, it may be 
accomplished several ways: 

■ Ground Vadj 

■ Raise R/C more positive than Vadj 

■ Wire "OR" the output 

Grounding Vadj wi" er, d tne timing cycle just as if the timing 
capacitor had reached its normal discharge point. A new 
timing cycle can be started by the trigger terminal as soon 
as the ground is released. A switching transistor is best for 
driving Vadj to as near ground as possible. Worst case sink 
current is about 300 juA. 

A timing cycle may be also ended by a positive pulse to a 
resistor (R <. Rt/100) in series with the timing capacitor. 



The pulse amplitude must be at least equal to Vadj (2.0V), 
but should not exceed 5.0V. When the timing capacitor dis- 
charges, a negative spike of up to 2.0V will occur across the 
resistor, so some caution must be used if the drive pulse is 
used for other circuitry. 




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LOGIC V* 



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TRANSISTOR 
OR LOGIC 
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TL/H/7408-5 

FIGURE 4. Cycle Interrupt 

The output of the timer can be wire ORed with a discrete 
transistor or an open collector logic gate output. This allows 
overriding of the timer output, but does not cause the timer 
to be reset until its normal cycle time has elapsed. 

USING THE LM122 AS A COMPARATOR 

A built-in reference and zero volt common mode limit make 
the LM122 very useful as a comparator. Threshold may be 
adjusted from zero to three volts by driving the Vadj termi- 
nal with a divider tied to Vref- Stability of the refrence volt- 
age is typically + 1 % over a temperature range of -55°C to 
+ 125°C. Offset voltage drift in the comparator is typically 
25 /u.V/°C in the boosted mode and 50 liV/°C unboosted. A 
resistor can be inserted in series with the input to allow 
overdrives up to ± 50V as shown in Figure 5. There is actu- 
ally no limit on input voltage as long as current is limited to 



N0N INVERTING 



R/C EMITTER 



u-i — r 

1 *S 'THRESHOLD 
1 ADJUST 

i i i n 



TL/H/7408-6 
•Timer Protected Against Damage for Up to ± 50V 

FIGURE 5. Comparator with Volts to 
3.0 Volts Threshold 

+ 1 mA. The resistor shown contributes a worst case of 5 
mV to initial offset. In the unboosted mode, the error drops 
to 0.25 mV maximum. The capability of operating off a sin- 
gle 5V supply should make this comparator very useful. 



265 



USING DUAL SUPPLIES 

The LM122 can be operated off dual supplies as shown in 
Figure 6. The only limitation is that the emitter terminal can- 
not be tied to ground, it must either drive a load referred to 
V~ or be actually tied to V - as shown. Although capacitive 
coupling is shown for the trigger input (to allow 5V trigger- 
ing), a resistor can be substituted for C1. R2 must be cho- 
sen to give proper level shifting between the trigger signal 
and the trigger pin of the timer. Worst case "lo" on the 
trigger pin (with respect to V - ) is 0.8V, and worst case 
"high" is 2.5V. R2 may be calculated from the divider equa- 
tion with R1 to give these levels. 



Mr 




TRIGGER BOOST 
LOGIC V* 



Vref COLLECTOR 



•Select For Proper Level Shift TL/H/7408-7 

Emitter Terminal Or Emitter Load Must Be Tied To GND Pin Of Timer. 

FIGURE 6. Operating Off Dual Supplies 
LINEARIZING THE CHARGING SWEEP 

In some applications (such as a linear pulse width modula- 
tor) it may be desirable to have the timing capacitor charge 
from a constant current source. A simple way to accomplish 
this is shown in the accompanying sketch. 



$R2 

S4.7k 



TL/H/7408-8 

Q1 converts the current through R1 to a current source in- 
dependent of the voltage across C t . R2, R3, D1 , and D2 are 
added to make the current through R1 independent of sup- 
ply variations and temperature changes. (D2 is a low TC 
type) D2 and R3 can be omitted if the V+ supply is stable 
and D1 and R2 can be omitted also if temperature stability if 
not critical. With D1 and R2 omitted, the current through R1 
will change about 0.015%/°C with a 15V supply and 
0.1 %/°C with a 5.0V supply. 



APPLICATIONS 

BASIC TIMERS 

Figure 7 Is a basic timer using the collector output. Rt and Ct 
set the time interval with R[_ as the load. During the timing 
interval the output may be either high or low depending on 
the connection of the logic pin. Timing waveforms are 
shown in the sketch alongside Figure 7. 




Lt 



_J 



OUTPUT 
LOGIC TIED TO V R6F 



L 



L (R,| (C) »J 

n OUTPUT I 

LOGIC TIEO TO GNO I 



_J 



1 

I 

L 



TL/H/7408-9 

FIGURE 7. Basic Timer-Collector Output 
and Timing Chart 

Figure 8 is again a basic timer, but with the output taken 
from the emitter of the output transistor. As with the collec- 
tor output, either a high or low condition may be obtained 
during the timing period. 




r 



_r 



L 



_j 



TL/H/7408-10 

FIGURE 8. Basic Timer-Emitter Output and Timing Chart 

Figure 9 shows the timer interfacing 5V logic to a high volt- 
age relay. Although the V+ terminal could be tied to the 
+ 28V supply, this would be an unnecessary waste of power 
in the IC. In any case, the threshold for the trigger is 1.6V 
regardless of where V+ is tied. 



fl 




X. 



TL/H/7408-11 

FIGURE 9. 5 Volt Logic Supply Driving 28 Volt Relay 



266 



Figure 10 indicates the ability of the timer to interface to 
digital logic when operating off a high supply voltage. Vout 
swings between + 5V and ground with a minimum fanout of 
5 for medium speed TTL 



some time. The relay remains de-energized for R t Ct sec- 
onds after Vcc is applied, then closes and stays energized 
until Vcc is turned off. Figure 12 is a similar circuit except 
that the relay is energized as soon as Vcc is applied. Rt Ct 
seconds later, the relay is de-energized and stays off until 
the Vcc supply is recycled. 



II 



TRIGGER BOOST 
LOGIC V' 



a 



x. 



£. 



TL/H/7408-12 

FIGURE 10. 30 Volt Supply Interfacing to 5 Volt Logic 

Figure 11 is an application where the LM122 is used to sim- 
ulate a thermal delay relay which prevents power from being 
applied to other circuitry until the supply has been on for 

-N-W- 



I 

"T_ 



U 



X. 



TL/H/7408-13 

FIGURE 11. Time Out on Power Up (Relay Energized 
RtCt Seconds After Vcc is Applied) 



TL/H/7408-14 

FIGURE 12. Time Out on Power Up (Relay Energized 
Until R t Ct Seconds After Vcc is Applied) 

Figure 13 is a more advanced application of the LM1 22 as a 
proportioning temperature controller with optical isolation 
and synchronized zero crossing features. The timing func- 
tion is not used. Instead the trigger terminal is held high and 
the LM122 is used as a high gain comparator with a built in 
reference. R1 is a thermistor with a -4%/°C temperature 
coefficient used as the sensor. R2 is used to set the temper- 
ature to be controlled by R1. R3 through R8 set up the 
proportioning action. R3 raises the impedance of the R1 /R2 
divider so that R5 sees a relatively constant impedance in- 
dependent of the set point temperature. R6 and R8 reduce 
the Vadj impedance so that internal variations in divider 
impedance do not affect proportioning action. R5 and R7 




R1— Thermistor (-4%/°C) 

Q1 — Optical coupler, minimum gain = 1 / 2 at 1.0 mA 

(D1-D3)— 1N459 

Q2 — Sensitive gate SCR, 1.0 mA or less 



TL/H/7408-15 



FIGURE 13. Proportioning Temperature Controller with Synchronized Zero-Crossing 



267 



set the actual width of the proportioning band and can be 
scaled as necessary to alter the width of the band. Larger 
resistors make the band narrower. The values shown give 
approximately a 1°C band. R4 and C1 determine the propor- 
tioning frequency which is about 1 Hz with the values 
shown. C1 or R4 can change to alter frequency, but R4 
should be between 50k and 500k, and C1 must be a low 
leakage type to prevent temperature shifts. D1 prevents 
supply voltage fluctuations from affecting set point or pro- 
portioning band. Any unregulated supply between 6V and 
1 5V is satisfactory. 

Q1 is an optical isolator with a minimum gain of 0.5. With the 
values shown for R9, R10, and R1 1, Q1 is over-driven by at 
least 3 to 1 to insure deep saturation for reliable turn off of 
the SCR. Q2 must be a sensitive gate device with a worst 
case gate firing current of 0.5 mA. R12, R13, and D2 imple- 
ment the synchronized zero-crossing feature by preventing 
Q1 from turning off after the voltage across Q2 has climbed 
above 2.5V. D3, R10, and C2 provide a source of semifil- 
tered dc current must have a minimum breakdown of 200V. 
Figure 14 shows the LM122 connected as a one hour timer 
with manual controls for start, reset, and cycle end. S1 
starts timing, but has no effect after timing has started. S2 is 
a center off switch which can either end the cycle prema- 



C10SET0 

START I— | S1 
TIMING 



H! 




TRIGGER BOOST 
LOGIC V* 



V HEF COLLECTOR 



4 



x 



c,* 

47nF 



TL/H/7408-16 
•Dearborn Electronics LP9A1A476K Polycarbonate 

FIGURE 14. One Hour Timer with Reset 
and Manual Cycle End 

turely with the appropriate change in output state and dis- 
charging of C t , or cause C t to be reset to 0V without a 
change in output. In the latter case, a new timing period 
starts as soon as S2 is released. The average charging cur- 
rent through R t is about 30 nA, so some attention must be 
paid to parts layout to prevent stray leakage paths. The sug- 
gested timing capacitor has a typical self time constant of 
300 hours and a guaranteed minimum of 25 hours at 
+ 25°C. Other capacitor types may be used if sufficient data 
is available on their leakage characteristics. 
Figure 15 is another application where the LM122 does not 
use its timing function. A switching regulator is made using 
the internal reference and comparator to drive a PNP switch 
transistor. Features of this circuit include a 5.5V minimum 
input voltage at 1 A output current, low part count, and good 
efficiency (> 75%) for input voltages to 10V. Line and load 
regulation are less than 0.5% and output ripple at the 
switching frequency is only 30 mV. Q1 is an inexpensive 
plastic device which does not need a heatsink for ambient 
temperature up to 50°C. D1 should be a fast switching di- 
ode. Output voltage can be adjusted between 1 V and 30V 
by choosing proper values for R2, R3, R4, and R5. For out- 
puts less than 2V, a divider with 250H the Thevinin resist- 



TRIGGER BOOST 
LOGIC V' 



EMITTER 
GN0 



xil 




TL/H/7408-17 

•No. 22 Wire Wound On Molybdenum Permalloy Core 

FIGURE 15. 5 Volt Switching Regulator with 1.0 Amp 
Output and 5.5 Volt Minimum Input 

ance must be connected between Vref and ground with its 
tap point tied to Vadj- 

By driving the logic terminal of the LM122 simultaneous to 
the trigger input, a simple, accurate pulse width detector can 
be made (Figure 16). 

TTL 

LOGIC 

LEVEL " 

PULSE 

INPUT 



TRIGGER BOOST 
LOGIC V* 



V„ EF COLLECTOR 




+ 



1 



TL/H/7408-18 



•Vout = For W < R t Ct 
Pulse Out = W - R, Ct For W > R, C t 

FIGURE 16. Pulse Width Detector 

In this application the logic terminal is normally held high by 
R3. When a trigger pulse is received, Q1 is turned on, driv- 
ing the logic terminal to ground. The result of triggering the 
timer and reversing the logic at the same time is that the 
output does not change from its initial low condition. The 
only time the output will change states is when the trigger 
input stays high longer than one time period set by Rt and 
Ct. The output pulse width is equal to the input trigger width 
minus Rt • Ct. C2 insures no output pulse for short (< RC) 
trigger pulses by prematurely resetting the timing capacitor 
when the trigger pulse drops. C|_ filters the narrow spikes 
which would occur at the output due to interval delays dur- 
ing switching. 

The LM122 can be used as a two terminal time delay switch 
if an "on" voltage drop of 2V to 3V can be tolerated. In 



268 



I* 



TRIGGER BOOST 
LOGIC v* 



V REF COLLECTOR 



R/C EMITTER 

Vaoj GND 



=F* I 



• 3.0 mA ■OFF" 



T^ — 

TL/H/7408-19 

FIGURE 17. Two-Terminal Time Delay Switch 

Figure 17, the timer is used to drive a relay "on" Rt Ct sec- 
onds after application of power "off" current of the switch is 
4 mA maximum, and "on" current can be as high as 50 mA. 
An accurate frequency to voltage converter can be made 
with the LM122 by averaging output pulses with a simple 
one pole filter as shown in Figure 18. Pulse width is adjusted 
with R2 to provide initial calibration at 10 kHz. The collector 
of the output transistor is tied to Vref. giving constant am- 
plitude pulses equal to Vref at the emitter output. R4 and 
C1 filter the pulses to give a dc output equal to, (Rt) (Ct) 
(Vref) (f)- Linearity is about 0.2% for a 0V to 1V output. If 
better linearity is desired R5 can be tied to the summing 
node of an op amp which has the filter in the feedback path. 
If a low output impedance is desired, a unity gain buffer 
such as the LM110 can be tied to the output. An analog 
meter can be driven directly by placing it in series with R5 to 
ground. A series RC network across the meter to provide 
damping will improve response at very low frequencies. 




TL/H/7408-20 

FIGURE 18. Frequency to Voltage Converter 
(Tachometer) Output Independent of Supply Voltage 

In some applications it is desirable to reduce supply drain to 
zero between timing cycles. In Figure 19 this is accom- 
plished by using an external PNP as a latch to drive the V+ 
pin of the timer. 

Between timing periods Q1 is off and no supply current is 
drawn. When a trigger pulse of 5V minimum amplitude is 




to 

-J 



TL/H/7408-21 

FIGURE 19. Zero Power Dissipation 
Between Timing Intervals 

received, the LM122 output transistor and Q1 latch for the 
duration of the timing period. D1 prevents coupling back into 
the trigger signal from the dc load created by the trigger 
input. If the trigger input is a short pulse, C1 and R2 may be 
eliminated. R|_ must have a minimum value of 
(V cc )/(2.5 mA). 

The LM122 can be made into a self-starting oscillator by 
feeding the output back to the trigger input through a capac- 



"X" 




TRIGGER BOOST 
LOGIC V* 



B/C EMITTER 

V«oj GND 




T* * 



TL/H/7408-22 



9.001 0.11 0.1 1J) 10 IM 

Ci(MF) 

TL/H/7408-23 

FIGURE 20. Oscillator 

itor as shown in Figure 20. Operating frequency is 1 /(Rt Ct). 
The output is a narrow negative pulse whose width is ap- 
proximately 2Rg Cf. For optimum frequency stability, Cf 
should be as small as possible. The minimum value is deter- 
mined by the time required to discharge Ct through the inter- 
nal discharge transistor. A conservative value for Cf can be 



269 






chosen from the graph included with Figure 20. For frequen- 
cies below 1 kHz, the frequency error introduced by Cf is a 
few tenths of one percent or less for R t > 500k. 
Although the LM1 22 is triggered by a positive going trigger 
signal, a differentiator tied to a normally "high" trigger will 
result in negative edge triggering. In Figure 21, R1 serves 



Hr 



J 



~L 



VOLTAGE ON TRIG PIN 



X 



tt 



EMITTER 
GND 



TL/H/7408-24 



FIGURE 21. Timer Triggered by 
Negative Edge of Input Pulse 



the dual purpose of holding the trigger pin normally high and 
differentiating the input trigger pulse coupled through C1. 
The timing diagram included with Figure 21 shows that trig- 
gering actually occurs a short time after the negative going 
trigger, while positive going triggers have no effect. The de- 
lay time between a negative trigger signal and actual starts 
of timing is approximately 0.5 to 1.5 R1 C1 depending on 
the trigger amplitude, or about 2.5 to 7.5 jus with the values 
shown. This time will have to be increased for Ct larger than 
0.01 ju,F because Q is charged to Vref whenever the trig- 
ger pin is kept high and must reset itself during the short 
time that the trigger pin voltage is low. A conservative value 
forCl is: 



C1 :> 



<2 
10 



The LM122 can be connected as a chain of timers quite 
easily with no interface required. In Figure 22A and 22B, two 
possible connections are shown. In both cases, the output 
of the timer is low during the timing period so that the posi- 
tive going signal at the end of timing period can trigger the 
next timer. There is no limitation on the timing period of one 
timer with respect to any other timer before or after it, be- 
cause the trigger input to any timer can be high or low when 
that timer ends its timing period. 



fl 



TRIGGER BOOST 
LOGIC v* 



m 



x 



■M 



X 







— r J 

i 
— 4— 



(A) 



TL/H/7408-25 



t 

• R/C 

X L^ 



TRIGGER BOOST 
LOGIC V* 



R/C EMITTER 

GND 



x. 




I-T-' 



[J OUTPUT 3 |_J 

" j | OUTPUT 2 | | 



I I OUTPUT 1 

[~| TRIGGER INPUT |~j 



TL/H/7408-26 



(B) 
FIGURE 22. Chain of Timers 



270 



Typical Performance Characteristics 



Comparator Bias Current 













T A - -56°C 










r 








^7 




^ 
















s— 




5 0.2 




T A -25°C 






\ 


1 




s 
















\ 




K D 












T A -100°C 

1 






« 


















^ 

















































0.5 1.0 15 2.0 2.5 
COMPARATOR INPUT VOLTAGE (V) 



Supply Current 







T A » -55° C 












/ 




T, 


-25'C 




f 


— — 




Ta-1 


2S°C 










I 










/ 










/ 











1.0 16 24 32 40 

V* (V) 



Collector Output Saturation 
Characteristics at High Current 

















1 1 1 














A 


T A - -SS°C 


5 120 

e 












) 


' 




T A - 25°C 


K 








j 


', 


/ 














/ 


/ 


/ 




T A 


-12 


S"C 








/ 


', 


y 














A 


V 


















A 


f 



















0.S 1.0 1.S 2.0 2.S 

SATURATION VOLTAGE (V) 



Reference Regulation 

























r 












1 






























A »125 


c 












T A -2rc / f*s^ 


^s^. 






T A .-5rc" 


s^ * 






1 





2.0 4.0 6.0 1.0 

OUTPUT CURRENT (mA| 



Comparator Bias Current 



-0.1 
-1.6 



































































TRIGGER "LO 












If 


125"C. 


to 


TRIGGER "HI" 
T A = 125"C| — 

_J 1 


k " 




•^ 






































" 





0.5 1.0 1.5 2.0 2.5 
COMPARATOR INPUT VOLTAGE (VI 



Trigger Input Characteristics 









1 

T A = -55° C 
















T A ■ 25°C 








T A "125C 























.0 16 24 32 

TRIGGER VOLTAGE (V) 



Timing Error Due to 
Comparator Bias Current 



iJlJ^L TMM mi „ ,#• tmm warm mmmti 

>1 71" / !/ 




1 / 


1 / 1 




am; 


1 jjr 


1 / ' 
/ /i 


~f ^ 








1- 




// 


I II 1 



1.0M 10M 100N 

TIMING RESISTOR (ill 



Suggested Timing Components 



100* 
1.0M 



100M 

LOG 



71 


55?- 1- 






— -1 


— 1 








j^i 












>^c 























































































0.1 5 

o 

0.01 3 
0.001 ~ 
0.0001 



1.0/j 100m iom 

TIME fuel 



1.0 100 10k 



Comparator Bias Current 



1 
T A - -55°C 








£ 






T A - 


2S°C 
















BOOST TIED TO V* 































0.05 1.0 1.5 2.0 2.5 
COMPARATOR INPUT VOLTAGE (VI 



Trigger Threshold 





















_ 






^WORST CASE " 


" 




















K 








^J TYPICAL^ 




> 1S 












1 






s 
























WORST CASE ' 


1" 



























-55 -15 25 65 105 

TEMPERATURE ( C) 



Reference Regulation 





































T A *2S C 
-56 tj£ 




























T A 













































8.0 16 24 32 40 

V*(V) 



Short Output Pulse 





6.0 
4.0 
2.0 

4.0 
2.0 



LOGIC PIN TIED TO I 1 






J- 












— 


-fl 


f T 


1 
= 125°C 
= 25C 


tW 


< 




FT' 


-+-* 




-J 


K 


f 


■T, 


1 _ r 


1 


». 


> 


£ 


L 






















































_V+ - 5.0V 
R,= 10k 
















1 






C 


OLL 


ECT 


OR 


OUTPUT R L 


soon 





to 



1.0 2.0 3.0 4.0 5.0 



TL/H/7408-27 



271 



LM340 Series Three 
Terminal Positive 
Regulators 



INTRODUCTION 

The LM340-XX are three terminal 1 .OA positive voltage reg- 
ulators, with preset output voltages of 5.0V or 15V. The 
LM340 regulators are complete 3-terminal regulators requir- 
ing no external components for normal operation. However, 
by adding a few parts, one may improve the transient re- 
sponse, provide for a variable output voltage, or increase 
the output current. Included on the chip are all of the func- 
tional blocks required of a high stability voltage regulator; 
these appear in Figure 1. 



PASS 
TRANSISTOR 



-QVout 



THERMAL SHUTDOWN 

AND CURRENT 

LIMIT CIRCUITRY 




6 

COMMON 

TL/H/7413-1 

FIGURE 1. Functional Block of the LM340 

The error amplifier is internally compensated; the voltage 
reference is especially designed for low noise and high pre- 
dictability; and, as the pass element is included, the regula- 
tor contains fixed current limiting and thermal protection. 
The LM340 is available in either metal can TO-3 or plastic 
TO-220 package. 

1. CIRCUIT DESIGN 

Voltage Reference 

Usually IC voltage regulators use temperature-compensat- 
ed zeners as references. Such zeners exhibit BV > 6.0V 
which sets the minimum supply voltage somewhat above 
6.0V. Additionally they tend to be noisy, thus a large bypass 
capacitor is required. 



National Semiconductor 
Application Note 1 03 
George Cleveland 





TL/H/7413-2 

FIGURE 2. Simplified Volt Reference 

Figure 2 illustrates a simplified reference using the predict- 
able temperature, voltage, and current relationship of emit- 
ter-base junctions. 

Assuming Jqi > J Q2 , lcQ2 > 'BQ2 = 'BQ3 . 
Area (emitter Q1) = Area (emitter Q2), and 

V BEQ1 = VbeQ3. 
then 

/kT R2\R2 w 
V REF = ( — In— ) — + V BEQ3 



(1-1) 



R3 



d-2) 



Simplified LM340 

In Figure 3 the voltage reference includes R1 -R3 and Q1 - 
Q5. Q3 also acts as an error amplifier and Q6 as a buffer 
between Q3 and the current source. If the output drops, this 
drop is fed back, through R4, R5, Q4, Q5, to the base of Q3. 
Q7 then conducts more current re-establishing the output 
given by: 

v -w R4 + R5 
v OUT - vref ^ 



272 



■( (— O V OUT 




Tl/H/7413-3 



Complete Circuit of the LM340 (Figure 4) 

Here (J Q2 , Jq3) > (Jq4. Jqs) and a positive TC AV B e ap- 
pears across R6. This is amplified by 17, (R6/R6 = 17) and 
is temperature compensated by the Vbe of Q6, Q7, Q8 to 
develop the reference voltage. R17 is changed to get the 
various fixed output voltages. 

Short Circuit Protection 

A) Vin-Vout < 6.0V: There is no current through D2 and 
the maximum output current will be given by: 

Vbeqh 



'out max 



R16 



= 2.2A (Tj = 25°C) 



(1-4) 



B) V|n-Vout > 60V: To kee P Q16 0P era *ing within its 
maximum power rating the output current limit must de- 
crease as Vin-Vout increases. Here D2 conducts and 
the drop across R16 is less than V BE to turn on Q14. In 
this case Iout maximum is: 

'OUT MAX = J ^j (^BEQ14 ~ 

[(V|N ~ Vqut) - V ZD 2 - VbEQuI 



0.077 [37.2 - 
at T; = 25°C 



R13 

(Vin - Vqut)] (A) 



R14 



d-5) 



FIGURE 3. LM340 Simplified 



I J l 

— r~v 




•Series pass element 
t Starting up resistor 



Tl/H/7413-4 



FIGURE 4. Complete Circuit of the LM340 



273 



CO 

o 



Thermal Shut Down 

In Figure 4 the Vbe of Q1 3 is clamped to 0.4V. When the die 
temperature reaches approximately + 1 75°C the Vbe to turn 
on Q13 is 0.4V. When Q13 turns on it removes all base 
drive from Q1 5 which turns off the regulator thus preventing 
a further increase in die temperature. 

Power Dissipation 

The maximum power dissipation of the LM340 is given by: 

PD MAX = (V|N MAX - V Ut) 'OUT MAX + V in MAX Iq (W) 

d-6) 
The maximum junction temperature (assuming that there is 
no thermal protection) is given by: 

36-13 l OUT MAX - (V [N - V OUT ) 



'jM 



+ 25°C (1-7) 



0.0855 
Example: 

Vin MAX = 23V, louTMAX = 10A, LM340T-15. 
Equation (1-7) yields: T jM = 200°C. So the Tj max of 150°C 
specified in the data sheet should be the limiting tempera- 
ture. 

From (1-6) Pq - 8.1W. The thermal resistance of the heat 
sink can be estimated from: 



Oa.a — 



T )MAX - T A 
P D 



(0j-c + c . s )(°C/W) 



(1-8) 



The thermal resistance 0j. c (junction to case) of the TO-220 
package is 6°C/W, and assuming a 0c. s (case to heat sink) 
of 0.4, equation (1-8) yields: 

s . a = 8.4°C/W 
2. CURRENT SOURCE 

The circuit shown on Figure 5 provides a constant output 
current (equal to V ut/R1 or 200 mA) for a variable 



V, N »28V 



Vreo 



25 
2.DW 



, CI* 
■ 0.22juF 



Zload 



VOOT 



o-±- 



0^Zi.^85n 

TL/H/7413-5 

•Required if regulator is located far from power supply filter 
FIGURE 5. Current Source 



load impedance of to 85JX Using the following definitions 
and the notation shown on Figure 5, Zout an d tout a re: 
Qcc/V = Quiescent current change per volt of input/out- 
put (pin 1 to pin 2) voltage change of the LM340 
L r /V = Line regulation per volt: the change in the LM340 

output voltage per volt of input/output voltage 

change at a given Iqut- 



AIOUT = (Qcc/V) AVquT + -—■ AVquT 



Zout 



Zqut 



avqut 
AIqut 



AVquT 



(Q CC /V)AVouT + %7^AVout 



R1 



Zout = 



(Qcc/V) + 



(L r /V) 
R1 



(2-1) 



(2-2) 



(2-3) 



(2-4) 



The LM340-5.0 data sheet lists maximum quiescent current 
change of 1 .0 mA for a 7.0V to 25V change in input voltage; 
and a line regulation (interpolated for Iqut = 200 mA) of 
35 mV maximum for a 7.0V to 25V change in input voltage: 

Q CC/V = - : 7 £- = 55 jaA/V (2-5) 



L r /V = 



15V 
35 mV 



18V 



s* 2 mV/V 



(2-6) 



The worst case change in the 200 mA output current for a 
1 .0V change in output or input voltage using equation 2-1 is: 



AIqut 
1.0V 



55juA + 



2mV 
250 



135 /xA 



(2-7) 



and the output impedance for a to 8511 change in Z[_ using 
equation 2-4 is: 

Zout = r~ - = 7.4 kil (2-8) 



55 fxA + 



2mV 
25fl 



Typical measured values of Zout varied from 10-12.3 kfl, 
or 81-100 jxA/V change input or output (approximately 
0.05%/V). 

3. HIGH CURRENT REGULATOR WITH SHORT CIRCUIT 
CURRENT LIMIT 

The 1 5V regulator circuit of Figure 6 includes an external 
boost transistor to increase output current capability to 
5.0A. Unlike the normal boosting methods, it maintains the 
LM340's ability to provide short circuit current limiting and 
thermal shut-down without use of additional active compo- 
nents. The extension of these safety features to the exter- 
nal pass transistor Q1 is based on a current sharing scheme 



274 



R1 

0.25 

'_». 16W 

VN/Sr 



Q1 
2N4398 



1 — vy 



10 



T I _^4.0W 1N ™9 

- VA H~ 



V| N = 19.5V TO 25V 



CI* 

■ I.O^F 



V 0UT = 15V 
1 AT 5 AMP 



C2* 
lOpF 



SINGLE 
POINT GNO 



•Solid tantalum 

Note 1: Current sharing between the LM340 and Q1 allows the extension of short 

circuit current limit, safe operating area protection, and (assuming QVs heat sink 

has four or more times the capacity of the LM340 head sink) thermal shutdown 

protection. 

Note 2: Ishort circuit is approximately 5.5 amp. 

Note 3: lour max at V ut = 15V is approximately 9.5 amp. 

FIGURE 6. 15V 5.0A Regulator with Short Circuit Current Limit 



using R1 , R2, and D1 . Assuming the base-to-emitter voltage 
of Q1 and the voltage drop across D1 are equal, the voltage 
drops across R1 and R2 are equal. The currents through R1 
and R2 will then be inversely proportional to their resistanc- 
es. For the example shown on Figure 6, resistor R1 will 
have four times the current flow of R2. For reasonable val- 
ues of Q1 beta, the current through R1 is approximately 
equal to the collector current of Q1 ; and the current through 
R2 is equal to the current flowing through the LM340. 
Therefore, under overload or short circuit conditions the 
protection circuitry of the LM340 will limit its own output 
current and, because of the R1 /R2 current sharing scheme, 
the output current of Q1 as well. Thermal overload protec- 
tion also extends Q1 when its heat sink has four or more 
times the capacity of the LM340 heat sink. This follows from 
the fact that both devices have approximately the same in- 
put/output voltage and share the load current in a ratio of 
four to one. 

The circuit shown on Figure 6 normally operates at up to 
5.0A of output current. This means up to 1.0A of current 
flows through the LM340 and up to 4.0A flows through Q1 . 
For short term overload conditions the curve of Figure 7 
shows the maximum instantaneous output current versus 
temperature for the boosted regulator. This curve reflects 
the approximately 2.0A current limit of the LM340 causing 
an 8.0A current limit in the pass transistor, or 10A, total. 

1 



lb 














































































































































5.0 





























































































SO 10 20 30 40 50 60 70 

JUNCTION TEMPERATURE (°C) 

FIGURE 7. Maximum Instantaneous 
Current vs Junction Temperature 



Under continuous short circuit conditions the L.M340 will 
heat up and limit to a steady total state short circuit current 
of 4.0A to 6.0A as shown in Figure 8. This curve was taken 
using a Wakefield 680-75 heat sink (approximately 
7.5°C/W) at a 25°C ambient temperature. 

10 















LM340K-15 HEAT SINK. 






WAKEFIEL[ 


NO. 6 


50-75 























































































TL/H/7413-7 



19 20 21 22 23 24 25 
INPUT VOLTAGE (V) 

TL/H/7413-8 

FIGURE 8. Continuous Short Circuit 
Current vs Input Voltage 

For optimum current sharing over temperature between the 
LM340 and Q1, the diode D1 should be physically located 
close to the pass transistor on the heat sink in such a man- 
ner as to keep it at the same temperature as that of Q1 . If 
the LM340 and Q1 are mounted on the same heat sink the 
LM340 should be electrically isolated from the heat sink 
since its case (pin 3) is at ground potential and the case of 
Q1 (its collector) is at the output potential of the regulator. 
Capacitors C1 and C2 are required to prevent oscillations 
and improve the output impedance respectively. Resistor 
R3 provides a path to unload excessive base charge from 
the base of Q1 when the regulator goes suddenly from full 
load to no load. The single point ground system shown on 
Figure 6 allows the sense pins (2 and 3) of the LM340 to 
monitor the voltage directly at the load rather than at some 
point along a (possibly) resistive ground return line carrying 
up to 5.0A of load current. Figure 9 shows the typical varia- 
tion of load regulation versus load current for the boosted 
regulator. The insertion of the external pass transistor in- 
creases the input/output differential voltage from 2.0V to 



275 



CO 

o 



approximately 4.5V. For an output current less than 5.0A, 
the R2/R1 ratio can be set lower than 4:1. Therefore, a less 
expensive PNP transistor may be used. 



V, N = 21V 
T, = +25°C 

















































10 2.0 3.0 4.0 

LOAD CURRENT (AMPS) 



FIGURE 9. Load Regulation 



TL/H/7413-9 



4. 5.0V, 5.0A VOLTAGE REGULATOR FOR TTL 

The high current 5.0V regulator for TTL shown in Figure 10 
uses a relatively inexpensive NPN pass transistor with a 
lower power PNP device to replace the single, higher cost, 
power PNP shown in Figure 6. This circuit provides a 5.0V 
output at up to 5.0A of load current with a typical load regu- 
lation of 1.8% from no load to full load. The peak instanta- 
neous output current observed was 1 0.4A at a 25°C junction 
temperature (pulsed load with a 1 .0 ms ON and a 200 ms 
OFF period) and 8.4A for a continuous short circuit. The 
typical line regulation is 0.02% of input voltage change 
('OUT = 0). 

One can easily add an overload indicator using the Nation- 
al's new NSL5027 LED. This is shown with dotted lines in 
Figure 10. With this configuration R2 is not only a current 
sharing resistor but also an overload sensor. R5 will deter- 
mine the current through the LED; the diode D2 has been 
added to match the drop across D1 . Once the load current 
exceeds 5.0A (1.0A through the LM340 assuming perfect 
current sharing and V D -| = V D2 ) Q3 turns ON and the over- 
load indicator lights up. 



Example: 
'overload = 5.0A 

I|_ed = 40 mA (light intensity of 16 mcd) 
V, N - 2.65 



Vled = 1.75, R5 



Iled 



(4-1) 



5. ADJUSTABLE OUTPUT VOLTAGE REGULATOR FOR 
INTERMEDIATE OUTPUT VOLTAGES 

The addition of two resistors to an LM340 circuit allows a 
non-standard output voltage while maintaining the limiting 
features built into IC. The example shown in Figure 1 1 pro- 
vides a 10V output using an LM340K-5.0 by raising the ref- 
erence (pin number 3) of the regulator by 5.0V. 




Vqut - iov 



TL/H/7413-11 

FIGURE 11. 10V Regulator 

The 5.0V pedestal results from the sum of regulator quies- 
cent current Iq and a current equal to Vreg/R1> flowing 
through potenteniometer R2 to ground. R2 is made adjusta- 
ble to compensate for differences in Iq and Vr E q output. 
The circuit is practical because the change in Iq due to line 
voltage and load current changes is quite small, 
The line regulation for the boosted regulator is the sum of 
the LM340 line regulation, its effects on the current through 



Vin-iov o 




4.ow r- 
I 
I 



< •— O Vqut " 6.0V 



2N2906 i * 



SINGLE 
POINT GND 



TL/H/7413-10 



'Solid tantalum 
FIGURE 10. 5.0V, 5.0A Regulator for TTL (with short circuit, thermal shutdown protection, and overload indicator) 



276 



R2, and the effects of AIq in response to input voltage 
changes. The change in output voltage is: 

(L r /V) AV, N R2 
AVqut = MV) AV| N + ' m 



+ (Q CC /V)AV, N R2 
giving a total line regulation of: 
AVqut 



AV, N 



MV)(i+£t) 



+ (Qcc/V) R2 



(5-1) 



(5-2) 



The LM340-5.0 data sheet lists AV ut < 50 mV and AIq < 
1.0 mA for AV jN = 18V at Iqut = 500 mA. This is: 



Lr/V = 



50 mV 
18V 



3mV/V 



1.0 mA _„ .... 
QCC/V = "^- = 55 ^A/V 



(5-3) 



(5-4) 



The worst case at line regulation for the circuit of Figure 1 1 
calculated by equation 5-2, Iout = 500 mA and R2 = 
31 OH is: 



AVdut / 310ft\ 

£I2yi = 3 mV/V 1 + — — - 
1.0V V 300ft/ 

+ (55 juA/V) 310ft 

^UI = 6 mV /v + 17 mV/V = 23 mV/V 
1.0V 



(5-5) 
(5-6) 



This represents a worst case line regulation value of 
0.23%/V. 

The load regulation is the sum of the LM340 voltage regula- 
tion, its effect on the current through R2, and the effect of 
AIq in response to changes in load current. Using the fol- 
lowing definitions and the notation shown on Figure 11 
AVout is: 

Zqut = Regulator output impedance: the change in output 
voltage per amp of load current change. 



Z340 = LM340 output impedance 

q cc /A= Quiescent current change per amp of load current 
change 



AVout = (Z340) AI L + ^^ AI L R2 

+ (Qcc/A) AI L R2 
and the total output impedance is: 

AVout (< + ™\ 

Zqut = ~^t z 340 I 1 + ~ ' 



AIl 

+ (Qcc/A) R2 



R1/ 



(5-7) 



(5-8) 



The LM340-5.0 data sheet gives a maximum load regulation 
L r = 50 mV and AIq = 1.0 mA for a 1.0A load change. 



Z340 



Qcc/A 



50 mV 
1.0A 

1 mA 
1.0A 



= 0.05ft 



= 100juA/A 



(5-9) 



(5-10) 



This gives a worst case dc output impedance (ac output 
impedance being a function of C2) for the 10V regulator 
using equation 5-8 of: 



Zqut = 0.05ft 1 + 



310ft \ 
300ft / 



(5-11) 



+ (100 fiA/A) 310ft 

Zqut = 0.10ft + 0.031ft = 0.13ft 

or a worst case change of approximately 1 .5% for a 1 .0A 
load change. Typical measured values are about one-third 
of the worst case value. 

6. VARIABLE OUTPUT REGULATOR 

In Figure 12 the ground terminal of the regulator is "lifted" 
by an amount equal to the voltage applied to the non-invert- 
ing input of the operational amplifier LM101A. The output 



> 
Z 

© 



V, N - 25V O 




Vout 



•Required if the regulator is located far from the power supply filter ^tr 
•Solid tantalum 

FIGURE 12. Variable Output Regulator 



TL/H/7413-12 



277 



voltage of the regulator is therefore raised to a level set by 
the value of the resistive divider R1, R2, R3 and limited by 
the input voltage. With the resistor values shown in Figure 
12, the output voltage is variable from 7.0V to 23V and the 
maximum output current (pulsed load) varies from 1 .2A to 
2.0A (Tj = 25°C) as shown in Figure 13. 





>u 


= 25 
LSED 


V 
LOA 







T 


" 


+25°C 






























































Ti = +150°C 











































































7.0 9.0 11 13 15 17 19 21 23 
Vout (V) 

TL/H/7413-13 

FIGURE 13. Maximum Output Current 

Since the LM101 A is operated with a single supply (the neg- 
ative supply pin is grounded). The common mode voltage 
V B must be at least at a 2.0 V BE + V§at above ground. R3 
has been added to insure this when R2 = 0. Furthermore 
the bias current Ib of the operational amplifier should be 
negligible compared to the current flowing through the resis- 
tive divider. 

Example: 
V| N = 25V 

VOUT MIN = 5 + V B , (R2 = 0), 
V B = R3 (I - l B ) = 2.0V 
R1 = 2.5 R3 

v OUT MAX = Vin ~ dropout volt. 
(R2 = R2 MAX ) 
R2 MAX = 3.3 R1 
So setting R3, the values of R1 and R2 can be determined. 



If the LM324 is used instead of the LM101A, R3 can be 
omitted since its common mode voltage range includes the 
ground, and then the output will be adjustable from 5 to a 
certain upper value defined by the parameters of the sys- 
tem. 

The circuit exhibits the short-circuit protection and thermal 
shutdown properties of the LM340 over the full output 
range. 

The load regulation can be predicted as: 



AVqut = 



R1 + R2 + R3 
R1 



AV340 



(6-1) 



where AV340 is the load regulation of the device given in the 
data sheet. To insure that the regulator will start up under 
full load a reverse biased small signal germanium diode, 
1N91, can be added between pins 2 and 3. 

7. VARIABLE OUTPUT REGULATOR 0.5V-29V 

When a negative supply is available an approach equivalent 
to that outlined in section 6 may be used to lower the mini- 
mum output voltage of the regulator below the nominal volt- 
age that of the LM340 regulator device. In Figure 14 the 
voltage Vq at the ground pin of the regulator is determined 
by the drop across R1 and the gain of the amplifier. The 
current I may be determined by the following relation: 



I = 



V340 R2 R5 - R3 R4 V| N ~ 
R1 R4(R2 + R3) R1 

or if R2 + R3 = R4 + R5 = R 
, V340 R2 1 



(7-1) 



(7-2) 



V| N + = 31V O— I * 




TL/H/7413-14 



'Solid tantalum 

FIGURE 14. Variable Output Voltage 0.5V- 30V 



278 



(7-3) 



considering that the output is given by: 

VrjUT = Vq + V340 
and 

V G = R1 I - V, N - (7-4) 

combining 7-2, 7-3, 7-4 an expression for the output voltage 



is: 



R2 
Vqut = V340 ^ 



(7-5) 



Notice that the output voltage is inversely proportional to R4 
so the output voltage may be adjusted very accurately for 
low values. A minimum output of 0.5V has been set. This 
implies that 



32 _o.i 5? -0.955 - 

R4 R4 R2 



(7-6) 



An absolute zero output voltage will require R4 = °° or R2 
= 0, neither being practical in this circuit. The maximum 
output voltage as shown in Figure 14 is 30V if the high volt- 
age operational amplifier LM143 is used. If only low values 
of Vout are sought, then an LM101 may be used. R1 can 
be computed from: 



R1 = 



(7-7) 



IQ340 



S - 300 

f 200 

100 



10 20 30 

Vout(V) 

TL/H/7413-15 

FIGURE 15. Typical Load Regulation for a 0.5V - 30V 
Regulator (AIqut = 1 - 0A ) 















































































































'IN 


+ 

IN 


- 


31 


1/ 
-1 


5V 












.. 








i. 


1 


2.1 

+ 5 
1 


)K 
5° 

| 


C 

| 


| 



Figure 15 illustrates the load regulation as a function of the 
output voltage. 

8. DUAL POWER SUPPLY 

The plus and minus regulators shown in Figure /Swill exhib- 
it line and load regulations consistent with their specifica- 
tions as individual regulators. In fact, operation will be en- 
tirely normal until the problem of common loads occurs. A 
30ft load from the + 1 5V output to the - 1 5V output (repre- 
senting a 0.5A starting load for the LM340K-15 if the 
LM320K-15 is already started) would allow start up of the 
LM340 in most cases. To insure LM340 startup over the full 
temperature range into a worst case 1 .0A current sink load 
the germanium power "diode" D1 has been added to the 
circuit. Since the forward voltage drop of the germanium 
diode D1 is less than that of the silicon substrate diode of 
the LM340 the external diode will take any fault current and 
allow the LM340 to start up even into a negative voltage 
load. D1 and silicon diode D2 also protect the regulator out- 
puts from inadvertant shorts between outputs and to 
ground. For shorts between outputs the voltage difference 
between either input and the opposite regulator output 
should not exceed the maximum rating of the device. 
The example shown in Figure 16 is a symmetrical +15V 
supply for linear circuits. The same principle applies to non- 
symmetrical supplies such as a +5.0V and -12V regulator 
for applications such as registers. 

9. TRACKING DUAL REGULATORS 

In Figure 17, a fraction of the negative output voltage "lifts" 
the ground pins of the negative LM320K-1 5 voltage regula- 
tor and the LM340K-15 through a voltage follower and an 
inverter respectively. The dual operational amplifier LM1558 
is used for this application and since its supply voltage may 
go as high as +22V the regulator outputs may be set be- 
tween 5.0V and 20V. Because of the tighter output toler- 
ance and the better drift of the LM320, the positive regulator 
is made to track the negative. The best tracking action is 
achieved by matching the gain of both operational amplifi- 
ers, that is, the resistors R2 and R3 must be matched as 
closely as possible. 



© 



V IN = 20V O- 



GN0O— <► 



,0— * 



C1 
0.22mF 



■C3* 
»2.2mF 



LM320K-15 



01** 
2N3612 



51 



D2 
1N4720 



-O 



V UT + 

+15V AT 1 AMP 



x 



u 



C2 
0.1»jF 



"O GND 



C4* 

1mF 



OVoot 
-15V AT 1 AMP 



TL/H/7413-16 



'Solid tantalum 

•Germanium diode (using a PNP germanium transistor with the collector shorted to the emitter) 
Note: C1 and C2 required if regulators are located far from power supply filter. 
FIGURE 16. Dual Power Supply 



279 



CO 



V IN - 20V O 



-V 1N = -20V O 




O + v 



1N4720 



O-V 



•Solid tantalum 



FIGURE 17. Tracking Dual Supply ±5.0V - ± 18V 




O+V ut = +15V 



0-Vout = -15V 



•Germanium diode 
"Solid tantalum 



TL/H/7413-18 



FIGURE 18. Tracking Dual Supply ± 15V 



Indeed, with R2 and R3 matched to better than 1%, the 
LM340 tracks the LM320 within 40-50 mV over the entire 
output range. The typical load regulation at Vout = ± 1 5V 
for the positive regulator is 40 mV from a to 1 .0A pulsed 
load and 80 mV for the negative. 

Figure 18 illustrates +15V tracking regulator, where again 
the positive regulator tracks the negative. Under steady 
state conditions V A is at a virtual ground and Vg at a V BE 
above ground. Q2 then conducts the quiescent current of 
the LM340. If -Vout becomes more negative the collector 
base junction of Q1 is forward biased thus lowering Vb and 
raising the collector voltage of Q2. As a result + Vqut rises 
and the voltage V A again reaches ground potential. 



Assuming Q1 and Q2 to be perfectly matched, the tracking 
action remains unchanged over the full operating tempera- 
ture range. 

With R1 and R2 matched to 1%, the positive regulator 
tracks the negative within 100 mV (less than 1%). The ca- 
pacitor C4 has been added to improve stability. Typical load 
regulations for the positive and negative sides from a to 
1.0A pulsed load (t N = 1.0 ms, t FF = 200 ms) are 10 mV 
and 45 mV respectively. 

10. HIGH INPUT VOLTAGE 

The input voltage of the LM340 must be kept within the 
limits specified in the data sheet. If the device is operated 



280 



V| N = 48V O 



2N3055 _ " V 



1N5359 
24V 



CI 
0.1A.F 



It 



O 
CO 



■ C(JUT 

• O.VF 



1 



"Heat sink Q1 and LM340 

FIGURE 19. High Input Voltage 



V,N=48VO 



R 
640 
2.0W 



I— VSA*— - <> — I— c 

R --*,».-,.*. — |— 0.VF 



■^ 1N4745 -p al " r 1^ 

L 16V I 

I 1 L—± 



•Heat sink Q1 and LM340 

FIGURE 20. High Input Voltage 



7r°' 



■ c 

■MyF 



TL/H/7413-20 



1 em np 

i L^vvv — (» 



1N5365 
36V 



• 0.VF 



,f _L 



-O Vqut ■ «8V 



INS3648 — r— O.ldF 

33V 



T 



•Germanium signal diooe 




TL/H/7413-21 



FIGURE 21. High Voltage Regulator 



above the absolute maximum input voltage rating, two fail- 
ure modes may occur. With the output shorted to ground, 
the series pass transistor Q16 (see Figure 4) will go to ava- 
lanche breakdown; or, even with the output not grounded, 
the transistor Q1 may fail since it is operated with a collec- 
tor-emitter voltage approximately 4.0V below the input 
If the only available supply runs at a voltage higher than the 
maximum specified, one of the simplest ways to protect the 
regulator is to connect a zener diode in series with the input 
of the device to level shift the input voltage. The drawback 
to this approach is obvious. The zener must dissipate 
(VsuPPLY - V| N MAX LM340). (I UTMAX) which may be sev- 
eral watts. Another way to overcome the over voltage prob- 
lem is illustrated in Figure 19 where an inexpensive, NPN- 
zener-resistor, combination may be considered as an equiv- 
alent to the power zener. The typical load regulation of this 
circuit is 40 mV from to 1 .0A pulsed load (Tj = 25°C) and 
the line regulation is 2.0 mV for 1.0V variation in the input 
voltage (Iout = 0). A similar alternate approach is shown in 
Figure 20. 



With an optional output capacitor the measured noise of the 
circuit was 700 jxVp-p. 

11. HIGH VOLTAGE REGULATOR 

In previous sections the principle of "lifting the ground termi- 
nal" of the LM340, using a resistor divider or an operational 
amplifier, has been illustrated. One can also raise the output 
voltage by using a zener diode connected to the ground pin 
as illustrated in the Figure 21 to obtain an output level in- 
creased by the breakdown voltage of the zener. Since the 
input voltage of the regulator has been allowed to go as 
high as 80V a level shifting transistor-zener (D2)— resistor 
combination has been added to keep the voltage across the 
LM340 under permissible values. The disadvantage of the 
system is the increased output noise and output voltage drift 
due to the added diodes. 

Indeed it can be seen that, from no load to full load condi- 
tions, the Alz will be approximately the current through R1 
( as 35 mA) and therefore the degraded regulation caused 
by D1 will be V z (at 35 mA + Iq) - V z (at Iq). 



281 



CO 

© 



The measured load regulation was 60 mV for AIout of 
5.0 mA to 1.0A (pulsed load), and the line regulation is 
0.01 %V of input voltage change (I OU t = 500 mA) and the 
typical output noise 2.0 mVp-p (C2 = 0.1 jiF). The value of 
R1 is calculated as: 



R1 



.,[ 



VlN ~ (V Z 1 + VZ2) 1 

I full load 



(11-D 



12. ELECTRONIC SHUTDOWN 

Figure 22 shows a practical method of shutting down the 
LM340 under the control of a TTL or DTL logic gate. The 
pass transistor Q1 operates either as a saturated transistor 
or as an open switch. With the logic input high (2.4V speci- 
fied minimum for TTL logic) transistor Q2 turns on and pulls 
50 mA down through R2. This provides sufficient base drive 



to maintain Q1 in saturation during the ON condition of the 
switch. When the logic input is low (0.4V specified maximum 
for TTL logic) Q2 is held off, as is Q1; and the switch is in 
the OFF condition. The observed turn-on time was 7.0 /as 
for resistive loads from 15fl to infinity and the turn-off time 
varied from approximately 3.0 jus for a 1 5fl load to 3.0 ms 
for a no-load condition. Turn-off time is controlled primarily 
by the time constant of R|_oad and C1 . 

13. VARIABLE HIGH VOLTAGE REGULATOR WITH 
OVERVOLTAGE SHUTDOWN 

A high voltage variable-output regulator may be constructed 
using the LM340 after the idea illustrated in section 7 and 
drawn in Figure 23. The principal inconvenience is that the 
voltage across the regulator must be limited to maximum 







Q1 
2N6 


107 








_ Vout = 15V 






' \ 




T~* 


^-* Iout • 1.8 AMP 


I 


R1 






3 




I 




500 












I 




L— VSArH. 










I 














— C1 


C2*— J— 
0.22jjF — | — 




> R2 

> 360 
? LOW 






— 0.1 M F 


!♦ 


1 LOGIC q '"L K Q2 










| 1 


| 0( : F INPUT U ^ 


L 2N4969 






















I"' 


J 



















•Required if the regulator is located far from the power supply filter 
"Head sink Q1 and the LM340 

FIGURE 22. Electronic Shutdown Circuit 



TL/H/7413-22 



V IN -62VO- 



■C1 
■ 0.2&F 





RESET THE REGULATOR 
AFTER SHORT CIRCUITS. 



•Solid tantalum TL/H/7413-23 

FIGURE 23. Variable High Voltage Regulator with Shortcircuit and Overvoltage Protection 



282 



/ 



rating of the device, the higher the applied input voltage the 
higher must be lifted the ground pin of the LM340. There- 
fore the range of the variable output is limited by the supply 
voltage limit of the operational amplifier and the maximum 
voltage allowed across the regulator. An estimation of this 
range is given by: 

VoUT MAX _ V OUT MIN = 

VSUPPLY MAX340 _ VNOMINAL340 _ 20V ( 13-1 ) 

Examples: 

LM340-15: V 0U TMAX - V UTMIN = 35 - 15 - 2 = 18V 
Figure 23 illustrates the above considerations. Even though 
the LM340 is by itself short circuit protected, when the out- 
put drops, also Va drops and the voltage difference across 
the device increases. If it exceeds 35V the pass transistor 
internal to the regulator will breakdown, as explained in sec- 
tion 1 1 . To remedy this, an over-voltage shutdown is includ- 



ed in the circuit. When the output drops the comparator 
switches low, pulls down the base Q2 thus opening the 
switch Q1, and shutting down the LM340. Once the short 
circuit has been removed the LM311 must be activated 
through the strobe to switch high and close Q1 , which will 
start the regulator again. The additional voltages required to 
operate the comparator may be taken from the 62V since 
the LM311 has a certain ripple rejection and the reference 
voltage (pin 3) may have a superimposed small ac signal. 
The typical load regulation can be computed from equation 
6-1. 

BIBLIOGRAPHY 

1 . AN-42: "IC Provides on Card Regulation for Logic Cir- 
cuits." 

2. Carl T. Nelson: "Power distribution and regulation can be 
simple, cheap and rugged." EDN, February 20, 1973. 



o 

00 



283 



Noise Specs Confusing? 



It's really all very simple— once you understand it. Then, 
here's the inside story on noise for those of us who haven't 
been designing low noise amplifiers for ten years. 
You hear all sorts of terms like signal-to-noise ratio, noise 
figure, noise factor, noise voltage, noise current, noise pow- 
er, noise spectral density, noise per root Hertz, broadband 
noise, spot noise, shot noise, flicker noise, excess noise, 
l/F noise, fluctuation noise, thermal noise, white noise, pink 
noise, popcorn noise, bipolar spike noise, low noise, no 
noise, and loud noise. No wonder not everyone understands 
noise specifications. 

In a case like noise, it is probably best to sort it all out from 
the beginning. So, in the beginning, there was noise; and 
then there was signal. The whole idea is to have the noise 
very small compared to the signal; or, conversely, we desire 
a high signal-to-noise ratio S/N. Now it happens that S/N is 
related to noise figure NF, noise factor F, noise power, 
noise voltage e n , and noise current I n . To simplify matters, it 
also happens that any noisy channel or amplifier can be 
completely specified for noise in terms of two noise genera- 
tors e n and i n as shown in Figure 1. 




NOISY CHANNEL 



TL/H/7414-1 

FIGURE 1. Noise Characterization of Amplifier 

All we really need to understand are NF, e n , and l n . So here 
is a rundown on these three. 

NOISE VOLTAGE, i n , or more properly, EQUIVALENT 
SHORT-CIRCUIT INPUT RMS NOISE VOLTAGE Is simply 
that noise voltage which would appear to originate at the 
input of the noiseless amplifier if the input terminals were 
shorted. It is expressed in nanovolts per root Hertz nV/VRz 
at a specified frequency, or in microvolts in a given frequen- 
cy band. It is determined or measured by shorting the input 
terminals, measuring the output rms noise, dividing by am- 
plifier gain, and referencing to the input. Hence the term, 
equivalent noise voltage. An output bandpass filter of 
known characteristic is used in measurements, and the 
measured value is divided by the square root of the band- 
width V§ if data is to be expressed per unit bandwidth or per 
root Hertz. The level of e n is not constant over the frequen- 
cy band; typically it increases at lower frequencies as shown 
in Figure 2. This increase is 1 /f NOISE. 
NOISE CURRENT, I n , or more properly, EQUIVALENT 
OPEN-CIRCUIT RMS NOISE CURRENT is that noise which 



National Semiconductor 
Application Note 1 04 




1.0 



_ 'n 



0.1 



10 



10k 



100 1.0k 

FREQUENCY (Hz) 

TL/H/7414-2 

FIGURE 2. Noise Voltage and Current for an Op Amp 

occurs apparently at the input of the noiseless amplifier due 
only to noise currents. It is expressed in picoamps per root 
Hertz pA/VHz at a specified frequency or in nanoamps in a 
given frequency band. It is measured by shunting a capaci- 
tor or resistor across the input terminals such that the noise 
current will give rise to an additional noise voltage which is 
I n x Rj n (or X cin ). The output is measured, divided by amplifi- 
er gain, referenced to input, and that contribution known to 
be due to e n and resistor noise is appropriately subtracted 
from the total measured noise. If a capacitor is used at the 
input, there is only e n and I n X cin . The ! n is measured with a 
bandpass filter and converted to pAVHz if appropriate; typi- 
cally it increases at lower frequencies for op amps and bipo- 
lar transistors, but increases at higher frequencies for field- 
effect transistors. 

NOISE FIGURE, NF is the logarithm of the ratio of input 
signal-to-noise and output signal-to-noise. 

where: S and N are power or (voltage)2 levels 
This is measured by determining the S/N at the input with 
no amplifier present, and then dividing by the measured S/N 
at the output with signal source present. 
The values of R gen and any X gen as well as frequency must 
be known to properly express NF in meaningful terms. This 
is because the amplifier l n x Z gen as well as R gen itself pro- 
duces input noise. The signal source in Figure 1 contains 
some noise. However e sig is generally considered to be 
noise free and input noise is present as the THERMAL 
NOISE of the resistive component of the signal generator 
impedance R gen . This thermal noise is WHITE in nature as it 
contains constant NOISE POWER DENSITY per unit band- 
width. It is easily seen_from Equation 2 that the e^ has the 
units V2/Hz and that (e n ) has the units V/yRz 

6r2 = 4kTRB (2) 

where: T is the temperature in °K 

R is resistor value in il 

B is bandwidth in Hz 

k is Boltzman's constant 



284 



RELATION BETWEEN e n , ! n . NF 

Now we can examine the relationship between I n and I n at 
the amplifier input. When the signal source is connected, 
the e n appears in series with the e S j g and eR. The l n flows 
through R gen thus producing another noise voltage of value 
"n * Rgen- Tnis n °i se voltage is clearly dependent upon the 
value of Rgen- All of these noise voltages add at the input in 
rms fashion; that is, as the square root of the sum of the 
squares. Thus, neglecting possible correlation between e n 
and i n , the total input noise is 

i^2 = e^2 + e^2 + i^Rgen 2 0) 

Further examination of the NF equation shows the relation- 
ship of In, I n . and NF - 

Sin x N ou t 

_ 10loo |n|E^ 

a in "^p 6r<= 

where: G p = power gain 



6m 2 

= 10 log = 

a2 



10 log 



6R 

in2 + e R 



2 + i_2 R 



gen" 



e R * 



NF= 10 



,og(l + e " 2+ ^ R ^ 2 ) 
V e R 2 / 



(4) 



Thus, for small R gen . noise voltage dominates; and for large 
Rgen. noise current becomes important. A clear advantage 
accrues to FET input amplifiers, especially at high values of 
Rgen. as the FET has essentially zero l n - Note, that for an 
NF value to have meaning, it must be accompanied by a 
value for R gen as well as frequency. 

CALCULATING TOTAL NOISE, e N 

We can generate a plot of In for various values of R ge n if 
noise voltage and current are known vs frequency. Such a 
graph is shown in Figure 5_drawn from Figure 2. To make 
this plot, the thermal noise or of the input resistance must 
be calculated from Equation 2 or taken from the graph of 
Figure 4. Remember that each term in Equation 3 must be 
squared prior to addition, so the data from Figure 4 and from 
Figure 2 is squared. A sample of this calculation follows: 

1000 



<* 10 



1.0 







































--•W 


101 


k Hill 




































. 1 10k lllliJ 













































































10 



10k 



100 1.0k 

FREQUENCY (Hz) 

TL/H/7414-3 

FIGURE 3. Total Noise for the Op Amp of Figure 2 



_ 100 





























1 


" "in 








































* 


l 










rrnr i 

«4kTRB : 




- : k ■= .38 x10' 23 : 










. T = 


00°K 










_ilL 


a 


HII 


in 



100 10k 10k 100k 1.0M 10M 100M 
R (OHMS) 

TL/H/7414-4 

FIGURE 4. Thermal Noise of Resistor 

Example 1 : Determine total equivalent input noise per unit 
bandwidth for an amplifier operating at 1 kHz from a source 
resistance of 10 kil. Use the data from Figures 2 and 4. 

1 . Read Ir from Figure 4 at 1 kft; the value is 1 2.7 nV/VRz. 

2. Read e n from Figure 2 at 1 kHz; the value is 9.5 nV/VHz. 

3. Read i n from Figure 2 at 1 kHz; the value is 0.68 pA/>/Hz. 
Multiply by 10 kfi to obtain 6.8 nVA/Hz. 

4. Square each term individually, and enter into Equation 3. 



e N 



~ V en 



2+e R 2 + i n 2R gen 2 



= ,/9.52+ 122 + 6.82 =.,/279 



4 



e N = 17.4nVA/Hz 
This is total rms noise at the input in one Hertz bandwidth at 
1 kHz. If total noise in a given bandwidth is desired, one 
must integrate the noise over a bandwidth as specified. This 
is most easily done in a noise measurement set-up, but may 
be approximated as follows: 

1. If the frequency range of interest is in the flat band; i.e., 
between 1 kHz and JO kHz in Figure 2, it is simply a 
matter of multiplying e^ by the square root of the band- 
width. Then, in the 1 kHz- 10 kHz band, total noise is 

In = 17.4^9000 
= 1.65 ju.V 

2. If the frequency band of interest is not in the flat band of 
Figure 2, one must break the band into sections, calculat- 
ing average noise in each section, squaring, multiplying 
by section bandwidth, summing all sections, and finally 
taking square root of the sum as follows: 



(5) 



e N = nj e R 2B + I (e n 2 + i n 2 Rg^), b, 

where: i is the total number of sub-blocks. 

For most purposes a sub-block may be one or two octaves. 

Example 2 details such a calculation. 

Example 2: Determine the rms noise level in the frequency 

band 50 Hz to 1 kHz for the amplifier of Figure 2 operating 

from Rg en = 2k. 

1 . Read Ir from Figure 4 at 2k, square the value, and multi- 
ply by the entire bandwidth. Easiest way is to construct a 
table as shown on the next page. 

2. Read the median value of e n in a relatively small frequen- 
cy band, say 50 Hz- 100 Hz, from Figure 2, square it and 
enter into the table. 



285 



3. Read the median value of I n in the 50 Hz- 100 Hz band 
from Figure 2, multiply by R gen = 2k, square the result 
and enter in the table. 

4. Sum the squared results from steps 2 and 3, multiply the 
sum by Af = 100-50 = 50 Hz, and enter in the table. 

5. Repeat steps 2-4 for band sections of 100 Hz-300 Hz, 
300 Hz- 1000 Hz and 1 kHz- 10 kHz. Enter results in the 
table. 

6. Sum all entires in the last column, and finally take the 
square root of this sum for the total rms noise in the 50 
Hz- 10,000 Hz band. 

7. Total i n is 1.62 ju,V in the 50 Hz- 10,000 Hz band. 
CALCULATING S/N and NF 

Signal-to-noise ratio can be easily calculated from known 
signal levels once total rms noise in the band is determined. 
Example 3 shows this rather simple calculation from Equa- 
tion 6 for the data of Example 2. 



S/N = 20 log -=r= 
e N 



(6) 



Example 3: Determine S/N for an rms e S j g = 4 mV at the 
input to the amplifier operated in Example 2. 

1 . RMS signal is e S j g = 4 mV 

2. RMS noise from Example 2 is 1 .62 jiV 

3. Calculate S/N from Equation 6 

4mV 

S/N= 20 log 

a 1.62juV 

= 20 log (2.47x1 03) 

= 20 (log 103 + log 2.47) 

= 20 (3 + 0.393) 
S/N = 68 dB 
It is also possible to plot NF vs frequency at various R gen for 
any given plot of e n and I n . However there is no specific all- 
purpose conversion plot relating NF, e n , I n , R gen and f. If 
either e n or I n is neglected, a reference chart can be con- 
structed. Figure 5 is such a plot when only e n is considered. 
It is useful for most op amps when R gen is less than about 
200ft and for FETs at any R gen (because there is no signifi- 
cant j n for FETs), however actual NF for op amps with 
Rgen > 200n is higher than indicated on the_ chart. The 
graph of Figure 5 can be used to find spot NF if e n and R gen 
are known, or to find e n if NF and R gen are known. It can 
also be used to find max R gen allowed for a given max NF 
when e n is known. In any case, values are only valid if i n 



is negligible and at the specific frequency of interest for NF 
and e n , and for 1 Hz bandwidth. If bandwidth increases, the 
plot is valid so long as e n is multiplied by VB. 



1000 



















: NF - 6.0 dB- 
NF = 5.0dB" 

:NF-4.0dB2 
NF-3.0dB! 


N5 


















NF*2.0dB^CT 
NF- 1.0 dB 7=g[ 
























p^f 








































J'ttr 































1.0 



10 100 1.0k 10k 100k 1.0M 10M 
Rw, (OHMS) 

TL/H/7414-5 

FIGURE & Spot NF vs R gen when Considering On/ye n 
and eR (not valid when ! n R gen is significant) 

THE NOISE FIGURE MYTH 

Noise figure is easy to calculate because the signal level 
need not be specified (note that e S j g drops out of Equation 
4). Because NF is so easy to handle in calculations, many 
designers tend to lose sight of the fact that signal-to-noise 
ratio (S/N) ou t is what is important in the final analysis, be it 
an audio, video, or digital data system. One can, in fact, 
choose a high Rgenjo reduce NF to near zero if I n is very 
small. In this case or is the major source of noise, over- 
shadowing e n completely. The result is very low NF, but 
very low S/N as well because of very high noise. Don't be 
fooled into believing that low NF means low noise per se\ 
Another term is worth considering, that is optimum source 
resistance Ropt- This is a value of R gen which produces the 
lowest NF in a given system. It is calculated as 



Ropt = -r 



(7) 



This has been arrived at by differentiating Equation 4 with 
respect to R gen and equating it to zero (see Appendix). Note 
that this does not mean lowest noise. 

For example, using Figure 2 to calculate Ropt at say 600 
Hz, 

10 nV 
RoPT = bT^ =14kn 



TABLE I. Noise Calculations for Example 2 



B(Hz) 


Af (Hz) 


e n 2 (nV/Hz) 


+ in 2 R fl en 2 






SUM x Af 


(nV2) 


50-100 


50 


(20)2 = 400 


(8.7 x 2.0k)2 


= 


302 


702* x 50 


35,000 


100-300 


200 


(13)2 = 169 


(8 x 2.0k)2 


= 


256 


425 x 200 


85,000 


300-1000 


700 


(10)2 = -100 


(7 x 2.0k)2 


= 


196 


296 x 700 


207,000 


1.0k- 10k 


9000 


(9)2 = 81 


(6 x 2.0k)2 


= 


144 


225 x 9000 


2,020,000 


50-10,000 


9950 


e R 2 = (5.3)2 = 28 
1620 nV = 1.62/xV 








28 x 9950 


279,000 


Total efg = 


V2,626,000 = 





•The units are as follows: (20 nV/VRz) 2 = 400 (nV) 2 /Hz 
(8.7 pAA/Hzx 2.0 kfl) 2 = (17.4 nA/Vftz) 2 = 302 (nV) 2 /Hz 
Sum = 702 (nV) 2 /Hz x 50 Hz = 35,000 (nV) 2 



286 



Then note in Figure 3, that 6n is in_the neighborhood of 
20 nV/jHz for Rg en of 14k, while e N = 10 nV/VRz for 
Rgen = 0-1 00ft. STOP! Do not pass GO. Do not be fooled. 
Using Rg Qn = Ropt does not guarantee lowest noise UN- 
LESS e S jg 2 = kRgen as in the case of transformer coupling. 
When e S jg 2 > kRg en . as is the case where signal level is 
proportional to R ge n (®sig = kR gen). jt makes sense to use 
the highest practical value of R gen - When e S j g 2 < kR gen> it 
makes sense to use a value of R ge n < Ropt- These conclu- 
sions are verified in the Appendix. 
This all means that it does not make sense to tamper with 
the R gen of existing signal sources in an attempt to make 
R gen = Ropt- Especially, do not add series resistance to a 
source for this purpose. It does make sense to adjust R ge n 
in transformer coupled circuits by manipulating turns ratio or 
to design R gen of a magnetic pick-up to operate with pre- 
amps where Ropt is known. It does make sense to increase 
the design resistance of signal sources to match or exceed 
Ropt so long as the signal voltage increases with R gen in at 
least the ratio e S j g 2 « R gen . It does not necessarily make 
sense to select an amplifier with Ropt to match R gen be- 
cause one amplifier operating at R gen = Ropt mav produce 
lower S/N than another (quieter) amplifier operating with 
Rgen ^ Ropt- 

With some amplifiers it is possible to adjust Ropt o ver a 
limited range by adjusting the first stage operating current 
(the National LM121 and LM381 for example). With these, 
one might increase operating current, varying Ropt. to find 
a condition of minimum S/N. Increasing input stage current 
decreases Ropt as e n is decreased and I n is simultaneously 
increased. 

Let us consider one additional case of a fairly complex na- 
ture just as a practical example which will point up some 
factors often overlooked. 

Example 4: Determine the S/N apparent to the ear of the 
amplifier of Figure 2 operating over 50-1 2,800 Hz when driv- 
en by a phonograph cartridge exhibiting R gen = 1350ft, 
Lgen = 0.5H, and average e^g = 4.0 mVrms. The cartridge 
is to be loaded by 47k as in Figure 6. This is equivalent to 
using a Shure V15, Type 3 for average level recorded mu- 
sic. 



1 . Choose sectional bandwidths of 1 octave each, these are 
listed in the following table. 

2. Read e n from Figure 2 as average for each octave and 
enter in the table. 

3. Read I n from Figure 2 as average for each octave and 
enter in the table. 

4. Read Ir for the R gen = 1350ft from Figure 4 and enter 
in the table. 

5. Determine the values of Z gen at the midpoint of each 
octave and enter in the table. 

6. Determine the amount of £r which reaches the amplifier 
input; this is 

- R1 

R1 + Zgen 

7. Read the noise contribution &4jy. of R1 = 47k from Fig- 
ure 4. 

8. Determine the amount of &47K which reaches the amplifi- 
er input; this is 

-gen 



24 

20 

16 

12 

S 8.0 

a 4.0 

< 

sj -*■" 

* -8.0 
-12 
-16 
-20 
-24 





R1 + Zg e n 












Him i 














' 41m ' 






























































T- 








































/ 


WEIGHTING CURVES 
A FOR LOW LEVELS. 
(ASA SOUND 






/ 






#*■ 






nutf 


MEASUREMENTS) 

1 1 111111 1 111 


Ul 



IB 



10k 



100 1.0k 

FREQUENCY (Hz) 

TL/H/7414-7 

FIGURE 7. Relative Gain for RIAA, 
ASA Weighting A, and H-F Boost Curves 



r 



~i 




L SHURE VRI5 III 
PHONO CARTRIOGE I 




PREAMPLIFIER, CURVE SHAPING, TONE CONTROL, 
I AND NOISE MEASUREMENT WEIGHTING (IF USED). 

•RECOMMENDED LOAD 

FIGURE 6. Phono Preamp Noise Sources 



TL/H/7414-6 



287 



9. Determine the effective noise contributed by I n flowing 
through the parallel combination of R1 and Z aen - This is 



-gen 



R1 



gen- 



-gen 



+ R1 



10. Square all noise voltage values resulting from steps 2, 6, 
8 and 9; and sum the squares. 

1 1 . Determine the relative gain at the midpoint of each oc- 
tave from the RIAA playback response curve of Figure 
7. 

12. Determine the relative gain at these same midpoints 
from the A weighted response curve of Figure 7 for 
sound level meters (this roughly accounts for variations 
in human hearing). 



13. Assume a tone control high frequency boost of 10 dB at 
10 kHz from Figure 7. Again determine relative response 
of octave midpoints. 

14. Multiply all relative gain values of steps 11-13 and 
square the result. 

15. Multiply the sum of the squared values from step 10 by 
the resultant relative gain of step 1 4 and by the band- 
width in each octave. 

16. Sum all the values resultant from step 15, and find the 
square root of the sum. This is the total audible rms 
noise apparent in the band. 

17. Divide e S j g = 4 mV by the total noise to find S/N = 
69.4 dB. 



STEPS FOR EXAMPLE 



1 


Frequency Band (Hz) 


50-100 


100-200 


200-400 


400-800 


800-1600 


1.6-3.2k 


3.2-6.4k 


6.4-1 2.8k 




Bandwidth, B (Hz) 


50 


100 


200 


400 


800 


1600 


3200 


6400 




Bandcenter, f (Hz) 


75 


150 


300 


600 


1200 


2400 


4800 


9600 


5 


Zg en atf(ft) 


1355 


1425 


1665 


2400 


4220 


8100 


16k 


32k 




Zgen R1 (") 


1300 


1360 


1600 


2270 


3900 


6900 


11.9k 


19k 




Zgen/R1 + Zgen) 


0.028 


0.030 


0.034 


0.485 


0.082 


0.145 


0.255 


0.400 




R1/(R1 + Z g en) 


0.97 


0.97 


0.97 


0.95 


0.92 


0.86 


0.74 


0.60 


11 


RIAA Gain, Ariaa 


5.6 


3.1 


2.0 


1.4 


1 


0.7 


0.45 


0.316 


12 


Corr for Hearing, Aa 


0.08 


0.18 


0.45 


0.80 


1 


1.26 


1 


0.5 


13 


H-F Boost, A boost 


1 


1 


1 


1 


1.12 


1.46 


2.3 


3.1 


14 


Product of Gains, A 


0.45 


0.55 


0.9 


1.12 


1.12 


1.28 


1.03 


0.49 




A2 


0.204 


0.304 


0.81 


1.26 


1.26 


1.65 


1.06 


0.241 


4 


e R (nV/VRz) 


4.74 


4.74 


4.74 


4.74 


4.74 


4.74 


4.74 


4.74 


7 


e 47k (nV/,/Hi) 


29 


29 


29 


29 


29 


29 


29 


29 


3 


I n (pAA/FS) 


0.85 


0.80 


0.77 


0.72 


0.65 


0.62 


0.60 


0.60 


2 


e n (nV/VRz) 


19 


14 


11 


10 


9.5 


9 


9 


9 


9 


©1 = in (Zgen R1) 


1.1 


1.09 


1.23 


1.63 


2.55 


4.3 


7.1 


11.4 


6 


e 2 = e R R1/(R1 + Z gen ) 


4.35 


4.35 


4.35 


4.25 


4.15 


3.86 


3.33 


2.7 


8 


e3 = e 47 k Z gen /(R1 + Zgen) 


0.81 


0.87 


0.98 


1.4 


2.4 


4.2 


7.4 


11.6 


10 


fnf 


360 


195 


121 


100 


90 


81 


81 


81 




ei2(fromi n ) 


1.21 


1.2 


1.5 


2.65 


6.5 


18.5 


50 


150 




I22 (from Ir) 


19 


19 


19 


18 


17 


15 


11 


7.2 




632 (from e 47k ) 


0.65 


0.76 


0.96 


2 


5.8 


18 


55 


135 




Se n 2 (nV2/Hz) 


381 


216 


142 


122 


120 


133 


147 


373 


15 


BA2 (Hz) 


10.2 


30.4 


162 


504 


1010 


2640 


3400 


1550 




BA2262 (nV2) 


3880 


6550 


23000 


61500 


121000 


350000 


670000 


580000 



16 2(e^2 + iTJ2 + ei|i + ~e^) BjA,2 = 1,815,930 nV2 
e N = VI = 1 .337 /LtV 

17 S/N = 20 log (4.0 mV/ 1.337 ju,V) = 69.4 dB 



288 



Note the significant contributions of l n and the 47k resistor, 
especially at high frequencies. Note also that there will be a 
difference between calculated noise and that noise mea- 
sured on broadband meters because of the A curve em- 
ployed in the example. If it were not for the A curve attenua- 
tion at low frequencies, the e n would add a very important 
contribution below 200 Hz. This would be due to the RIAA 
boost at low frequency. As it stands, 97% of the 1 .35 jliV 
would occur in the 800-12.8 kHz band alone, principally 
because of the high frequency boost and the A measure- 
ment curve. If the measurement were made wjthout either 
the high frequency boost or the A curve, the e n would be 
1.25 jliV. In this case, 76% of the total noise would arise in 
the 50 Hz-400 Hz band alone. If the A curve were used, but 
the high-frequency boost were deleted, i n would be 
0.91 jxV; and 94% would arise in the 800-12,800 Hz band 
alone. 

The three different methods of measuring would only pro- 
duce a difference of +3.5 dB in overall S/N, however the 
prime sources of the largest part of the noise and the fre- 
quency character of the noise can vary greatly with the test 
or measurement conditions. It is, then, quite important to 
know the method of measurement in order to know which 
individual noise sources in Figure 6 must be reduced in or- 
der to significantly improve S/N. 



CONCLUSIONS 

The main points in selecting low noise preamplifiers are: 

1 . Don't pad the signal source; live with the existing R gen . 

2. Select on the basis of low values of e n and especially I n if 
Rgen ' s over about a thousand fl. 

3. Don't select on the basis of NF or Ropt in most cases. 
NF specs are all right so long as you know precisely how 
to use them and so long as they are valid over the fre- 
quency band for the R gen or Z gen with which you must 
work. 

4. Be sure to (root) sum all the noise sources e n , l n and eR 
in your system over appropriate bandwidth. 

5. The higher frequencies are often the most important un- 
less there is low frequency boost or high frequency atten- 
uation in the system. 

6. Don't forget the filtering effect of the human ear in audio 
systems. Know the eventual frequency emphasis or filter- 
ing to be employed. 



> 

Z 
■ 

o 

■Ok 



APPENDIX I 

Derivation of Rqpt : 



NF=10log- 



^gerr 



e R 2 



10log(l + en2+ ^ en2 ) 



8NF 



0.435 4 kTRB (2R i n 2) - (e n 2 + i n 2 R2)4 kTB 



SR (4 kTRB)2 1 + (e n 2 + i n 2 R2)/4 kTRB 

where: R = R ge n 
Set this = 0, and 

4 kTRB(2R T^) = 4 kTB (i^2 + i^2 R2) 

2ln2R2 = 1^2 + 1^2 R2 

l^2R2 = i^2 

R2 = e^2/in2 

p - if1 

"OPT - T 



APPENDIX II 

Selecting R gen for highest S/N. 



S/N = 



B(e R 2 + e n 2 + i n 2 R2) 



For S/N to increase with R, 
8S/N 



SB 



> 



SS/N 2e sig (Se sig /SR) (e R 2 + e n 2 + i n 2 R2) - e sig 2 (4 kT + 2 i n 2R) 



SR 



B(e R 2 + e n 2 + i n 2 R2)2 



289 



APPENDIX II (Continued) 
If we set > 0, then 

2 (8e sig /8 R) (iii + i^2 + 1^2 R2) > e sig (4 kT + 2 1^2 R) 



For e S jg = k! VR, Se sig /SR 



2VR 



(2 k 1 /2VR) (etf + i^2 + !^2 R2) > ^VR (4 kT + 2 1^2 R) 

e^2 + i^2 + 1^2 R2 > 4 kTR + 2 i^2 R2 

e72>i^2R2 

R < e n /f n 

Therefore S/N increases with R gen so long as R gen ^ Ropt 

For e sig = kj R, 8e sig /8R = ^ 

2 ki (eii + e^2 + 1^2 R2) > k-|R (4 kT + 2 i^2 R) 

2ei2 + 2i^2 + 2l^2R2>4kTR + 2i^2R2 
ep + 2e^2 > 

Then S/N increases with R gen for any amplifier. 

For any e S j g < k-i x/R, an optimum R gen may be determined. Take, for example, e S j g = k-| R0- 4 , 8e S j g /8R = 0.4ki R~°- 6 

(0.8 1^ /RO-6) (ep + i^2 + 1^2 R2) > 1^ R0* (4 kT + 2 1^2 R) 

0.8 ep + 0.8 i^2 + 0.8 1^2 R2 > 4 kTR + 2 1^2 R2 

0.8 e^2 > 0.2 eP + 1 .2 1^2 R2 

Then S/N increases with R gen until 
0.25 eR2 + 1 .5 1^2 R2 = i^2 



290 



Fast IC Power Transistor 
with Thermal Protection 



National Semiconductor 
Application Note 1 1 




INTRODUCTION 

Overload protection is perhaps most necessary in power 
circuitry. This is shown by recent trends in power transistor 
technology. Safe-area, voltage and current handling capa- 
bility have been increased to limits far in excess of package 
power dissipation. In RF transistors, devices are now avail- 
able and able to withstand badly mismatched loads without 
destruction. However, for anyone working with power tran- 
sistors, they are still easily destroyed. 
Since power circuitry, in many cases, drives other low level 
circuitry — such as a voltage regulator — protection is doubly 
important. Overloads that cause power transistor failure can 
result in the destruction of the entire circuit. This is because 
the common failure mode for power transistors is a short 
from collector to emitter — applying full voltage to the load. 
In the case of a voltage regulator, the raw supply voltage 
would be applied to the low level circuitry. 
A new monolithic power transistor provides virtually abso- 
lute protection against any type of overload. Included on the 
chip are current limiting, safe area protection and thermal 
limiting. Current limiting controls the peak current through 
the chip to a safe level below the fuzing current of the alumi- 
num metalization. At high collector to emitter voltage the 
safe area limiting reduces the peak current to further protect 
the power transistor. If, under prolonged overload, power 
dissipation causes chip temperature to rise toward destruc- 
tive levels, thermal limiting turns off the device keeping the 
devices at a safe temperature. The inclusion of thermal lim- 
iting, a feature not easily available in discrete circuitry 
makes this device especially attractive in applications where 
normal protective schemes are ineffective. 
The device's high gain and fast response further reduce 
requirements of surrounding circuitry. As well as being used 
in linear applications, the IC can interface transistor-transis- 
tor logic or complementary-MOS logic to power loads with- 
out external devices. In fact, the input-current requirement 
of 3 microamperes is small enough for one CMOS gate to 
drive over 400 LM195's. 

Besides high dc current gain, the IC has low input capaci- 
tance so it can be easily driven from high impedance sourc- 
es — even at high frequencies. In a standard TO-3 power 
package, the monolithic structure ties the emitter, rather 
than the collector, to the case effectively boot-strapping the 
base-to-package capacitance. Additionally, connecting the 
emitter to the package is especially convenient for ground- 
ed emitter circuits. 

The device is fully protected against any overload condition 
when it is used below the maximum voltage rating. The cur- 
rent-limiting circuitry restricts the power dissipation to 35 
watts, 1 .8 amperes are available at collector-to-emitter volt- 



age of 1 7V decreasing to about 0.8 amperes at 40V. In reali- 
ty, however, like standard transistors, power dissipation in 
actual use is limited by the size of the external heat sink. 
Switching time is fast also. At 40V 25 Ohm load can be 
switched on or off in a relatively fast 500 ns. The internal 
planar double diffused monolithic transistors have an ft of 
200 MHz to 400 MHz. The limiting factor on overall speed is 
the protective and biasing circuitry around the output tran- 
sistors. An important performance point is that no more than 
the normal 3 p.A base current is needed for fast switching. 
To the designer, the LM1 95 acts like an ordinary power tran- 
sistor, and its operation is almost identical to that of a stan- 
dard power device. However, it provides almost absolute 
protection against any type of overload. And, since it is man- 
ufactured with standard seven-mask IC technology, the de- 
vice is produceable in large quantities at reasonable cost. 

CIRCUIT DESIGN 

Besides the protective features, the monolithic power tran- 
sistor should function as closely to a discrete transistor as 
possible. Of course, due to the circuitry on the chip, there 
will be some differences. 

Figure 1 shows a simplified schematic of the power transis- 
tor. A power NPN Darlington is driven by an input PNP. The 
PNP and output NPN's are biased by internal current source 
li. The composite three transistors yield a total current gain 
in excess of 1 6 making it easy to drive the power transis- 
tors from high impedance sources. Unlike normal power 
transistors, the base current is negative, flowing out of the 
PNP. However, in most cases this is not a problem. 



B *l fc l soo jr 




TL/H/7418-1 

FIGURE 1. Simplified Circuit of the LM195 



291 



The input PNP transistor is made with standard IC process- 
ing and has a reverse base-emitter breakdown voltage in 
excess of 40V. This allows the power transistor to be driven 
from a stiff voltage source without damage due to excessive 
base current. At input voltages in excess of about 1V the 
input PNP becomes reverse biased and no current is drawn 
from the base lead. In fact it is possible for the base of the 
monolithic transistor to be driven with up to 40V even 
though the collector to emitter voltage is low. Further, the 
input PNP isolates the base drive from the protective circuit- 
ry insuring that even with high base drive the device will be 
protected. When the device is turned off current li is shunt- 
ed from the base of the NPN transistor by the PNP and 
appears at the emitter terminal. This sets the minimum load 
current to about 2 mA, not a severe restriction for a power 
transistor. Because of the PNP and h, the power transistor 
turns "on" rather than "off" if the base is opened; however, 
most power circuits already include a base-emitter resistor 
to absorb leakage currents in present power transistors. 
A schematic of the LM1 95 is shown in Figure 2. The circuitry 
is biased by four current sources comprised of Q4, Q7, Q8 
and Q9. The operating current is set by Q5 and Q6 and is 
relatively independent of supply voltage. FET Q1 and R2 
insure reliable starting of the bias circuitry while D1 clamps 
the output of the FET limiting the starting current at high 
supply voltage. 

The output transistors Q1 9 and Q20 are driven from input 
PNP Q14. Current limiting independent of temperature 
changes is provided by Q21, Q16, and Q15. At high collec- 
tor to emitter voltages the current limit decreases due to the 
voltage across R21 from D3, D4 and R20. The double emit- 
ter structure used on Q21 allows the power limiting to more 
closely approximate constant power curve rather than a 



straight line decrease in output current as input voltage in- 
creases. 

Transistor Q13 thermally limits the device by removing the 
base drive at high temperature. The actual temperature 
sensing is done by Q11 and Q12 with Q10 regulating the 
voltage across the sensors so thermal limit temperature re- 
mains independent of supply. As temperature increases, the 
collector current of Q11 increases while the Vbe of Q12 
decreases. At about 170°C the Q12 turns on Q13 removing 
the base drive from the output transistors. Finally, C1, Q2 
and Q3 boost operating currents during switching to obtain 
faster response time and Q17 and Q18 compensate for hf e 
variations in the power devices. 

PERFORMANCE 

The new power transistor is packaged in a standard TO-3 
transistor package making it compatible with standard pow- 
er transistors. An added advantage of the monolithic struc- 
ture is that the emitter is tied to the case rather than the 
collector. This allows the device to be connected directly to 
ground in collector output applications. 

A photomicrograph of the LM1 95 is shown in Figure 3. More 
than half of the die area is needed for the output power 
transistor (Q20). Actually, the power transistor is many indi- 
vidual small transistors connected in parallel with a common 
collector. Partitioning the power device into small discrete 
areas improves power handling over a single large device. 
Firstly, the power device has ten base sections spread 
across the chip. Between the base diffusion are N + collec- 
tor contacts. Each section has its own emitter ballasting 
resistor to insure current sharing between sections. One of 
these resistors is used to sense the output current for cur- 
rent limiting. 




EMITTER BASE 



FIGURE 2. Schematic Diagram of the LM195 



292 







HJRH 






llTIII>L'iiHII|ff [J IJJBJffli 


B 


Jj; 




a 


















iW 


|fSI|pllI 




pi% 


lip?**/! 



TL/H/7418-3 

FIGURE 3. LM 195 Chip 

TABLE I. Typical Performance 

Collector to Emitter Voltage 42V 

Base to Emitter Voltage (max.) 42V 

Peak Collector Current (internally limited) 1 .8 amps 

Reverse Base Emitter Voltage 20V 

Base to Emitter Voltage (l c = 1 .0 amp) 0.9V 

Base Current 3 juA 

Saturation Voltage 2V 

Switching Time (turn on or turn off) 500 ns 

Power Dissipation (internally limited) 35 watts 

Thermal Limit Temperature 1 65°C 

Maximum Operating Temperature 1 50°C 

Thermal Resistance (Junction to Case) 2.3°C/W 

A detail of one of the base sections is shown in Figure 4. An 
interdigitated structure is used with alternating base con- 
tacts and emitter stripes. Integrated into each emitter is an 
individual emitter ballasting resistor to insure equal current 
sharing between emitters in each section. Aluminum metali- 
zation runs the length of the emitter stripe to prevent lateral 



voltage drop from debiasing a section of the stripe at high 
operating currents. All current in the stripe flows out through 
the small ballasting resistor where it is summed with the 
currents from the other stripes in the section. The partition- 
ing in conjunction with the emitter resistor gives a power 
transistor with large safe-area and good power handling ca- 
pability. 

APPLICATIONS 

With the full protection and high gain offered by this mono- 
lithic power transistor, circuit design is considerably simpli- 
fied. The inclusion of thermal limiting, not normally available 
in discrete design allows the use of smaller heat sinks than 
with conventional protection circuitry. Further, circuits where 
protection of the power device is difficult — if not impossi- 
ble — now cause no problems. 

For example, with only current limiting, the power transistor 
heat sink must be designed to dissipate worst case over- 
load power dissipation at maximum ambient temperature. 
When the power transistor is thermally limited, only normal 
power need be dissipated by the heat sink. During overload, 
the device is allowed to heat up and thermally limit, drasti- 
cally reducing the size of the heat sink needed. 
Switching circuits such as lamp drivers, solenoid drivers or 
switching regulators do not dissipate much power during 
normal operation and usually no heat sink is necessary. 
However, during overload, the full supply voltage times the 
maximum output current must be dissipated. Without a large 
heat sink standard power transistors are quickly destroyed. 
Using this new device is easier than standard power transis- 
tors but a few precautions should be observed. About the 
only way the device can be destroyed is excessive collector 
to emitter voltage or improper power supply polarity. Some- 
times when used as an emitter follower, low level high fre- 
quency oscillations can occur. These are easily cured in- 
serting a 5k-1 0k resistor in series with the base lead. The 
resistor will eliminate the oscillation without effecting speed 
or performance. Good power supply bypassing should also 
be used since this is a high frequency device. 



COLLECTOR CONTACT 
CUTOUT 




N* COLLECTOR 
DIFFUSION 



N* EMITTER 
DIFFUSION 



EMITTER 

CONTACT CUTOUT 

FOR OUTPUT CURRENT 



BASE 
CONTACT 
CUTOUT 



PBASE 
DIFFUSION 



FIGURE 4. Detailed Structure of one Section of the Power Transistor 



TL/H/7418-4 



293 



38V ' 



Q1 
2N290S 



Lin 




I 



R4 



RS 
Ik 



D1 
LM103'A R2 
3.9V ^ 390k 



R6 < 
2k ? 



• * 



02 
LM19S* 



■nrw) f m 



ci 

0.05uF 



R7 R8 

2k 2Sk 



02 
1N3890 



C2 • 
100j*F* ■ 



OUTPUT 
"4.5V -30V 



* l> 



•Sixty turns wound on arnold type A-0830B1-2 core. 
"Four devices in parallel. 
tSolid tantalum. 

FIGURE 5. 6 Amp Variable Output Switching Regulator 



TL/H/7418-5 



Figure 5 shows a 6 amp, variable output switching regulator 
for general purpose applications. An LM105 positive regula- 
tor is used as the amplifier-reference for the switching regu- 
lator. Positive feedback to induce switching is obtained from 
the LM105 at pin 1 through an LM103 diode. The positive 
feedback is applied to the internal amplifier at pin 5 and is 
independent of supply voltage. This forces the LM105 to 
drive the pass devices either "on" or "off," rather than lin- 
early controlling their conduction. Negative feedback, de- 
layed by L1 and the output capacitor, C2, causes the regula- 
tor to switch with the duty cycle automatically adjusting to 
provide a constant output. Four LM195's are used in parallel 
to obtain a 6 amp output since each device can only supply 
about 2 amps. Note that no ballasting resistors are needed 
for current sharing. When Q1 turns "on" all bases are pulled 
up to V+ and no base current flows in the LM195 transis- 
tors since the input PNP's are reverse biased. 
A two terminal current/power limiter is shown in Figure 6. 
The base and collector are shorted — turning the power tran- 
sistor on. If the load current exceeds 2 amps, the device 
current limits protecting the load. If the overload remains on, 
the device will thermal limit, further protecting itself and the 
load. In normal operation, only 2V appear across the device 
so high efficiency is realized and no heat sink is needed. 
Another method of protection would be to place the mono- 
lithic power transistor on a common heat sink with the de- 
vices to be protected. Overheating will then cause the 
LM195 to thermal limit protecting the rest of the circuitry. 




TL/H/7418-6 

FIGURE 6. Two Terminal Current Limiter 

The low base current make this power device suitable for 
many unique applications. Figure 7 shows a time delay cir- 
cuit. Upon application of power or S1 closing, the load is 
energized. Capacitor C1 slowly charges toward V~ through 
R1. When the voltage across R1 decreases below about 0.8 
volts the load is de-energized. Long delays can be obtained 
with small capacitor values since a high resistance can be 
used. 



RESET 



10mF 




TL/H/7418-7 



FIGURE 7. Time Delay Circuit 



294 




FIGURE 8. 1 Amp Positive Voltage Regulator 



tSolid tantalum. 




TL/H/7418-9 



FIGURE 9. 1 Amp Negative Regulator 



Figures 8 and 9 show how the LM195 can be used with 
standard IC's to make positive or negative voltage regula- 
tors. Since the current gain of the LM195 is so high, both 
regulators have better than 2 mV load regulation. They are 
both fully overload protected and will operate with only 2V 
input-to-output voltage differential. 
An optically isolated power transistor is shown in Figure 10. 
D1 and D2 are almost any standard optical isolator. With no 
drive, R1 absorbs the base current of Q1 holding it off. 
When power is applied to the LED, D2 allows current to flow 




TL/H/7418-10 

FIGURE 10. Optically Isolated Power Transistor 



from the collector to base. Less than 20 juA from the diode 
is needed to turn the LM195 fully on. 
An alternate connection for better ac response is to return 
the cathode of D2 to separate positive supply rather than 
the collector of Q1 , as shown in Figure 1 1, eliminating the 
added collector to base capacitance of the diode. With this 
circuit a 40V 1 amp load can be switched in 500 ns. Of 
course, any photosensitive diode can be used instead of the 
opto-isolator to make a light activated switch. 

■v + 



C"ii 



- / "^-~ i 


i A 


\ 


— 




~~s 


J 




Q1 


R1 • 




l» 




LM 






I — 



TL/H/7418-11 

FIGURE 11. Fast Optically Isolated Switch 



295 




BASE— A^^ 
500 pF 



IT 



< 



< 



•Protects against excessive 
base drive. 
•Needed for stability. 



■COLLECTOR 

TL/H/7418-13 



FIGURE 12. 1 Amp Lamp Flasher 



TL/H/7418-12 



FIGURE 13. PNP Configuration for LM195 




"Adjust for 50 mA quiescent current. 
tSolid tantalum. 



FIGURE 14. Power Op Amp 



TL/H/7418-14 



A power lamp flasher is shown in Figure 12. It is designed to 
flash a 1 2V bulb at about a once-per second rate. The re- 
verse base current of Q2 provides biasing for Q1 eliminating 
the need for a resistor. Typically, a cold bulb can draw 8 
times its normal operating current. Since the LM195 is cur- 
rent limited, high peak currents to the bulb are not experi- 
enced during turn-on. This prolongs bulb life as well as eas- 
ing the load on the power supply. 
Since no PNP equivalent of this device is available, it is 
advantageous to use the LM195 in a quasi-complementary 
configuration to simulate a power PNP. Figure 13 shows a 
quasi PNP made with an LM195. A low current PNP is used 
to drive the LM195 as the power output device. Resistor R1 
protects against overdrive destroying the PNP and, in con- 
junction with C1, frequency compensates the loop against 
oscillations. Resistor R2 sets the operating current for the 
PNP and limits the collector current. 
Figure 14 shows a power op amp with a quasi-complemen- 
tary power output stage. Q1 and Q2 form the equivalent of a 
power PNP. The circuit is simply an op amp with a power 
output stage. As shown, the circuit is stable for almost any 
load. Better bandwidth can be obtained by decreasing C1 to 
1 5 pF (to obtain 1 50 kHz full output response), but capaci- 



tive loads can cause oscillation. If due to layout, the quasi- 
complimentary loop oscillates, collector to base capaci- 
tance on Q1 will stabilize it. A simpler power op amp for up 
to 300 Hz operation is shown in Figure 15. 
One of the more difficult circuit types to protect is a current 
regulator. Since the current is already fixed, normal protec- 
tion doesn't work. Circuits to limit the voltage across the 
current regulator may allow excessive current to flow 
through the load. About the only protection method that pro- 
tects both the regulator and the driven circuit is thermal lim- 
iting. 

A 100 mA, two terminal regulator is shown in Figure 16. The 
circuit has low temperature coefficient and operates down 
to 3V. Once again, the reverse base current of the LrVM 95 to 
bias the operating circuitry. 

A 2N2222 is used to control the voltage across a current 
sensing resistor, R2 and diode D1 , and therefore the current 
through it. The voltage across the sense network is the Vbe 
of the 2N2222 plus 1.2V from the LM113. In the sense net- 
work R2 sets the current while D1 compensates for the Vbe 
of the transistor. Resistor R1 sets the current through the 
LM113 to 0.6 mA. 



296 



C4 

VFt 



r^h. 



10k 

-VW- 



■HR' 



Q1 
LM195 



tSolid tantalum. 




tr 



C5t 
VF 



FIGURE 15. 1 Amp Voltage Follower 



TL/H/7418-15 



2N2222 J T T 

SR1 V 

"T J 1 



D1 
LM113 




D2 
1N4002 



TL/H/7418-16 

FIGURE 16. Two Terminal 100 mA Current Regulator 



CONCLUSIONS 

A new IC power transistor has been developed that signifi- 
cantly improves power circuitry reliability. The device is virtu- 
ally impossible to destroy through abuse. Further it has high 
gain and fast response. It is manufactured with standard 



seven mask IC technology making it produceable in large 
quantities at reasonable prices. Finally, in addition to the 
protection features, it has high gain simplifying surrounding 
circuitry. 



297 



Use the LM158/LM258/ S^r &SJ1 
LM358 Dual, Single Supply f JrA\ 
Op Amp ^^^ 

INTRODUCTION 

Use the LM158/LM258/LM358 dual op amp with a single In many applications the LM158/LM258/LM358 can also 
supply in place of the LM1458/LM1558 with split supply and be used directly in place of LM1558 for split supply opera- 
reap the profits in terms of: tion. 

a. Input and output voltage range down to the negative SINGLE SUPPLY OPERATION 

The LM1 458/LM1 558 or similar op amps exhibit several im- 

b. Single supply operation portant limitations when operated from a single positive (or 

c. Lower standby power dissipation negative) supply. Chief among these is that input and output 

d. Higher output voltage swing s'Qna! swin 9 is severely limited for a given supply as shown 

e. Lower input offset current in F '9 ure h For linear °P eration > tne in P ut volta 9e must not 

reach within 3 volts of ground or of the supply, and output 

f. Generally similar performance otherwise range is simi | ar | y | imited t0 withjn 3 _ 5 vo , ts of ground or 

The main advantage, of course, is that you can eliminate the supply. This means that operation with a +12V supply 
negative supply in many applications and still retain equiva- could be limited as low as 2 Vp-p output swing. The LM358 
lent op amp performance. Additionally, and in some cases however, allows a 10.5 Vp-p output swing for the same 12V 
more importantly, the input and output levels are permitted supply. Admittedly these are worst case specification limits, 
to swing down to ground (negative rail) potential. Table I but they serve to illustrate the problem, 
shows the relative performance of the two in terms of guar- 
anteed and/or typical specifications. 

TABLE 1. Comparison of Dual Op Amps LM1458 and LM358 


Characteristic 


LM1458 


LM3S8 


Vio 


6mVMax 


7mVMax 


CMV| 


24 Vp-p* 


0-28.5V* 


llO 


200 nA 


50 nA 


>OB 


500 nA 


-500 nA 


CMRR 


60dBMin@ 100 Hz 
90 dB Typ 


85 dB Typ @ DC 


e n @ 1 kHz, RQENtOkn 


45 nV/VRz Typ 


40nVA/HzTyp** 


Z|N 


200 Mil Typ 


Typ 100 Mil 


AvOL 


20k Min 
100k Typ 


100k Typ 


fc 


1.1 MHz Typ 


1 MHz Typ** 


Pbw 


14 kHz Typ 


11 kHz Typ** 


dV /dt 


0.8V/ jas Typ 


0.5V/ju,sTyp** 


V @R|_= 10k/2k 


24/20 Vp-p* 


28.5 Vp-p 


'sc 


20 mA Typ 


Source 20 mA Min (40 Typ) 
Sink 10 mA Min (20 Typ) 


PSRR @ DC 


37 dB Min 
90 dB Typ 


100dBTyp 


l D (R L = oo) 


8 mA Max 


2 mA Max 


tFrom laboratory measurement 
•Based on V s = 30V on LM358 only, or V s = ± 15V 
"From data sheet typical curves 



298 



CMV, N 
8±3V 




-6±3V(R t »t0k) 
V = 6±1V 



V = 0-1 0.5V 



CMV IN 
0-10.5V 



TL/H/7424-1 

FIGURE 1. Worst Case Signal Levels with + 12V Supply 




TL/H/7424-2 



wv 




V " 10 ±7V 



R V o =+10V 

+20VO— ^W 



v,n O— J j-VW-A- 



R V o = +10V 

+ 20VO— -^^~ 



-vw 



T 




V o = 10±8.5V 



' B ■=■ 



TL/H/7424-3 



TL/H/7424-4 



FIGURE 2. Operating with AC Signals 



AC GAIN 

For AC signals the input can be capacitor coupled. The in- 
put common mode and quiescent output voltages are fixed 
at one-half the supply voltage by a resistive divider at the 
non-inverting input as shown in Figure 2. This quiescent out- 
put could be set at a lower voltage to minimize power dissi- 
pation in the LM358, if desired, so long as Vq ^ Vin pk. For 
the LM1458 the quiescent output must be higher, Vq ^ 3V 
+ Vin pk thus, for small signals, power dissipation is much 
greater with the LM1458. Example: Required Vrj = Vq ± "IV 
pk into 2k, Vsupply = as required. Find quiescent dissipa- 
tion in load and amplifier for LM1458 and LM358. 



LM358 

Vq=+1V 

v supply = +3.5V 

Ei 2 1 
Pt_OAD = — = —=0.5 mW 
LOAD R L 2k 

Pd=v s Is* + (Vs-Vq)Il 

JV 
= 3.5V X 0.7 mA + (3.5 - 1 )— 

P D = 2.45+ 1.25 = 3.7 mW 
PTOTAL = 3.7 + 0.5 = 4.2 mW 
•From typical characteristics 



LM1458 

Vq = 4V 

Vsupply = 8V 
42 

PLOAD = ^=8mW 

Pd=Pd* + (V S -Vq)I L 

4V 

= 22mW+(8-4)— 

2k 

P D = 22 + 8 = 30mW 

PTOTAL = 30 + 8 = 38 mW 

•From typical characteristics 



The LM1458 requires over twice the supply voltage and 
nearly 10 times the supply power of the LM358 in this appli- 
cation. 

INVERTING DC GAIN 

Connections and biasing for DC inverting gain are essential- 
ly the same as for the AC coupled case. Note, of course, 
that the output cannot swing negative when operated from a 
single positive supply. Figure 3 shows the connections and 
signal limitations. 

NON-INVERTING DC GAIN 

The non-inverting gain connection does not require the Vq 
biasing as before; the inverting input can be returned to 
ground in the usual manner for gains greater than unity, (see 
Figure 4). A tremendous advantage of the LM358 in this 
connection is that input signals and output may extend all 
the way to ground; therefore DC signals in the low-millivolt 
range can be handled. The LM1458 still requires that 
Vin = 3-1 7V. Therefore maximum gain is limited to Ay = 
(Vo-3)/3, or Ay max = 5.4 for a 20V supply. 
There is no similar limitation for the LM358. 



299 



ZERO T.C. INPUT BIAS CURRENT 



BALANCED SUPPLY OPERATION 



An interesting and unusual characteristic is that Iin has a The LM358 will operate satisfactorily in balanced supply op- 
zero temperature coefficient. This means that matched re- eration so long as a load is maintained from output to the 
sistance is not required at the input, allowing omission of negative supply, 
one resistor per op amp from the circuit in most cases. 



, - 3-17V O— wv-4- 



-WNr 



+20V O— ^W 



V Q - 3-1 7 V 



r 

T 



-18.5V O— ^^— •— 



-AAAr- 



"li 



I V - 3-17V 



+20VO-^VW 



V Q » 0.1 -18.5V 



r 

T 




I V ■ 0-1 8.5V 



TL/H/7424-5 



TL/H/7424-6 



FIGURE 3. Typical DC Coupled Inverting Gain 



<WSr 



V, N = 3-17V< 




AAAr 



V -3-17V 




*R1 = °° for A v = + 1 
A v ^ 5.4 for 20V Supply 



*R1 = oo for A v = +1 
Ay not limited 



FIGURE 4. Typical DC Coupled Non-Inverting Gain 



V ' 0-1 8.5V 



TL/H/7424-8 



Crossover (distortion) occurs at Vq = V s 




TL/H/7424-9 



R L + R F 

FIGURE 5. Split Supply Operation of LM358 



300 



The output load to negative supply forces the amplifier to 
source some minimum current at all times, thus eliminating 
crossover distortion. Crossover distortion without this load 
would be more severe than that expected with the normal 
op amp. Since the single supply design took notice of this 
normal load connection to ground, a class AB output stage 
was not included. Where ground referenced feedback resis- 
tors are used as in Figure 5, the required load to the nega- 
tive supply depends upon the peak negative output signal 
level desired without exhibiting crossover distortion. R|_ to 
the negative rail should be chosen small enough that the 
voltage divider formed by Rp and R|_ will permit V to swing 
negative to the desired point according to the equation: 



R L = R F 



vg-v 



Rj_ could also be returned to the positive supply with the 
advantage that V max would never exceed (Vs + - 1 .5V). 
Then with +15V supplies R L min would be °- 12 R F- Tne 
disadvantage would be that the LM358 can source twice as 
much current as it can sink, therefore R|_ to negative supply 
can be one-half the value of R|_ to positive supply. 
The need for single or split supply is based on system re- 
quirements which may be other than op amp oriented. How- 
ever if the only need for balanced supplies is to simplify the 
biasing of op amps, there are many systems which can find 
a cost effective benefit in operating LM358's from single 
supplies rather than standard op amps from balanced sup- 
plies. Of the usual op amp circuits, Table II shows those few 
which have limited function with single supply operation. 
Most are based on the premise that to operate from a single 
supply, a reference Vq at about one-half the supply be avail- 
able for bias or (zero) signal reference. The basic circuits 
are those listed in AN-20. 



TABLE II. Conventional Op Amp Circuits 
Suitable for Single Supply Operation 



Application 

AC Coupled amp! 

Inverting amp 

Non-inverting amp 

Unity gain buffer 

Summing amp 

Difference amp 

Differentiator 

Integrator 

LP Filter 

l-V Connector 

PE Cell Amp 

I Source 

I sink 

Volt Ref 

FW Rectifier 

Sine wave osc 

Triangle generator 

Threshold detector 

Tracking, regulator PS 

Programmable PS 

Peak Detector 



Limitations 

Vq* 

Vq 

OK* 

OK 

Vq 

Vq 

Vq 

Vq 

Vq 

Vq 

0K 1.5 

'O MIN = -57 

OK R1 

OK 

Vq or modified circuit 

Vq 

Vq 

OK 

Not practical 

OK 

OK to V| N = 



o> 



v s 



tSee AN20 for conventional circuits 

*Vq denotes need for a reference voltage, usually at about -^ 

OK means no reference voltage required 



301 



LM 143 Monolithic 
High Voltage 
Operational Amplifier 
Applications 



INTRODUCTION 

The LM143 is a general purpose, high voltage operational 
amplifier featuring ±40V maximum supply voltage opera- 
tion, output swing to ±37V, ±38V input common-mode 
range, input overvoltage protection up to ±40V and slew 
rate greater than 2V/ju.s*. Offset null capability plus low in- 
put bias and offset currents (8 nA and 1 nA respectively) 
minimize errors in both high and low source impedance ap- 
plications. Due to isothermal symmetry of the chip layout, 
gain is constant for loads ^ 2 kfl at output levels to ± 37V. 
Because of these features, the LM143 offers advantages 
not found in other general purpose op amps. The LM143 
may, in fact, be used as an improved performance, plug-in 
replacement for the LM741 in most applications. 
This paper describes the operation of the LM143 and pre- 
sents applications which take advantage of its unique, high 
voltage capabilities. Obviously, other applications exist 
where the low input current and high slew rate of the LM1 43 
are useful. (See AN-29 on the LM108.) Application tips are 
included in the appendix to guide the user toward reliable, 
trouble-free operation. 

CIRCUIT DESCRIPTION 

A simplified schematic of the LM143, shown in Figure 1, 
illustrates the basic circuit operation. The super-/? input 
transistors^), Q1 and Q2, are used as emitter followers to 
achieve low input bias currents. Although these devices ex- 
hibit /8 = 2000-5000, they inherently have a low collector- 
base breakdown voltage of about 4V. Therefore, active volt- 
age clamps Q3 and Q4 protect Q1 and Q2 under all input 



National Semiconductor 
Application Note 1 27 




conditions including common-mode and differential over- 
voltage. Other NPNs in the circuit are representative of 
those found in standard IC op amps (/3 ~ 200, LVqeo = 
50-70V). 

The input stage differential amplifier Q7 and Q8 with large 
base width exhibit LV C eo = 90V to 110V and high BV EB o 
so readily withstand input overvoltages. The total input 
stage collector current (li =80 /a.A) is made higher than in 
most op amps to improve slew rate. Emitter degeneration 
resistors, R10 and R11, reduce transconductance( 2 ) to limit 
small signal bandwidth at 1 MHz for a phase margin of 75°. 
Q16 and Q17 function as active collector loads for Q7 and 
Q8 and provide differential to single-ended current conver- 
sion with full differential gain. 

One of the highest breakdown voltages available in stan- 
dard planar NPN processing is the collector-base, BVcbo 
which is typically 90V to 120V. To make use of this high 
voltage capability in the active region, the second stage 
consists of a cascode (common emitter-common base pair) 
connection of Q21 and Q23. The internal voltage bias Vgi, 
shunts avalanche-induced leakage current away from the 
base of Q21, avoiding /J multiplication as found in the 
LVqeo mode. Q23 and emitter follower Q22 are internally 
biased at a low voltage so the BVceo mode is impossible. 
Frequency compensation is achieved with an internal, high 
voltage capacitor, Cq. 

* An externally compensated version of the LM143, the LM144, offers even 
higher slew rate in most applications. The LM144 is pin-for-pin compatible 
with the LM101A. 




Ov 0UT 



FIGURE 1. LM143 Simplified Schematic 



302 



The second stage drives a complementary class AB output 
stage. A cascode connection of Q32 and Q34 is again em- 
ployed for high breakdown voltage. The associated voltage 
bias, Vb2. is internally derived. A Darlington PNP pair, Q39 
and Q40 with BVceo = 100V > provides the active pull- 
down. 

HIGH VOLTAGE APPLICATIONS 

The following applications make use of the high voltage ca- 
pabilities of the LM143. As with most general purpose op 
amps, the power supplies should be adequately bypassed 
to ground with 0.1 ju,F capacitors. 

130 Vp-p Drive to a Floating Load 

A circuit diagram using two LM143's to drive up to 130V 

peak-to-peak is given in Figure 2. 

A non-inverting voltage amplifier, with a gain of Ay = 1 + 

(R2/R1), is followed by a unity gain inverter. The load is 

applied across the outputs of A1 and A2. Therefore, 

VrjUT = V1 - V2 = V1 - (-V1) = 2V1. If VI = 65 Vp-p, 

then2V1 = 130 Vp-p. 

The above circuit was breadboarded and the results are as 

follows: 

i ) Maximum output voltage: 138 Vp-p undipped into 10 kfl 

load 
ii ) Slew rate: 6V//u.s 

±34V Common-Mode Range Instrumentation Amplifier 
An instrumentation amplifier with ±34V common-mode 
range, high input impedance and a gain of X1000 is shown 
in Figure 3. 

For a differential input signal, Vin, A1 and A2 act as non-in- 
verting amplifiers of gain A V i = 1 + (2R1/R2), where 
R1 = R3. However, the gain is unity for common-mode 



W 3 * V CERAMIC 




All resistors are 1%, 1/4W 



V + = +31V 



TL/H/7432-2 

FIGURE 2. 130V Drive Across a Floating Load 

signals since voltages V1 and V2 are in phase, and no cur- 
rent flow is developed through R1, R2 and R3. The second 
stage is simply an op amp connected as a simple differential 
amplifier of gain, Av2 = (R5/R4), where R5 = R7 and 
R4 = R6. The total gain of the instrumentation amplifier is 
I 2R1\/R5\ [ A 2x100k\ /1.0M\ 

= 1000 
R7 may be adjusted to take up the resistance tolerances of 
R4, R5 and R6 for best common-mode rejection (CMR). 
Also, R2 may be made adjustable to vary the gain of the 
instrumentation amplifier without degrading the CMR. 




-Ov 0UT 



/ o p-t \ pe 

V S = ±38V A V = y 1 + — J — Where: R4 



R6 
R5 = R7 

All resistors are 1 %, 1 / 4 W 
*R2 may be adjustable to trim the gain. 

**R7 may be adjusted to compensate for the resistance tolerance ot R4-R7 
for best CMR. 



TL/H/7432-3 

FIGURE 3. Wide Common-Mode Range Instrumentation Amplifier 



303 



CM 



Laboratory evaluation of this circuit revealed noise and 
CMR data as follows: 

i) Frequency response with 10k load and Av = 1000: 
-3.0 dB at 8.9 kHz 

ii) CMR measurements (common-mode signal of ±34 

Vp-p) in Figure 4 
iii ) Noise measurements in Figure 5 





















90 












"S 


= 








Rs 


= 1k 










80 


























RS = 1 


Ik 






XI 000 
n. INST" 
























r*3 


4V 






V 













100 200 300 400 

f(Hz) 

TL/H/7432-4 

FIGURE 4. Common-Mode Rejection Measurements 



o '"« 




































o 70 

> 


































1 5° 
£=? 31 

h- — 

Z 

J 20 

> 

a 

i 

















































































100 1.0k 

f(Hz) 



TL/H/7432-5 



FIGURE 5. Noise Measurements 
High Compliance Current Source 

A current source with a compliance of ±28V is shown in 
Figure 6. 




The non-inverting input of the op amp senses the current 
through R4 to establish an output current, Iq proportional to 
the input voltage. The expression for Iq is 



"0 = 



E, N R2 



R1 R4 



0.1 mA. 



E|N- 



R3 keeps the circuit stable under any value of load resist- 
ance. Measured circuit performance is as follows: 

lOMAX = ± 3.5 mA at E| N = ±35V 
R OUT = 2 Mn at Iout = ±2.0 mA 

CURRENT BOOSTED APPLICATIONS 

Because of the high voltage capability of the LM143, some 
thought must be given for the selection of the minimum load 
resistance. At an ambient temperature of 25°C, the LM143 
can dissipate 680 mW. Worst case dissipation arises when 
the load resistance Rl is connected to one supply and 
Vq = 0. Then the amplifier sources lo = (38V7Rl) with 
38V internal voltage drop. During this condition, 

Ei 2 (38V)2 
P M ax = 680 mW = -J- = i— - L 
R L R L 

1444V2 

orR L = ,., ~ 2.1 kft 

680 mW 

Hence, load resistances less than 2k will cause excessive 
power dissipation. 

Simple Power Boost Circuit 

For loads less than 2 kfl, a power boost circuit should be 
added. The simple booster shown in Figure 7 has the ad- 
vantage of minimal parts count, but crossover distortion is 
noticeable and there is no short circuit protection; hence, 
either the LM143 or the boost transistors may fail under 
short circuit conditions. 



V|N' 




V UT 



Heat sink is a Thermalloy No. 2230-5 or equivalent. 
All resistors are 10%, 1W. 

FIGURE 7. Simple Power Boost Circuit 



TL/H/7432-6 
All resistors 1 % metal film, %W unless otherwise specified. 

FIGURE 6. High-Compliance Current Source 



304 



100 mA Current Boost Circuit 

With the addition of 4 diodes, a resistor and a capacitor, the 
booster circuit can be short circuit protected at 100 mA as 
shown in Figure 8. 

<38V 



V|N 




Ot 02 

I N N I 



D3 D4 

■W-M 



-O v 0UT 



-38V 

TL/H/7432- 
Heat sink is a Thermalloy No. 2230-5 or equivalent. 
All diodes are 1N914. 
All resistors are ViW, 10%. 

FIGURE 8. 100 mA Current Boost Circuit 



R1 protects the LM143 by limiting the maximum drive cur- 
rent to (38V/3.0k) * 12.5 mA, thereby keeping safely within 
the device dissipation limit of 680 mW. D1— D4 in conjuction 
with R2 and R3 protect the output transistors Q1 and Q2 by 
shunting the output drive current if the voltage drop across 
R2 or R3 exceeds 0.7V. 
Breadboard Data: 

i) Frequency Response: Limited by LM143 frequency re- 
sponse and slew rate, 
ii ) Step response for unity gain, voltage follower configura- 
tion: Less than 10% overshoot for 1.0V step with 0.01 
ju,F capacitive load, 50% overshoot with 0.47 jnF capaci- 
tive load. The circuit is unconditionally stable for capaci- 
tive loads, 
iii ) Output Voltage: ±33 Vp-p into 400H load 

1.0 Amp Class AB Current Booster 

If crossover distortion is objectionable and currents of up to 
1 .0A are needed, the circuit in Figure 9 should be used. 
The output of the LM143 drives a class AB complementary 
output stage. The quiescent current for the output stage is 
set by the current flow through R4, R5 and diodes D1 -D4. 
The diodes D1-D4 are on a common heat sink with the 
output transistors Q3 and Q4 so that the voltage drops 
across the diodes and base-emitter junctions of the output 



V* = +38V 
O 



VinO- 



V" - -38V 



-VSrV- 



T0.1pF 
CERAMIC 




-Q 



D5 D6 



03' B.OVf 
07 08 

H H 



K^2N403 




0.1»jF 
CERAMIC | 



4— OVOUT 



TL/H/7432-9 



tPut on common heat sink, Thermalloy 6006B or equivalent. 
All diodes are 1N3193. 
All resistors are 10%, 1 / 4 W except as noted. 

FIGURE 9. 1 Amp Class AB Current Booster with Short Circuit Protection 



305 



transistors will track with temperature. Normally, R4 and R5 
supply the current drive for the output Darlingtons, Q1, Q3 
and Q2, Q4, but if additional drive is needed, the LM143 
supplies the remainder through R2 and R3. For short circuit- 
ed load, the drive current is bypassed around the output 
transistors through D1, D5 and D6 during the positive half 
cycle and through D4, D7 and D8 during the negative half 
cycle. Drive current bypassing, or output current limiting, oc- 
curs whenever R8 or R9 sees more than one diode drop 
(« 0.7V). An expression for the maximum output current is 



'max = 



0.7V 



0.68ft 

l M AX = 1-0A. 

Capacitor C1 stabilizes the circuit under most feedback and 
load conditions and C3 and C4 bypass the power supply. 
Measured performance is as follows: 

i) Maximum output voltage with Rl = 40ft: + 29.6V, -28V 
with V s = ±38 V DC . 

ii ) Harmonic distortion measurements of Figure 10 were 
measured with a closed loop gain of 10. 





,. 


r - 


r 


















. L 7"" 

































































































































































































































































10 20 30 40 SO 60 

V M (V) 

TL/H/7432-10 

FIGURE 10. Harmonic Distortion Measurements 

Very High Current Booster with High Compliance 

If very high peak drive current is required in addition to a 
capability for the output swing to within 4.0V of the supplies 
under full load, the circuit in Figure 11 should be used. 



U? 



o , , 

I I " 0.047 M F 




3.0W 



X 0.047 (it 
-38VU — 

All resistors are 1 / 2 W, 5% unless otherwise noted. 
All capacitors are 20%, 100V, ceramic disc unless otherwise noted. 
ttOutput current limit adjust. 

FIGURE 1 1. Very High Current Booster with High Compliance 



TL/H/7432-11 



306 



Excluding the LM143, the current booster has three stages. 
The first stage is made up of Q1 and Q2 which level shifts 
and boosts the current output of the LM143 to about 
100 mA. Q3 and Q4 further boost the output of Q1 and Q2 
to about 1.0A. Q5 and Q6 then have adequate drive to 
source and sink at least 1 0A. There is no quiescent current 
path when the output voltage is zero since Q1 and Q2 are 
biased off. 

The short circuit protection circuit is made up of Q7 and Q9 
on the positive side and Q8 and Q1 on the negative side. 
Q9 or Q10 turns on as soon as Vbe - 0.7V appears across 
R10 when the output terminal is shorted to ground. Then Q7 
or Q8 bypass the drive to the output devices, Q5 and Q6. 
Since R10 is 0.3(1, current limiting under short circuited out- 
put occurs at 2.3A and is relatively independent of the cur- 
rent limit adjustment resistor, R11. An expression for the 
maximum output current, Iout max. with Vout and R11 as 
variables is 



I'OUTMAXI - 



(|Vqut1-Vdi)R13 

R11 + R12 + R13 



+ V B E9 



R10 



+ 0.7V 



(IVqutI - Q-7) 56n 

R11 + 526Q 

0.3H 

The equation is valid for both output polarities. The plot in 
Figure 12 superimposes the above equation on the maxi- 
mum operating area curve for the 2N3773 and illustrates the 
safe area protection feature. 

16 




TL/H/7432-12 

FIGURE 12. Maximum Output Current 
as a Function of R11 and Vout 

The diodes, D1 and D2, are in the circuit to keep the base- 
emitter junctions of Q9 and Q10 from being reversed biased 
during the opposite polarity output voltage swings. C1 , C2, 
C3, C6, C7 and C9 are judiciously inserted in the circuit to 
prevent oscillation. R17, R18, C8 and L1 are used in the 
circuit to maintain stability under all load conditions. Diodes 
D3 and D4 provide protection for inductive loads. 



All measurements taken with a 4n load and ±38V supplies 

unless otherwise stated: 

i ) Maximum power out: 144 Wrms 

ii ) Frequency response: 

a) -3.0 dB at 10 kHz at full power 

b) -3.0 dB at 11.5 kHz at 10 Vp-p out 
iii) Maximum output voltage: ± 34V 

iv) Maximum capacitive load: 10 /u.F with 10% overshoot 

for a small signal step response 
v ) DC deadband: 20 /xV 
vi) Quiescent current: 12.7 mA (positive supply), 2.1 mA 

(negative supply) 
vii ) Input impedance: 1 Mil 
viii ) Voltage gain: 21 
HIGH POWER APPLICATIONS 

90 Wrms Audio Power Amplifier 

A circuit diagram of an audio power amplifier which is capa- 
ble of 90 Wrms into a 4fl speaker or 70 Wrms into an 8fl 
speaker is given in Figure 13. The circuit features safe area, 
short circuit and overload protection, harmonic distortion 
less than 0.1% at 1.0 kHz, and an all NPN output stage. 
The output of the LM143 drives a quasi-complementary out- 
put stage made up of Q1 , Q2, Q3 and Q4. This quasi-com- 
plementary circuit, which makes possible an all NPN output, 
was chosen over the complementary output circuit due to 
the lack of low cost high voltage power PNP transistors. 
Safe area current limiting occurs whenever the output cur- 
rent is 

(|V utI-Vd3)R11 






R11 + R13 



+ V BE 5 



R12 



|l0UTMAxl - 

where R11 = R15 = 330ft, 

R13 = R14 = 3.9k, 
R12 = R16 = 0.25Hand 

V B E5 = V B E6 = V D3 =V D 4 = 0.7V. 

If the output is shorted, the above equation simplifies to 

VBE5 = 0-7V _ 
R12 0.25H 

If the output voltage is 30V, 



'OUTMAX - 



2.8A 



'OUTMAX = 



(30V -0.7V) 330 
4.23k 
0.25H 



+ 0.7V 



2.3 + 0.7V 
0.25 



12A 



307 



CM 




izj 



-O OUTPUT 



tPut on common heat sink, Thermalloy 6006B or 

equivalent. 
•Turns of No. 20 wire on a %" form. 

All resistors 1 / 2 W, 5% except as noted. 

All capacitors 100 Vdc WV except as noted. 



X0.VF 
CERAMIC 



TL/H/7432-13 



FIGURE 13. 90W Audio Power Amplifier 



The maximum output current, lo(MAX). versus Vo is plotted 
in Figure 14. D4 and D3 are in the circuit to keep Q5 off 
during the negative half of the output voltage cycle and Q6 
off during the positive half cycle. 

















12 


























|u 


























4.0 









































±V (V) 

TL/H/7432-14 

FIGURE 14. Output Current Limiting as a 
Function of Output Voltage 

The output stage is biased into class AB operation by using 
the resistor string R4, R5, R7 and R8 to set the voltage 
drops across R6, D1 and D2, which then determine the qui- 
escent current through the output transistors. These diodes 
are thermally coupled to the output devices to track their 
base-emitter junction voltages with temperature. Low distor- 
tion at low power levels is achieved by adjusting R6 to set 
the quiescent current through Q3 and Q2 to about 1 00 mA. 



Figure 15 shows a plot of distortion at 50 mW versus quies- 
cent current. C2 and C3 are connected between the output 
and the R4, R5 and R7, R8 junctions to provide a "boot- 
strapped" drive potential for the output stage during output 
voltage swings near the power supply potentials. The abso- 
lute magnitudes of the voltages at these junctions exceed 
the power supply voltages during the high outputs swings so 
that adequate current drives to Q4 and Q1 are available. C1 
and C4 are used for compensating the output stage. C5 and 
C6 are used for power supply bypassing. R18, C7, R19 and 
L1 are included in the circuit to keep the amplifier stable 
under all load conditions. D5 and D6 provide protection for 
inductive loads. 





















1.0 
























l n 


0.8 


























rf- 


OkH 






0.6 






























0.4 


















■f = 


.Okl 


ul 












0.2 


V 
















V 


• — 
























T~ 



40 80 120 160 

l Q (mA) 

TL/H/7432-15 

FIGURE 15. Quiescent Current vs Distortion 



308 



The input impedance of the audio amplifier is simply the 
value of R3. To keep the output offset voltages to a mini- 
mum, R3 = R1 || R2. The voltage gain is 



A v = 1 + 



R1 
R2 



2.0M „„ 

1 + = 21 

100k 



The following data was taken with Vs = +38V: 
i ) Maximum power output before visible clipping: 

a) 90 Wrms at 1 .0 kHz into 4ft load 

b) 70 Wrms at 1 .0 kHz into 8ft load 

ii ) Distortion measurement: distortion versus frequency and 

power is plotted in Figures 16 and 17. 
iii ) Maximum capacitive load: 20 ju,F 
iv) Output noise, 10 Hz to 20 kHz: 100 juVrms 
v) Frequency response: 

a) Small signal (1.0 Vrms into 4.0ft): -3.0 dB at 40 kHz 

b) Power (90W into 4ft): -3.0 dB at 29 kHz 

c) Power (70W into 8ft): -3.0 dB at 30 kHz 

0.6 



D.4 

0.3 

0.2 

0.1 


10 



— I 

R 


-TTT 
t -4 


TT ■'- 
$1 






"»i 


III/ 

-90WX. 








































/Lp.ow 














lifiow. 




















1 









10k 20k 



100 1.0k 

MHz) 

TL/H/7432-16 

FIGURE 16. Distortion vs Frequency, Rl = 4ft 



R 


I. 


urn 

= 8fi 


I 






















P 


) = 1.0Wy 

NOW 




























jflffl70W 






III 








ill 



* °- 3 

a 
x 
•- 0.2 

0.1 



10 100 1.0k 10k 20k 

TL/H/7432-17 

FIGURE 17. Distortion vs Frequency, R L = 8ft 

POWER SUPPLY CIRCUITS 

The ability of the LM143 to withstand up to 80V can be 
exploited fully in the design of regulated power supplies. 
The circuits to be described use a zener reference voltage, 
an IC voltage amplifier, and a discrete power transistor pass 
element. If care is taken to keep the voltage drop across the 



pass element within 40V, standard three terminal voltage 
regulators such as the LM340, LM120, etc. may be used as 
pass elements and significantly decrease parts count and 
circuit complexity. Circuits using this approach are given in 
the LM340 application note (see AN-103). 

A Tracking ± 65V Supply with 500 mA Output 

A tracking power supply circuit can be made by modifying 
the circuit for the 1 30 Vp-p driver circuit. The modified circuit 
is given in Figure 18. 

A 2N4275 is used as a stable zener voltage reference of 
about 6.5V. Its output is amplified from one to about 10 
times by the circuitry associated with IC1 . The output of IC1 
is applied through R10 to the Darlington connected transis- 
tors, Q2 and Q3. The feedback resistor, R5, one end of 
which is connected to the V + output node, is made variable 
so that the V+ output voltage will vary from 6.5V to about 
+ 65V. The V+ output is applied to a unity gain inverting 
power amplifier to generate the V - output voltage. The out- 
put circuit of the unity gain inverter uses a composite PNP, 
Q4 and Q5, to provide the current boost. 
Since the input terminals of A2 are at ground potential, the 
positive supply lead cannot be grounded; instead, it is con- 
nected to the output of a 4.7V zener diode, D8, to keep 
within the input common-mode range. 
C1 , C3 and C4 are used for decreasing the power supply 
noise. C2 is used in bypassing most of the noise generated 
by the reference voltage and C5 and C6 are used to reduce 
the voltage output noise. Short circuit protection is provided 
by D1, D2, D3, R10 and R14 on the positive side and by D4, 
D5, R11 and R15 on the negative side. The short circuit 
protection circuit is the same as the one used in the 1 .OA 
current booster circuit. 
The short circuit current is given by 

. s Yje s Ybe 
MAX R14 R15 



0.7 
0.56 



= 1.25A 



where Vbe = voltage drop across a diode. 

±65V, 1.0A Power Supply with Continuously Variable 
Output Current and Voltage 

If a continuously variable output current as well as output 
voltage supply is needed, a power supply circuit given in 
Figure 19 will do the job. It has an output range from 7.1V to 
65V with an adjustable output current range of to 1 .0A. 
Basically, the power supply circuit is a non-ideal voltage 
source in series with a non-ideal current source. A reference 
voltage of approximately 6.5V is obtained by zenering the 
base-emitter junction of the 2N4275. The positive tempera- 
ture coefficient of the zenering voltage is compensated by 
the negative temperature coefficient of the forward biased 
base-collector junction. The output of the voltage reference 
goes to the variable gain power amplifier made up of IC2, 
Q6, Q7 and their associated components and to a reference 
current source made up of Q2, D1 and components around 
them. The variable gain power amplifier multiplies the refer- 
ence voltage from one to ten times due to the variable feed- 
back resistor, R17. since the maximum current output of IC2 
is at most 20 mA, the Darlington connected Q6 and Q7 are 
used to boost the available output current to 500 mA. 



309 



CM 



C1 -i-l 
50V I 



100k 

t-VvV 



r 



k 2N 




±65V 
■ REGULATEO 
OUTPUT 



tPut on common heat sink, Thermalloy 6006B or equivalent. 
All resistors are 1 / 2 W, 5%, except as noted. 

FIGURE 18. Tracking 65V, 1 A Power Supply with Short Circuit Protection 



TL/H/7432-18 




OVQUT 



<oov oc 'I'JSSft 



tPut on common heat sink, Thermalloy 6006B or equivalent. 
All resistors ViW, 10% unless otherwise noted. 
All capacitors 20%. 

FIGURE 19. 1A, 65V Power Supply with Variable Current Limit 



TL/H/7432-19 



310 



Breadboard Data for the Tracking 65V Power Supply 

V| N = ±75V, Iqut = ±500 mA, Tj = 25°C, T A = 25°C, V 0u t = ±40V, unless otherwise specified. 



Parameter 


Conditions 


Measured 
Data 


+ V UT 


-VoUT 


Load Regulation 


^ loUT ^ 500 mA 


0.5 mV 


1.0 mV 


Line Regulation 


|±50V|^V| N =£|±80V| 
Iqut = ± 100 mA 
Iqut = ± 500 mA 


175mV 
169mV 


176mV 
173mV 


Quiescent Current 


Iout = 


Pos. Supply 
28.22 mA 


Neg. Supply 
6.55 mA 


Output Noise Voltage* 


10 Hz <: f <: 100 kHz 


0.125 mV 


0.135 mV 


Ripple Rejection 


Iout = ±20 mA, 
f = 120 Hz 


-72.5dB 


-63.4 dB 


Output Voltage Drift* 




3.38 mV/°C 


3.43 mV/°C 



IN) 
-si 



•The output noise and drift are due primarily to the zener reference. 



Measured Performance of the 1 A, 65V Power Supply 

V, N = +76V, Iqut = 50 ° mA - T j = 25 ° c - v OUT = +40V unless otherwise specified 



Parameter 


Conditions 


Measured 
Data 


Load Regulation 


o £ Iout ^ 500 mA 
(Pulsed Load) 


5.0 mV 


Line Regulation 


46V <. V| N <; 76V 






Iqut = 100 mA 


297 mV 




Iqut = 500 mA 


286 mV 




(dc Loads) 




Maximum Output 


dc Load 


68.6V 


Voltage 






Quiescent Current 




21.4 mA 


Output Noise Voltage* 


10Hz^f <: 100 kHz 


0.280 mV 


Ripple Rejection 


Iout = 20 mA 






f = 120 Hz 


66.6 dB 




A V S = 3.0 Vp-p 






A Vo = 6.0 mVp-p 




Loads are Pulsed Loads 


200 ju.s Pulse Ever 


y 200 ms 



•The output noise is due primarily to zener reference 



The power current source is an op amp used as a differen- 
tial amplifier which senses the voltage drop across R8 and 
maintains this same voltage across R14. Hence, the maxi- 
mum output current is 

R8 1 0k 

Iout = * l REF < - 1 — x 5.0 mA = 1 .0A. 

■out R14 Mtt- 5Qn 

Since the output load under most conditions will not de- 
mand what the power current source can deliver, Q4 and 
Q5 will remain in saturation during normal operation. When 
Q4 and Q5 are pulled out of saturation, the output load volt- 
age will drop until the load current just equals what is avail- 



able from the power current source. Because the positive 
supply terminal of IC2 is tied to the collectors of Q4 and Q5, 
IC2 will supply just enough current drive to Q6 and Q7 to 
keep itself on. Hence, a current limiting resistor is unneces- 
sary for IC2. A 10k current limiting resistor, R13, is present 
since the total unregulated power supply voltage is available 
for IC1 . R6 is used to stay within the input common-mode 
voltage range of IC1 . 

I R EF is derived from the 6.5V reference source, Q1 , by using 
Q2 in a current source configuration. R22 is made adjusta- 
ble so that Iref can be set for 5.0 mA. 



311 



CM 



CONCLUSION 

The LM143 is a high performance operational amplifier suit- 
ed for applications requiring supply voltages up to ±40V. 
The LM143 is especially useful in power supply circuits 
where the unregulated voltages are as high as ±40V and in 
amplifier circuits where output voltages greater than ± 30V 
peak are needed. The LM143 is internally compensated and 
is pin-for-pin compatible with the LM741 . Compared with the 
LM741, the LM143 exhibits an order of magnitude lower 
input bias currents, better than five times the slew rate and 
twice the output voltage swing. 

APPENDIX 

Toward the goal of trouble-free applications, this appendix 
details some of the more subtle features of the LM143 and 
reviews application hints pertinent both to op amps in gen- 
eral and the LM143 in particular. The complete schematic of 
the LM143 is shown in Figure 20. 

The circuit starts drawing supply current, at supply voltages 
of + 4V, when current is provided to a 7.5V zener diode D5 



by the collector FET Q41 . The gate-channel junction of Q41 
exhibits 100V breakdown as source and drain are lightly 
doped NPN collector and substrate material. The collector 
current of Q18 biases current sources Q25 through Q30 and 
sets the supply current at nearly zero TC. 
Q1 9 furnishes a bias voltage, 5V above the negative supply, 
for the collectors of Q1 5, Q20 and Q22. The low impedance 
2V reference (Vbi in Figure 1) for the base of Q21 appears 
at the emitter of Q20 and has the correct TC to insure that 
Q23 never saturates. Should this occur, the low resistance 
of Q23 would cause premature LVqeo breakdown of Q21 . 
The input transistors, Q1 and Q2, are biased by Q13 and 
Q14 which have a breakdown voltage essentially equal to 
BVqbo by virtue of the high emitter impedance, R18 and 
R19, relative to the low dynamic impedance of D4. In a simi- 
lar way, Q18 and Q19 stand off essentially the full supply 
voltage. These devices have a high output impedance 
caused by series feedback and so hold the supply current 
nearly constant to prevent excessive power dissipation at 
high supply voltages. 




FIGURE 20. Complete Schematic of the LM143 



TL/H/7432-20 



312 



While the simple voltage clamping scheme, Q3 and Q4 in 
Figure 1, is adequate, it is prone to oscillation when built 
with high $ PNPs. The more elaborate scheme of Figure 20 
prevents instability. This clamping method is similar to that 
used in the LM108, but allows large differential inputs to 
exist with complete input overvoltage protection. Q9 and 
Q1 0, which withstand the high input common-mode voltage, 
have a BVcBO-tyP e breakdown due to the low impedance 
diodes seen from the base leads and the high impedance of 
Q1 and Q2 (enhanced by 100% series feedback) in the 
emitter leads. Input overvoltage protection also holds up un- 
der high-level transient input voltages. 
With a large negative-going step input, as could occur in the 
unity-gain voltage follower configuration, diode-connected 
Q6 turns "ON", protecting the emitter-base junction of Q2 
from zener breakdown and subsequent long-term fi degra- 
dation. At the same time, stray capacitance at the collector 
of Q2 is discharged by D2 through Q4 and Q12. This holds 
Q10 in a true BVcbo mode (emitter open-circuited) and 
clamps the voltage across Q2 to 3 Vbe- 
With a large positive-going step input, stray capacitance at 
the collectors of Q2 and Q12 is charged by the forward-bi- 
ased collector junction of Q2. As before, with D2 conduct- 
ing, Q10 is again in the BVcbo breakdown mode. Since the 
inverting input can be subject to the same transients, Q1 is 
afforded the same protection. 

Distributed capacitance associated with R10 and R11, to- 
gether with the collector-base capacitance of Q26, cause a 
high frequency transmission pole ( the "tail" pole< 2 )) which 
can degrade phase margin. This is avoided by adding a 
small lead capacitor, C1 , which provides an alternative low- 
impedance signal path, thus bypassing the tail pole. 
The offset null resistors, R21 and R23, are made larger than 
that strictly necessary to null the offset voltage. This reduc- 
es the transconductance of Q17 and, therefore, the noise 
gain of the active loads into R10 and R11. By this simple 
expedient, broadband input noise voltage is substantially re- 
duced. 

The voltage reference for the output stage (Vb2 in Figure 1) 
is realized by actively simulating a 4-diode stack. The volt- 
age across Q33, given by (1 + R8/R9) V B e. is about 3.5V. 
Biased at 400 juA from Q30, the circuit presents a low im- 



pedance, less than 50n, to the base of Q32. Since the TC 
of the reference is negative, Q34 is designed to always re- 
main out of saturation under worst-case conditions of high 
temperature and high output current. This avoids potential 
destructive breakdown of Q32. 

Current limiting for Q32 and Q34 is provided by diode-con- 
nected Q37 and resistor R12. When the voltage drop across 
R12 turns on Q37, it removes base drive from Q34. In a 
similar fashion, current limiting in the negative direction is 
initiated when the voltage drop across R13 causes Q38 to 
conduct. This current is limited in Q21 by R20 to about 1 
mA. When this occurs, base drive is removed from Q39. 
Although output short circuits to ground or either supply can 
be sustained indefinitely at supply voltages lower than 
±22V, short circuits should be of limited duration when op- 
erating at higher supply voltages. Units can be destroyed by 
any combination of high ambient temperature, high supply 
voltages, and high power dissipation which results in exces- 
sive die temperature. This is also true when driving low im- 
pedance or reactive loads or loads that can revert to low 
impedance; for example, the LM143 can drive most general 
purpose op amps outside of their maximum input voltage 
range, causing heavy current to flow and possibly destroy- 
ing both devices. 

Precautions should be taken to insure that the power sup- 
plies never become reversed in polarity — even under tran- 
sient conditions. With reverse voltage, the IC will conduct 
excessive current, fusing the internal aluminum intercon- 
nects. As with all IC op amps, voltage reversal between the 
power supplies will almost always result in a destroyed unit. 
Finally, caution should be exercised in high voltage applica- 
tions as electrical shock hazards are present. Since the 
negative supply is connected to the case, users may inad- 
vertently contact voltages equal to those across the power 
supplies. 

REFERENCES 

1. R. J. Widlar, "Super Gain Transistors for ICs", National 
Semiconductor TP-1 1 , March 1969. 

2. J. E. Solomon, "The Monolithic Op Amp: A Tutorial 
Study", IEEE Journal of Solid-State Circuits, Vol. SC-9, 
No. 6, December 1 974. 



ro 



313 



to 



FM Remote Speaker 
System 



National Semiconductor 
Application Note 146 



INTRODUCTION 

A high quality, noise free, wireless FM transmitter/receiver 
may be made using the LM566 VCO and LM565 PLL Detec- 
tor. The LM566 VCO is used to convert the program materi- 
al into FM format, which is then transformer coupled to stan- 
dard power lines. At the receiver end the material is detect- 
ed from the power lines and demodulated by the LM565. 
The important difference between this carrier system and 
others is its excellent quality and freedom from noise. 
Whereas the ordinary wireless intercom uses an AM carrier 
and exhibits a poor signal-to-noise ratio (S/N), the system 
described here uses an FM carrier for inherent freedom 
from noise and a PLL detection system for additional noise 
rejection. 

The complete system is suitable for high-quality transmis- 
sion of speech or music, and will operate from any AC outlet 
anywhere on a one-acre homesite. Frequency response is 
20-20,000 Hz and THD is under 1 / 2 % for speech and music 
program material. 

Transmission distance along a power line is at least ade- 
quate to include all outlets in and around a suburban home 
and yard. Whereas many carrier systems operate satisfacto- 
rily only when transmitter and receiver are plugged into the 
same side of the 120-240/V power service line, this system 
operates equally well with the receiver on either side of the 
line. 

The transmitter is plugged into the AC line at a radio or 
stereo system source. The signal for the transmitter is ideal- 
ly taken from the MONITOR or TAPE OUT connectors pro- 
vided on component system Hi-Fi receivers. If these outputs 
are not available, the signal could be taken from the main or 
extra speaker terminals, although the remote volume would 
then be under control of the local gain control. The carrier 
system receiver need only be plugged into the AC line at the 
remote listening location. The design includes a 2.5W power 
amplifier to drive a speaker directly. 

TRANSMITTER 

Two input terminals are provided so that both LEFT and 
RIGHT signals of a stereo set may be combined for mono 
transmission to a single remote speaker if desired. 
The input signal level is adjustable by Ri to prevent over- 
modulation of the carrier. Adding C2 across each input re- 
sistor R 7 and R$ improves the frequency response to 
20 kHz as shown in Figure 5. Although casual listening does 
not demand such performance, it could be desired in some 
circumstances. 

The VCO free-running frequency, or carrier frequency f c , de- 
termined by R 4 and C 4 is set at 200 kHz which is high 
enough to be effectively coupled to the AC line. VCO sensi- 
tivity under the selected bias conditions with V§ = 12V is 
about ±0.66 f c /V. For minimum distortion, the deviation 
should be limited to ±10%; thus maximum input at pin #5 




of the VCO is ± 0.15V peak. A reduction due to the sum- 
ming network brings the required input to about 0.2V rms for 
±10% modulation of f c , based on nominal output levels 
from stereo receivers. Input potentiometer R^ is provided to 
set the required level. The output at pin #3 of the LM566, 
being a frequency modulated square wave of approximately 
6V pk-pk amplitude, is amplified by a single transistor Q1 
and coupled to the AC line via the tuned transformer T-|. 
Because T-| is tuned to f c , it appears as a high impedance 
collector load, so Q-| need not have additional current limit- 
ing. The collector signal may be as nuch as 40-50V pk-pk. 
Coupling capacitor C 8 isolates the transfomer from the line 
at 60 Hz. 

A Voltage regulator provides necessary supply rejection for 
the VCO. The power transformer is sized for peak second- 
ary voltage somewhat below the regulator breakdown volt- 
age spec (35V) with a 125V line. 

RECEIVER 

The receiver amplifies, limits, and demodulates the received 
FM signal in the presence of line transient interference 
sometimes as high as several hundred volts peak. In addi- 
tion, it provides audio mute in the absence of carrier and 
2.5W output to a speaker. 

The carrier signal is capacitively coupled from the line to the 
tuned transformer T^ Loaded Q of the secondary tank T^ 
is decreased by shunt resistor R1 to enable acceptance of 
the ±10% modulated carrier, and to prevent excessive tank 
circuit ringing on noise spikes. The secondary of T-| is 
tapped to match the base input impedance of Q-ia- Recov- 
ered carrier at the secondary of T1 may be anywhere from 
0.2 to 45V p-p; the base of Q-ia may see pk-to-pk signal 
levels of from 12 mV to 2.6V. 

Q1A-Q1D operates as a two-stage limiter amplifier whose 
output is a symmetrical square wave of about 7V pk-pk with 
rise and fall times of 100 ns. 

The output of the limiting amplifier is applied directly to the 
mute peak detector, but is reduced to 1V pk-pk for driving 
the PLL detector. 

The PLL detector operates as a narrow band tracking filter 
which tracks the input signal and provides a low-distortion 
demodulated audio output with high S/N. The oscillator 
within the PLL is set to free-run at or near the carrier fre- 
quency of 200 kHz. The free-run frequency is f = 1 /(3.7 
R 16 C 13)- Since the PLL will lock to a carrier near its free-run 
frequency, an adjustment of Ri 6 is not strictly necessary; 
R16 could be fixed at 4700 or 5100H. Actually, the PLL with 
the indicated value of C-\ 1 can lock on a carrier within about 
± 40 kHz of its center frequency. However, rejection of im- 
pulse noise in difficult circumstances can be maximized by 
carefully adjusting f to the carrier frequency f c . Adding 



314 




LEFT 0-»VW-| 
760./C2L 



a> 



h 

TOKO 
RAN-10A6729EK 



CAPACITOR VALUES IN pF 
RESISTOR VALUES IN it 
tSELECT FOR CARRIER FREQ. 

f c C4 C 7 

200 kHz 82 1000 
100 kHz 160 3900 



FIGURE 1. Carrier System Transmitter 




CAPACITOR VALUES IN PF 
RESISTOR VALUES IN fi 
•SELECT FOR CARRIER FREO. 

200 kHz 1000 
100 kHz 3(00 



Q1A-O1E*LM30W 



C13 



TL/H/7442-2 



FIGURE 2. Carrier System Receiver 



315 



C-io = 100 pF will reduce the carrier level fed to the power 
amplifier. Even though the listener cannot hear the carrier, 
the audio amplifier could overload due to carrier signal pow- 
er. 

A mute circuit is included to quiet the receiver in the ab- 
sence of a carrier. Otherwise, when the transmitter is turned 
OFF, an excessive noise level would result as the PLL at- 
tempts to lock on noise. The mute detector consists of a 
voltage doubling peak detector DiQ 2 C 7 . The peak detector 
shunts the 1 -2 mA bias away from Q-| E without loading the 
limiter amplifier. When no carrier is present, the +4V line 
biases Qi E ON via R-| and R-n; and the audio signal is 
shorted to ground. When a carrier is present, the 7V square 
wave from the limiter amplifier is peak detected*, and the 
resultant negative output is integrated by R9C7, averaged by 
R10 across C 7 , and further integrated by RnC 6 . The result- 
ant output of about -4V subtracts from the +4V bias sup- 
ply, thus depriving Q-| E of base current. Peak detector inte- 
gration and averaging prevents noise spikes from deactivat- 



ing the mute in the absence of a carrier when the limiter 
amplifier output is a series of narrow 7V spikes. 
The LM380 supplies 2.5W of audio power to an 8ft load. 
Although this is adequate for casual listening in the kitchen 
or garage, for hi-fi listening, a larger amplifier may be direct. 

CONSTRUCTION 

PC board layout and stuffing diagrams are shown in Figures 
3 & 4. After the receiver board has been loaded and 
checked, the power transformer is mounted to the foil side 
of the board with a piece of fish-paper or electrical insulating 
cloth between board and transformer. Insulating washers of 
Yi6-% inch thickness can be used to advantage in holding 
the transformer away from the foil. The board is laid out so 
that the volume control potentiometer may be mounted on 
either side of the board depending on the desired mounting 
to a panel. 

The line coupling coils are available in production quantities 
from TOKO AMERICA, INC. 1250 Feehanville Drive, Mount 
Prospect, IL 60056. TEL: (312) 297-0070 




FIGURE 3. Carrier System Transmitter PC Layout and Loading Diagram (Not Full Scale) 




FIGURE 4. Carrier System Receiver PC Layout and Loading Diagram (Not Full Scale) 



TL/H/7442-4 



316 



ADJUSTMENT 

Adjustments are few and extremely simple. Transmitter car- 
rier frequency f c is fixed near 200 kHz by R4 and C4; the 
exact frequency is unimportant. T1 for both transmitter and 
receiver are tuned for maximum coupling to and from the 
AC line. Plug in both receiver and transmitter; no carrier 
modulation is necessary. Insure that both units are opera- 
tive. Observe or measure with an AC VTVM the waveform at 
T1 secondary in the receiver. Tune T1 of the transmitter for 
maximum observed signal amplitude. Then tune T-i of the 
receiver for a further maximum. Repeat on the transmitter, 
then the receiver. Tuning is now complete for the line cou- 
pling transformers and should not have to be repeated for 
either. If the receiver is located some distance from the 
transmitter in use, or on the opposite side of the 1 10-220V 
service line, a re-adjustment of the receiver T1 may be 
made to maximize rejection of SCR dimmer noise. The re- 
ceiver PLL free-running frequency is adjusted by R-|6- Set 
R16 near the center of its range. Rotate slowly in either 
direction until the PLL loses lock (evidenced by a sharp in- 
crease in noise and a distorted output). Note the position 
and then repeat, rotating in the other direction. Note the 
new position and then center R16 between the two noted 
positions. A fine adjustment may be made for minimum 
noise with an SCR dimmer in operation. The final adjust- 
ment is for modulation amplitude at the transmitter. Connect 
the audio signal to the transmitter input and adjust the input 
potentiometer R1 for a signal maximum of about 0.1 V rms at 
the input to the LM566. Adjustment is now complete for 
both transmitter and receiver and need not be repeated. 

A STEREO SYSTEM 

If full stereo or the two rear channels of a quadraphonic 
system are to be transmitted, both transmitter and receiver 
must be duplicated with differing carriers. Omit Rq and in- 
clude R7 & C2 on the transmitter if desired. Carriers could 
be set to 100 and 200 kHz for the two channels. Actually, 
they need only be set a distance of 40 kHz apart. 

PERFORMANCE 

Overall S/N is about 65 dB. Distortion is below about 1 / 4 % 
at low frequencies, and in actual program material it should 
not exceed 1 / 2 % as very little signal power occurs in music 
above about 1 kHz. 







Illl 






in 
















































l 
































































































' 
























1 






il 


















II 






nflk 














WITHOUT 


- in 














"C 


2 


ON XMTK 


IP 






























































III 








I 





10 



100 



1k 



10k 



100k 



FREQUENCY (Hz) 

TL/H/7442-5 

FIGURE 5. Overall System Performance 
Transmitter Input to Input of Receiver Power Amplifier 

The 2.5W audio amplifier provides an adequate sound level 
for casual listening. The LM380 has a fixed gain of 50. 
Therefore for a 2.5W max output, the input must be 89 mV. 
This is slightly less than the + 1 0% deviation level so we are 
within design requirements. Average program level would 
run a good 10 dB below this level at 28 mV input. 
Noise rejection is more than adequate to suppress line 
noise due to fluorescent lamps and normal line transients. 
Appliance motors on the same side of the 110-220V line 
may produce some noise. Even SCR dimmers produce only 
a background of impulse noise depending upon the relative 
location of receiver and SCR. Otherwise, performance is 
noise-free anywhere in the home. Satisfactory operation 
was observed in a factory building so long as transmitter 
and receiver were connected to the same phase of the 
three-phase service line. 

APPLICATIONS 

Additional applications other than home music systems are 
possible. Intercoms are one possibility, with a separate 
transmitter and receiver located at each station. A micro- 
phone can serve as the source material and the system can 
act as a monitor for a nursery room. Background music may 
be added to existing buildings without the expense of run- 
ning new wiring. 



317 



1.3V IC Flasher, Oscillator, 
Trigger or Alarm 



National Semiconductor 
Application Note 1 54 




INTRODUCTION 

Most linear integrated circuits are designed to operate with 
power supplies of 4.5 to 40V. Practically no battery/portable 
equipment is provided with indicator lights due to unaccept- 
able power drain. Even LEDs (solid state lamps) won't light 
from a 1 .5V battery, and drain the common 9V radio battery 
in a few hours. 

The LM3909 changes all this. Obtaining long life from a sin- 
gle 1 .5V cell, it opens a whole new area of applications for 
linear integrated circuits. Sufficient voltage for flashing a 
light emitting diode is generated with cell voltage down to 
1.1V. In such low duty cycle applications batteries will last 
for months to years of continuous operation. Such flasher 
circuits then become practical for marking location of flash- 
lights, emergency equipment, and boat mooring floats in the 
dark. 

The LM3909 is simple in design, easy to use, and includes 
extra resistors to minimize external circuitry and the size of 
the completed flasher or oscillator. 

CIRCUIT OPERATION 

The circuit below in Figure A is the LM3909 connected as 
the simplest type of oscillator. Ignoring the capacitor for a 
moment, and assuming 1.5V on pin 5, current will flow in the 



3k and 6k timing resistors through the emitter of Q-|. This 
current will be amplified by about 3 by Q2 and passed to the 
base of Q3. Q3 will then conduct, pulling down on the base 
of Q4 and hence the base of Q1 . This is a negative feedback 
since it will reduce timing resistor current and current to the 
power transistor's base until a balance is reached. This will 
occur with the collector of Q 3 at about 0.5V, the base of Q 4 
at about 1 V, and a very small voltage from pin 8 to ground. 
The difference between these two voltages is the base- 
emitter drop of Q1 and 2/3 the base-emitter drop of Q4 as 
set by the high resistance divider from its base to emitter. 
Note that negative feedback voltage is attenuated by at 
least 2 due to the divider of two 400H resistors. Now con- 
sidering the capacitor, its positive feedback is initially unity. 
Therefore the DC bias condition and the temporary excess 
positive feedback conditions are met and the circuit must 
oscillate. 

The waveform at pin 8 of the above oscillator is shown be- 
low. The waveform at pin 2, the power transistor collector, is 
almost a rectangle. It extends from a saturation voltage of 
0.1V or less to within about 0.1V of the supply voltage. The 
"on" period of course coincides with the negative pulses at 
pin 8. Other circuit voltages can easily be inferred from the 
two waveforms in Figure B. 




=■1 VOLT (DROP) 

JUST BEFORE Qj 

CONDUCTS 



FIGURE A 




TL/C/7213-2 



FIGURE B 



318 



The simplicity of LED and incandescent pilot lamp flashers 
is illustrated below in Figure 1. In the LED flasher, the 
LM3909 uses the single capacitor for both timing and volt- 
age boosting. 

The LM3909, although designed as a LED flasher, is ideal 
for other applications such as high current, trigger pulse for 
SCRs and "Triacs." The frequency of oscillation adjusts 
from under 1 Hz to hundreds of kHz. Waveshape can be set 
from pulses a few ju.s wide to approximately a square wave. 
Thus the LM3909 can perform as a sound effects generator, 
an audible alarm, or audible continuity checker. Finally it can 
be a radio (detector/amplifier), low power one-way inter- 
com, two-way telegraph set, or part of a "mini-strobe" light 
flashing up to 7 times per second. 
Operating with only a 1.5V battery as a supply gives the 
LM3909 several rather unique characteristics. First, no 
known connection can cause immediate destruction of the 
IC. Its internal feedback loop insures self-starting of properly 
loaded oscillator circuits. Experimenters can safely explore 
the possibilities of the LM3909 as an AC amplifier, one-shot, 
latch circuit, resistance limit detector, multi-tone oscillator, 
heat detector, or high frequency oscillator. 



NSL5027 



With the accent on the practical, a brief circuit description 
will be given followed by circuits in the following application 
areas: 

Flasher & Indicator Applications 

Audio & Oscillator Applications 

Trigger & Other Applications 
For those who want to modify or design their own circuits 
using the LM3909, application hints will be covered near the 
end of this note. 

CIRCUIT DESCRIPTION 

The circuit of Figure 2 again shows the typical 1 .5V LED 
flasher, but with the internal circuitry of the IC illustrated. 
The flasher achieves minimum power usage in two ways. 
Operated as above, the LED receives current only about 
1 % of the time. The rest of the time, all transistors but Q 4 
are off. The 20k resistor from Q4S emitter to supply-com- 
mon draws only about 50 juA The 300 juF capacitor is 
charged through the two 400ft resistors connected to pin 5 
and through the 3k resistor connected to pin 1 of the circuit. 



Incandescent Bulb Flasher 

















+6V 








8 |7 |6 






) 






5 


a 




LM3909 






1 




2 |3 

1 


4 






-;i+ 

400 mF 





Note: Nominal Flash Rate: 1 Hz. 



TL/C/7213-3 
Note: Flash Rate: 1 .5 Hz. 



FIGURE 1. Two Simple Flashers 

NSL5027 




FIGURE 2. Circuit Operation 



319 






Transistors Q-| through Q3 remain off until the capacitor be- 
comes charged to about 1V. This voltage is determined by 
the junction drop of Q 4 , its base-emitter voltage divider, and 
the junction drop of Q-|. When voltage at pin 1 becomes a 
volt more negative than that at pin 5 (supply positive termi- 
nal) Q-| begins to conduct. This then turns on Qg and Q3. 
The LM3909 then supplies a pulse of high current to the 
LED. Current amplification of Q2 and Q3 is between 200 and 
1000. Q 3 can handle over 100 mA and rapidly pulls pin 2 
close to supply common (pin 4). Since the capacitor is 
charged, its other terminal at pin 1 goes below the supply 
common. The voltage at the LED is then higher than battery 
voltage, and the 12fl resistor between pins 5 and 6 limits 
the LED current. 

Many of the other oscillator circuits work in a similar fashion. 
If voltage boost is not needed (with or without current limit- 
ing) loads can be hooked between pins 2 and 6 or pins 2 
and 5. 



APPLICATIONS: FLASHER & INDICATOR 

Differing uses and supply voltages will require adjustment of 
flashing rates. Often it is convenient to leave the capacitor 
the same value to minimize its size, or to fix the pulse ener- 
gy to the LED. First, the internal RC resistors can be used to 
obtain 3k, 6k, or 9k by hooking to or shorting the appropriate 
pins. Further adjustment methods are shown in the two 
parts of Figure 3 below. 

In Figure 3a, it can be seen that the internal RC resistors are 
shunted by an external 1 k between pins 8 and 4. This will 
give a little over 3 times the flashing rate of the typical 1 .5V 
flasher of Figure 1. 

The 3.9k resistor in Figure 3b connected from pin 1 to the 
6V supply raises voltage at the bottom of the 6k RC resistor. 
Charging current through that resistor is greatly reduced, 
bringing flashing rate down to about that of the 1 .5V circuit 
(1 Hz). As will be explained later, this biasing method also 
insures starting of oscillation even under unfavorable condi- 
tions. 




FIGURE 3a. Fast Blinker 




3.9k 



FIGURE 3b. 6 Volt Flasher 



320 



Two precautions are taken for circuit reliability. The added 
75ft series resistor for the LED keeps current peaks within 
safe limits for the diode and IC. Also, in operation above a 
3V supply, the electrolytic capacitor sees momentary volt- 
age reversals. It should be rated for periodic reversals of 
1.5V. 

A continuously appearing indicator light can also be pow- 
ered from a single 1 .5V cell as shown in Figure 4. Duty cycle 
and frequency of the current pulses to the LED are in- 
creased until the average energy supplied provides suffi- 
cient light. At frequencies above 2 kHz, even the fastest 
movement of the light source or the observer's head will not 
produce significant flicker. 

Since this indicator powering circuit uses the smallest ca- 
pacitor that will reliably provide full output voltage, its oper- 
ating frequency is well above the 2 kHz point. The indicator 
is not, however, intended as a long life system, since battery 
drain is about 1 2 mA. 



High frequency operation requires addition of two external 
resistors, typically of the same value. One, of course, shunts 
the high internal timing resistors. If only this one were used, 
the capacitor charging current would have to pass through 
the two 400ft resistors internally connected between pin 5 
and the collector of Q3. Oscillation at a slower rate and 
lower duty cycle than desired would occur, and oscillation 
might cease altogether before the battery was fully dis- 
charged. The second 68ft resistor shunting the two 400ft 
resistors eliminates these problems. 
The circuit in Figure 5 is a relaxation type oscillator flashing 
2 LEDs sequentially. With a 12 VDC supply, repetition rate is 
2.5 Hz. C2, the timing and storage capacitor, alternately 
charges through the upper LED and is discharged through 
the other by the IC's power transistor, Q3. 
If a red/green flasher is desired, the green LED should have 
its anode or plus lead toward pin 5 (like the lower LED). A 
shorter but higher voltage pulse is available in this position. 



NSLS057 




■^vW 



FIGURE 4. "Continuous" 1.5V Indicator 



.* .r 300 a. 




I J± cz 

1 ^400/iF 



TL/C/7213-8 



FIGURE 5. Alternating Flasher 

321 






Indication or monitoring of a high voltage power supply at a 
remote location can be done much more safely than with 
neon lamps. If the dropping resistor (43k as in Figure 6) is 
located at the source end, all other voltages on the line, the 
IC, and the LED will be limited to less than 7V, above 
ground. 



The timing capacitor is charged through the dropping resis- 
tor and the two 400fl collector loads between pins 2 and 5 
of the IC. When capacitor voltage reaches about 5V, there 
is enough voltage across the 1 k resistor (to pin 8) to turn on 
Qi , and hence trigger on the whole IC to discharge the ca- 
pacitor through the LED. 




TL/C/7213-9 



FIGURE 6. Safe, High Voltage Flasher 



OFF 




TL/C/7213-10 



FIGURE 7. "Mini-Strobe" Variable Flasher 



322 



There are many other LED applications and variations of 
circuits. A chart outlining operation of the circuit of Figure 6 
at various voltages appears on the LM3909 data sheet. Also 
shown are circuits for adjusting the flash rate, flashing 4 
LEDs in parallel, and details for building a blinking locator 
light into an ordinary flashlight. 

Incandescent bulbs can also be flashed, as already illustrat- 
ed in Figure 1. However, most such bulbs draw more than 
the 150 mA that the LM3909 can switch. The two following 
circuits therefore use an added power transistor rated at 1A 
or more. In each circuit, an NPN transistor is used, so the 
power transistor's base drive is obtained from the common 
or ground pin of the flasher IC. 

The 3V "mini-strobe" of Figure 7 may be used as a variable 
rate warning light or for advertising or special effects. The 
rate control is so wide range that it adjusts from no flashes 
at all to continuously on. Chosen for rapid response, the 
miniature 1 767 lamp can be flashed several times a second. 



A "mini-strobe" circuit was tested in a Lantern Flashlight 
with a large reflector. In a dark room, the flashes were al- 
most fast enough to stop a person's motion. As a toy, the 
fast setting can mimic the strobes at rock concerts or the 
flicker of old-time movies. 

Figure 8 below shows a higher power application such as 
would use an automotive storage battery for power. It pro- 
vides about a 1 Hz flash rate and powers a lamp drawing a 
nominal 600 mA. 

A particular advantage of this circuit is that it has only 2 
external wires and thus may be hooked up in either of the 
two ways shown below in Figure 9. Further, no circuit failure 
can cause a battery drain greater than that of the bulb itself, 
continuously lit. 

In the circuit of Figure 8, the 3300 juF capacitor performs a 
number of other functions. It makes the LM3909 immune to 
supply spikes, and provides the means of limiting the IC's 
supply voltage. Since the LM3909 can only operate with 




Q POSITIVE 



6 COM 



Tl/C/7213-11 



FIGURE 8. 12 Volt Flasher (2 Wire) 



*3> 

POSITIVE 



1 



2 WIRE 
FLASHER 



I 



Note: If flasher case insulated, it will 
operate in positive or negative 
ground systems. 




TL/C/7213-12 



FIGURE 9. 2 Wire Flasher Usage 



323 



7.5V or less on pin 5 (in this circuit) the 2000/1. 3k divider 
attached to pin 8 of the IC causes it to turn fully on at 7V or 
less on pin 5. Then the LM3909 discharges the timing ca- 
pacitor (its own supply voltage) to 4V or less, whereupon it 
turns off. The capacitor discharge current comes out of pin 
4 of the IC, turning on the NSD U01 transistor. It is the large 
size of the timing capacitor that allows it to store all the 
needed energy for turning on the power transistor. This in 
turn permits the whole flasher circuit to operate as a 2 wire 
device. 

Many other flasher possibilities exist. LED flash rate can be 
varied from to 20 Hz, or a number of LEDs may be flashed 
in parallel. With a 3V supply, yellow and green LEDs may be 
flashed. A 6V incandescent "emergency lantern" can be 
made and its PR-13 bulb may be made to give continuous 
light or flash by switch selection. This is a more reliable, 
longer lived system than a lantern with a second thermal 
flasher bulb. The NSL4944 Current Regulated LED makes 
possible flashing many LEDs in parallel or with high volt- 
ages without series resistors. 

APPLICATIONS: Audio & Oscillator 

Very economical continuity checkers, tone generators, and 
alarms may be made from the LM3909. No matching trans- 
former is needed because the 150 mA capability of the 
LM3909 output can drive many standard permanent magnet 
(transistor radio) loudspeakers directly. The 1.5V battery 
used in most applications is both lower in cost and longer 
lasting than the conventional 9V battery. 
In the continuity checker of Figure 10, a short, up to about 
100J1, across the test probes provides enough power for 
audible oscillation. By probing 2 values in quick succession, 
small differences such as between a short and 5fl can be 
detected by differences in tone. 

A novel use of this circuit is found in setting the timing of 
certain types of motorcyles. This is due to the difference in 
tone that can be heard from the tester depending whether 
there is a short or not across the low resistance primary of 
the 'cycle's ignition coil. In other words, the difference be- 



tween a 1 fl resistor and a 1 n inductor can be heard. Quick 
checks for shorts and opens in transformers and motors 
can therefore be made. 

Darkrooms, laundry rooms, laboratories, and cellar work- 
shops can often suffer damage from spills or water seepage 
ruining lumber, chemicals, fertilizer, bags of dry concrete, 
etc. The circuit of Figure 11 is safe on potentially damp 
floors since there is no connection to the power line. Fur- 
ther, its standby battery drain of 100 juA yields a battery life 
close to (or, according to some experiments, exceeding) 
shelf life. 

Without moisture, multivibrator transistor Q a is completely 
off, and its collector load (6.2k) provides enough current to 
hold pin 8 of the LM3909 above 0.75V where it cannot oscil- 
late. When the sense electrodes pass about 0.25 jwA, due to 
moisture, Q a starts turning on, and since Qb is already par- 
tially biased on, positive feedback now occurs. Q a and Qb 
are now an astable multivibrator which starts at about 1 Hz 
and oscillates faster as more leakage passes across the 
sense electrodes. 

This "multi" then acts as both an amplifier and a modulator. 
The pulse waveform at the collector of Q a varies the timing 
current through the 3.9k resistor to pin 8 of the LM3909 
resulting in a distinctively modulated tone output. 
The sensor should be part of the base of the box the alarm 
circuitry is packaged in. It consists of two electrodes six or 
eight inches long spaced about 1 / 8 inch apart. Two strips of 
stainless steel on insulators, or the appropriate zig-zag path 
cut in the copper cladding of a circuit board will work well. 
The bare circuit board between the copper sensing areas 
should be coated with warm wax so that moisture on the 
floor, not that absorbed by the board, will be detected. The 
circuit and sensor can be tested by just touching a damp 
finger to the electrode gap. 

Minimum cost, simplicity, and very low power drain are the 
aims of the Morse Code set of Figure 12. One oscillator 
simultaneously drives speakers at both sending and receiv- 




TL/C/7213-13 



FIGURE 10. "Buzz Box" Continuity and Coil Checker 



324 



SENSE ELECTRODES 



"LTLT 

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>470k>51k>6.2k>3.! 

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x 



470k 



"& °£H 



'3.9M 



• » 



IP- 




2sn 



QA & QB = 2N2484 



ALL CAPACITORS 1 jiF 

FIGURE 11. Water Seepage Alarm 



> 
ui 



TL/C/7213-14 



80 



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SLOW 
RC 



I FAST 
iRC 



vh 



20 k 
10k 



100ft 

■wv 



5 V *| F 390ft 

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2 



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-AVv ♦ 



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f-AW '» 




-400ft 



tLSV 



6.5 V mJl 



#22 WIRE 



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TL/C/7213-15 



FIGURE 12. Morse Code Set 



325 



ing ends. Calculations and actual use tests indicate life of a 
single alkaline penlight cell to be 3 months to over a year 
depending on usage. "Buzzer" type sets use two or more 
batteries with much shorter life. 

Commonly available, low cost 8ft speakers are effectively in 
series to better match LM3909 characteristics. The three 
wire system and parallel telegraph keys allow beginners and 
children to use the set without having to understand use of a 
"send-receive" switch. 

The two resistors are added to obtain a suitable average 
power output and electrically force the oscillator toward the 
desired 50% duty cycle. Acoustically, both speakers are op- 
erated at resonance (about 400 Hz in the prototype) for 
maximum pleasing tone with minimum power drain. Each of 
the two speaker enclosures has holes added to augment 
this resonance. For each different type or brand of speaker 
and size of box, hole and capacitor sizes will have to be 
determined by experiment for the most stable resonant tone 
over the expected battery voltage variation. 
Experiments with the above circuit led to development of 
circuit in Figure 13. It is optimized to oscillate at any acous- 
tic load frequency of resonance! With just a speaker, oscilla- 
tion occurs at the speaker cone "free-air" resonance. If the 
speaker is in an enclosure with a higher resonant frequency 
. . . this becomes the frequency at which the circuit oscil- 
lates. 

An educational audio demonstration device, or simply an 
enjoyable toy, has been fabricated as follows. A roughly cu- 
bical box of about 64 in. 3 was made with one end able to 



slide in and out like a piston. The box was stiffened with thin 
layers of pressed wood, etc. Minimum volume with the pis- 
ton in was about 10 in. 3 . Speaker, circuit, battery, and all 
were mounted on the sliding end with the speaker facing out 
through a 2% in. hole. A tube was provided (2 1 / 2 in. long, 5 / 16 
in. ID) to bleed air in and out as the piston was moved while 
not affecting resonant frequency. 

"Slide tones" can be generated, or a tune can be played by 
properly positioning the piston part and working the push 
button. Position and direction of the piston are rather intui- 
tive, so it is not difficult to play a reasonable semblance of a 
tune after a few tries. 

The 1 2ft resistor in series with pin 2 (output transistor Q3's 
collector) and the speaker, decouples voltages generated 
by the resonating speaker system from the low impedance 
switching action of Q3. The 100 juF feedback capacitor 
would normally set a low or even sub-audio oscillation fre- 
quency. Therefore, the major positive feedback voltage to 
pin 8 is the resonant motion generated voltage from the 
speaker voice coil. Therefore the LM3909 will continue to 
drive the speaker at the resonance with the highest com- 
bined amplitude and frequency. 

It can be seen already that the LM3909, having direct 
speaker drive and resonance following capability, can do 
things that are a lot less practical with older timer and uni- 
junction circuitry. Two final "sound effect" type of circuits 
are illustrated in Figure 14. 



N.o. 
PUSH BUTTON 




TL/C/7213-16 



FIGURE 13. Electronic "Trombone" 



326 



The siren of Figure 14a produces a rapidly rising wail upon 
pressing the button, and a slower "coasting down" upon 
release. If it is desirable to have the tone stop sometime 
after the button is released, an 1 8k resistor may be placed 
between pins 8 and 6 of the IC. The sound is then much like 
that of a motor driven siren. 

In this circuit, the oscillation must not be influenced by 
acoustic resonances. The 1 ju,F capacitor and 200fi resistor 
determine a pulse to the speaker that is wider than that for 
flashing LEDs, but much narrower than is used in the tuned 
systems of Figures 12 and 13. The repetition rate of speak- 
er pulses is determined by the 2.7k resistor, and the charge 
on the 500 ju.F capacitor. Discharging this capacitor with 



the pushbutton increases current in the 2.7k resistor caus- 
ing a rapid upshift in tone. 

The "whooper" of Figure 14b sounds somewhat like the 
electronic sirens used on city police cars, ambulances, and 
airport "crash wagons." The rapid modulation makes the 
tone seem louder for the same amount of power input. 
The tone generator is the same as in the previous siren. 
Instead of a pushbutton, a rapidly rising and falling modulat- 
ing voltage is generated by a second LM3909 and its asso- 
ciated 400 jaF capacitor. The 2N1304 transistor is used as a 
low voltage (germanium) diode. This transistor along with 
the large feedback resistor (5.1k to pin 8) forces the ramp 
generator LM3909 into an unusual mode of operation hav- 









25 SI SPKR 

rem- 



6V 



2.7k, 




C 



\0FF 

t-o V 




TL/C/7213-17 



FIGURE 14a. Fire Siren 



25 n 

rrrrx. 



^ 



1*iF 



•200fi 



[3.9k 



U |7 |6 



9k NC Rl V+ 

LM3909 
3k OUT NC V- 



2 3 



TONE GENERATOR 



TOP 
VIEW 



8j7_[6_ 



TOP 
5 VIEW 



9k NC Rl V+ 

LM3909 
3k OUT NC V- 



TIT 



±L4Q0jiF 
3V 



300 n 
I •— Vv\ ' 

>— K2N1304 

25Z 



RAMP GENERATOR 
FIGURE 14b. Whooper Siren 



TL/C/7213-18 



327 



ing longer "on" periods than "off" periods. This raises the 
average tone of the tone generator and makes the modula- 
tions seem more even. 

APPLICATIONS: Trigger & Other 

With its high pulse current capability, the LM3909 is a good 
pulse-transformer driver. Further, it uses fewer parts and 
operates more successfully from low voltage supplies than 
do the equivalent unijunction circuits. The "Triac" trigger of 
Figure 15 operates from a 5V logic supply and provides gate 
trigger pulses of up to 200 mA. 

With no gate input, or a TTL logic high input, the LM3909 is 
biased off since pin 1 is tied to V + . With a logic low at the 
gate in, the IC provides 10 jus pulses at about a 7 kC rate. A 
TTL gate loaded only by this circuit is assumed since other- 
wise worst-case voltage swing may be insufficient. This trig- 
ger is not of the "Synchronized Zero Crossing" type since 
the first trigger pulse after gating on could occur at any time. 
However, the repetition rate is such that after tne first cycle, 
a triac is triggered within 8V of zero with a resistive load and 
a 115 VAC line. 

The standard Sprague PC mounting transformer provides a 
2:1 current step-up, and suitable isolation between the low 
voltage circuitry and power lines up to 240 VAC. Resistor 
R g , which includes transformer winding resistance, can be 
as little as 3 or 4fl for high current triacs. Low current types 
may need excessive "holding" current with such low R g , so 
it may be raised to as much as 1 0011 with a sensitive gate 
triac. 

Oscillation of the LM3909 will start when the DC bias at pin 
8 is between 1.6 and 3.9V. In Figure 15, pin 8 is connected 
between the 10k input resistor and a 6k resistor to 
5V. With 3.8V in, pin 8 is at 4.5V so there is no oscillation. 
With 1V, or less, in, pin 8 is at 3.5V or below and oscillation 



occurs. From this example, it can be seen that other input 
resistors or bias dividers can be calculated to gate the 
LM3909 triac trigger from other logic levels. 
A useful electronic lab device is a precision square wave 
generator/calibrator. If the output is held at a few tenths 
percent of 1 V, peak-to-peak, it is useful in calibrating oscillo- 
scopes and adjusting 'scope probes. Many lower cost or 
battery-portable oscilloscopes do not have this feature built 
in. Also it is useful in checking gain and transient response 
of various amplifiers including "hi-fi" power amplifiers. 
Battery powered equipment is free from both the inconve- 
nience of a line cord, and from some of the noise and hum 
effects of equipment attached to the power line. Operation 
for over five hundred hours from a single flashlight "D" cell 
is the bonus provided by the circuit of Figure 16. The lowest 
reference voltage regulator available, the LM1 13, is used in 
conjunction with a current source, and the voltage boost 
characteristic of the LM3909. 

Output is a clean rectangular wave which can be adjusted to 
exactly a 1 V amplitude. A rectangular wave of approximate- 
ly 1.5 ms "on" and 5.5 ms "off" was chosen for circuit sim- 
plicity and low battery drain. Waveform clipping is virtually 
flat due to complete turn-off of the current switch Q2 and 
the typical "on" impedance of 0.2ft provided by the LM1 1 3. 
The 0.01% temperature coefficient of the LM113 at room 
temperature allows negligible drift of the waveform ampli- 
tude under laboratory conditions. Loading by a 'scope probe 
will also be insignificant. 

The circuit will work properly down to battery voltages of 
1.2V. This is because the 100 \xF electrolytic capacitor 
drives the emitter of Q2 below the supply minus terminal. At 
a battery voltage of 1.2V, the collector of Q2 can still swing 
more than 1 ,6V. Q1 uses the "off" periods of the LM3909 to 
insure that the 100 ju,F capacitor is charged to almost the 



+5VDC 



SPRAGUE 11 Z2003 




TL/C/7213-19 



FIGURE 15. Triac Trigger 



328 




> 
z 

01 



TL/C/7213-20 



FIGURE 16. 'Scope Calibrator 




TL/C/7213-21 



FIGURE 17. R.F. Oscillator 



entire battery voltage. Thus when the LM3909 turns on and 
pin 2 drives almost to the minus supply voltage, the negative 
side of the capacitor is driven 0.9 to 1 .2V below this termi- 
nal. Low battery voltage cannot lead to an undetected error 
in the 1V squarewave. This is because the waveform be- 
comes distorted rather than just decreasing in amplitude as 
battery voltage becomes too low. 

Taking advantage of the versatility and the indestructability 
of the LM3909 by a 1.5V battery, the IC can become an 
ideal teaching means, or experimental device for the young 
electronic hobbyist. As well as the circuits already present- 
ed, the LM3909 can be made to work as amplifier, radio, 
and even logic type circuits. The ideas of negative and posi- 
tive feedback can be presented. The circuits presented in 
Figures 17 through 21 are intended as illustrations or dem- 
onstrations of circuitry concepts such as would be used in 
an experimenter's kit. They are not meant to be used as 
parts of finished commercial products with specific perform- 



ance specifications. In other words, working circuits have 
been breadboarded, but no measurements of performance 
such as frequency range and distortion have been attempt- 
ed. 

Both tuned circuits of Figures 17 and 18 use standard AM 
radio ferrite antenna coils (loopsticks) with a tap 40% of the 
turns up from one end. The oscillator works up to 800 kHz 
or so, and the radio tunes the regular AM broadcast band. 
Both also use standard (360 pF) AM radio tuning capacitors. 
The oscillator has the normal capacitive positive feedback 
used with LM3909 circuits, but with frequency determined 
by the tuned circuit loading the output circuit. Detailed oper- 
ating descriptions of these experimenter's circuits will not 
be attempted in order to keep down the length of this note. 
Near the end, a discussion of the IC's general theory of 
operation will be given, which should help in understanding 
the individual circuits. 



329 



In the radio circuit of Figure 18, the LM3909 acts as a detec- 
tor amplifier. It does not oscillate because there is no posi- 
tive feedback path from pin 2 to pin 8. The tuning ability is 
only as good as simple "crystal set," but a local radio sta- 
tion can provide listenable volume with an efficient 6 inch 
loudspeaker. Extremely low power drain allows a month of 
continuous radio operation from a single "D" flashlight cell. 
Antennae for the radio circuit can be short (10 to 20 feet) 
and connected directly to the end of the antenna coil as 
illustrated. Longer antennae (30 to 100 feet) work better if 
attached to the previously mentioned tap on the coil . . . also 
illustrated. 

The following two circuits are examples of logic or computer 
type functions. They use 3V power supplies (2 cells) be- 
cause the LM3909 was designed not to have any stable or 
"latching" states with a 1.5V supply. 



Switches on both the above circuits are momentary types. 
In each case a small charge or impulse affects the circuit's 
state. The circuit of Figure 19 switches to and holds its con- 
dition whenever the switch changes sides, even if contact is 
made only very briefly. The circuit of Figure 20 delivers 
about a 1 / 2 second flash from the LED every time its push- 
button makes contact, whether briefly or for a much longer 
period of time. Such circuits are used with keyboards, limit 
switches, and other mechanical contacts that must feed 
data into electronic digital systems. 
By again leaving out the positive feedback capacitor, the 
LM3909 can become a low power amplifier. This little audio 
amplifier can be used as a one-way intercom or for "listen- 
ing in" on various situations. Operating current is only 12 to 
1 5 mA. It can hear fairly faint sounds, and someone speak- 
ing directly into the microphone generates a full 1 .4V peak- 
to-peak at the loudspeaker. 




nmn_ 



f 




^O.ImF 



TL/C/7213-22 



FIGURE 18. Radio 



"ON" s- 0.3 VOLTS 
"OFF" a 2.9 VOLTS 
O 




TL/C/7213-23 



FIGURE 19. Latch Circuit 



330 




TL/C/7213-24 



FIGURE 20. Indicating One-Shot 



|3.2fiSPKR 
AS MIC. 



3.2n:15k 



50 FT 
TWISTED 



rrrrt. 



.mm 



40 n 

SPKR. 




: 0.001 mF 



: o.i AiF 



TL/C/7213-25 



FIGURE 21. Mini-Power Amplifier 



331 



APPLICATION HINTS 

With 1 .5V supplies, certain problems can occur to stop os- 
cillation or flashing. Due to the way gain is achieved and the 
type of feedback, too heavy a load may stop an LM3909 
from oscillating. 20H of pure resistive load will sometimes 
do it. Strangely enough, lamp filaments, probably because 
of some inductance, don't seem to follow this rule. Also in 
flasher circuits, an LED with leakage or conductivity be- 
tween 0.9 and 1 .2V will stop the LM3909. Maybe 1 % of 
LEDs will have this defect because they are not often tested 
for it. 

Greater frequency stability was not one of the design aims 
of the LM3909. In LED flasher circuits it is better than might 
be expected because the negative temperature coefficient 
of the LED partially compensates the IC. We planned it this 
way. Simple oscillators, without the LED, are uncompensat- 
ed for temperature. This is due to using 1 2 / 3 of a silicon 
junction drop as the on-off trip point and the use of the 
integrated timing resistors with their positive temperature 
coefficient. Further, most capacitors of 1 \iF or over, shown 
in the circuits, will usually be electrolytics for size reasons. 
These, however, are not particularly stable with temperature 
and their initial tolerances vary greatly with type of capaci- 
tor. 

In most of the oscillator circuits, frequency is also propor- 
tional to battery voltage. This must be considered when 
starting with a completely unused cell at 1.54V or so and 
deciding what the "end-of-life" voltage is to be. This can be 
in the range of 1.1 to 0.9V, a drastic change. It helps to 
remember how bright flashlights are with a fresh set of bat- 
teries, and how dim they are when the batteries are finally 
changed. 

Flashers and tone generators for alarms are not, however, 
demanding for stability. Flash rate changes of 50% or tone 
shifts of 1 / 2 an octave are not particularly annoying or even 
too noticeable. 

One interesting point is that the low operating power of 
most of the circuits presented allows them to be powered by 
solar cells as well as regular batteries. In bright sunlight, 3 to 
4 cells in series will be needed. In dimmer light, 4 to 6 cells 
will do the job. Current from cells way under an inch in area 



generally will be sufficient, but circuits drawing a high pulse 
current (such as SCR triggers) will need a surge storage 
capacitor across the solar cell array. 
The LM3909 was designed to be inherently self-starting as 
an oscillator, and LED flasher circuits are, at any voltage, 
because the load is nonlinear. A load with sufficient self 
inductance will always self-start, although possibly at a high- 
er than expected frequency. There is an exception for large- 
ly resistive loads on an oscillator operating with a supply 
larger than 2 or 2.5V. A stable state exists with Q3 turned 
completely "on" and the timing resistors from pin 8 to the 
supply minus still drawing current. A reliable solution is to 
bias pin 8 (for instance with a resistor to V + ) so that its DC 
voltage is one half V less than half the supply voltage. 
The duty cycle of the basic LED flasher is inherently low 
since the timing capacitor is also driving the very low LED 
"on" impedance. For other oscillators the "on" duty cycle 
can be stretched by adding resistance in series with the 
timing capacitor. Additionally, nonlinear resistance can be 
used as timing resistance. (See Figure 14b) 

CONCLUSION 

Applications covered in this note range in use from toys to 
the laboratory, and in frequency from DC to RF. The 
LM3909 can be used to amuse, teach, or even upon occa- 
sion to save a life. As a practical cost consideration the 
LM3909 IC can often replace a circuit having a number of 
transistors, associated parts, and high assembly cost. 
Further, the LM3909 demonstrates the practicality of very 
low voltage electronic circuits. They can work at high effi- 
ciencies if ingenuity is used to design around transistor junc- 
tion drops. In such circuits stresses on parts are so low that 
extremely long life can be predicted. Often transistors, ca- 
pacitors, etc. that would be rejects at higher voltages can be 
used. Voltage dividers, protective diodes, etc. often needed 
at higher voltages can be left out of designs. Power drains 
are so low that circuits can be made that will last months to 
years on a single cell. 

A single cell is more reliable and has a higher energy densi- 
ty then multiple cells. This is due to lack of cell interconnec- 
tions and insulation as well as elimination of packaging to 
hold multiple cells in place. 



332 



Specifying A/D and D/A 
Converters 



National Semiconductor 
Application Note 156 




The specification or selection of analog-to-digital (A/D) or 
digital-to-analog (D/A) converters can be a chancey thing 
unless the specifications are understood by the person 
making the selection. Of course, you know you want an ac- 
curate converter of specific resolution; but how do you en- 
sure that you get what you want? For example, 1 2 switches, 
1 2 arbitrarily valued resistors, and a reference will produce a 
12-bit DAC exhibiting 12 quantum steps of output voltage. In 
all probability, the user wants something better than the ex- 
pected performance of such a DAC. Specifying a 12-bit 
DAC or an ADC must be made with a full understanding of 
accuracy, linearity, differential linearity, monotonicity, scale, 
gain, offset, and hysteresis errors. 

This note explains the meanings of and the relationships 
between the various specifications encountered in A/D and 
D/A converter descriptions. It is intended that the meanings 
be presented in the simplest and clearest practical terms. 
Included are transfer curves showing the several types of 
errors discussed. Timing and control signals and several bi- 
nary codes are described as they relate to A/D and D/A 
converters. 

MEANING OF PERFORMANCE SPECS 
Resolution describes the smallest standard incremental 
change in output voltage of a DAC or the amount of input 
voltage change required to increment the output of an ADC 
between one code change and the next adjacent code 
change. A converter with n switches can resolve 1 part in 
2 n . The least significant increment is then 2~ n , or one least 
significant bit (LSB). In contrast, the most significant bit 
(MSB) carries a weight of 2 _1 . Resolution applies to DACs 
and ADCs, and may be expressed in percent of full scale or 
in binary bits. For example, an ADC with 12-bit resolution 
could resolve 1 part in 2^2 (1 part in 4096) or 0.0244% of 
full scale. A converter with 10V full scale could resolve a 
2.44mV input change. Likewise, a 12-bit DAC would exhibit 
an output voltage change of 0.0244% of full scale when the 
binary input code is incremented one binary bit (1 LSB). 
Resolution is a design parameter rather than a performance 
specification; it says nothing about accuracy or linearity. 



Accuracy is sometimes considered to be a non-specific 
term when applied to D/A or A/D converters. A linearity 
spec is generally considered as more descriptive. An accu- 
racy specification describes the worst case deviation of the 
DAC output voltage from a straight line drawn between zero 
and full scale; it includes all errors. A 12-bit DAC could not 
have a conversion accuracy better than ± 1 / 2 LSB or ± 1 
part in 2 12 + 1 (±0.0122% of full scale) due to finite resolu- 
tion. This would be the case in Figure 1 if there were no 
errors. Actually, +0.0122% FS represents a deviation from 
100% accuracy; therefore accuracy should be specified as 
99.9878%. However, convention would dictate 0.0122% as 
being an accuracy spec rather than an inaccuracy (toler- 
ance or error) spec. 

Accuracy as applied to an ADC would describe the differ- 
ence between the actual input voltage and the full-scale 
weighted equivalent of the binary output code; included are 
quantizing and all other errors. If a 1 2-bit ADC is stated to be 
±1 LSB accurate, this is equivalent to ±0.0245% or twice 
the minimum possible quantizing error of 0.0122%. An ac- 
curacy spec describes the maximum sum of all errors in- 
cluding quantizing error, but is rarely provided on data 
sheets as the several errors are listed separately. 




000 001 010 011 100 101 110 111 
DIGITAL CODE 

TL/H/5612-1 

FIGURE 1. Linear DAC Transfer Curve Showing 
Minimum Resolution Error and Best Possible Accuracy 



333 



Quantizing Error is the maximum deviation from a straight 
line transfer function of a perfect ADC. As, by its very na- 
ture, an ADC quantizes the analog input into a finite number 
of output codes, only an infinite resolution ADC would exhib- 
it zero quantizing error. A perfect ADC, suitably offset 1 / 2 
LSB at zero scale as shown in Figure 2, exhibits only ± 1 / 2 

LSB maximum output error. If not offset, the error will be ~ J 

LSB as shown in Figure 3. For example, a perfect 12-bit 
ADC will show a ± 1 / 2 LSB error of ±0.0122% while the 
quantizing error of an 8-bit ADC is ± 1 / 2 part in 28 or 
±0.195% of full scale. Quantizing error is not strictly appli- 
cable to a DAC; the equivalent effect is more properly a 
resolution error. 




ANALOG INPUT 



FIGURE 2. ADC Transfer Curve, 1 / 2 LSB Offset at Zero 



in 

110 










/ Y 


101 








, 




§ 10 ° 








/ / 




< 011 












5 010 
001 


<-. 


A 









t 

1 LSB 



FS 



ANALOG INPUT 

TL/H/5612-2 

FIGURE 3. ADC Transfer Curve, No Offset 

Scale Error (full scale error) is the departure from design 
output voltage of a DAC for a given input code, usually full- 
scale code. (See Figure 4.) In an ADC it is the departure of 
actual input voltage from design input voltage for a full-scale 
output code. Scale errors can be caused by errors in refer- 
ence voltage, ladder resistor values, or amplifier gain, et. al. 
(See Temperature Coefficient.) Scale errors may be cor- 
rected by adjusting output amplifier gain or reference volt- 
age. If the transfer curve resembles that of Figure 7, a scale 
adjustment at 3 / 4 scale could improve the overall ± accura- 
cy compared to an adjustment at full scale. 




000 001 010 on too 101 110 111 
DIGITAL CODE 

FIGURE 4. Linear, 1 LSB Scale Error 



TL/H/5612-3 



Gain Error is essentially the same as scale error for an 
ADC. In the case of a DAC with current and voltage mode 
outputs, the current output could be to scale while the volt- 
age output could exhibit a gain error. The amplifier feedback 
resistors would be trimmed to correct the gain error. 
Offset Error (zero error) is the output voltage of a DAC with 
zero code input, or it is the required mean value of input 
voltage of an ADC to set zero code out. (See Figure 5.) 
Offset error is usually caused by amplifier or comparator 
input offset voltage or current; it can usually be trimmed to 
zero with an offset zero adjust potentiometer external to the 
DAC or ADC. Offset error may be expressed in % FS or in 
fractional LSB. 




y, LSJ__ 000 J M1 01| > <"' 10 ° "> 1 "° in 

OFFSET 

DIGITAL CODE 

TL/H/5612-4 

FIGURE 5. DAC Transfer Curve, 1 / 2 LSB Offset at Zero 

Hysteresis Error in an ADC causes the voltage at which a 
code transition occurs to be dependent upon the direction 
from which the transition is approached. This is usually 
caused by hysteresis in the comparator inside an ADC. Ex- 
cessive hysteresis may be reduced by design; however, 
some slight hysteresis is inevitable and may be objectiona- 
ble in converters if hysteresis approaches 1 / 2 LSB. 
Linearity, or, more accurately, non-linearity specifications 
describe the departure from a linear transfer curve for either 
an ADC or a DAC. Linearity error does not include quantiz- 
ing, zero, or scale errors. Thus, a specification of ± 1 / 2 LSB 



334 



linearity implies error in addition to the inherent ± 1 / 2 LSB 
quantizing or resolution error. In reference to Figure 2, 
showing no errors other than quantizing error, a linearity 
error allows for one or more of the steps being greater or 
less than the ideal shown. 

Figure 6 shows a 3-bit DAC transfer curve with no more 
than ± 1 / 2 LSB non-linearity, yet one step shown is of zero 
amplitude. This is within the specification, as the maximum 
deviation from the ideal straight line is ±1 LSB ( 1 / 2 LSB 
resolution error plus 1 / 2 LSB non-linearity). With any linearity 
error, there is a differential non-linearity (see below). A ± 1 / 2 
LSB linearity spec guarantees monotonicity (see below) and 
<. ± 1 LSB differential non-linearity (see below). In the ex- 
ample of Figure 6, the code transition from 1 00 to 1 01 is the 
worst possible non-linearity, being the transition from 1 LSB 
high at code 100 to 1 LSB low at 1 10. Any fractional non-lin- 
earity beyond + 1 / 2 LSB will allow for a non-monotonic trans- 
fer curve. Figure 7 shows a typical non-linear curve; non-lin- 
earity is 1 1 / 4 LSB yet the curve is smooth and monotonic. 




mm 001 010 011 100 101 110 111 
DIGITAL C00E 



FIGURE 6. ± 1 / 2 LSB Non-Linearity (Implies 1 LSB 

Possible Error), 1 LSB Differential Non-Linearity 

(Implies Monotonicity) 




000 001 010 011 100 101 110 111 
DIGITAL CODE 

TL/H/5612-5 

FIGURE 7. 1 1 / 4 LSB Non-Linear, 
1 / 2 LSB Differential Non-Linearity 

Linearity specs refer to either ADCs or to DACs, and do not 
include quantizing, gain, offset, or scale errors. Linearity er- 
rors are of prime importance along with differential linearity 
in either ADC or DAC specs, as all other errors (except 
quantizing, and temperature and long-term drifts) may be 
adjusted to zero. Linearity errors may be expressed in % FS 
or fractional LSB. 



Differential Non-Linearity indicates the difference be- 
tween actual analog voltage change and the ideal (1 LSB) 
voltage change at any code change of a DAC. For example, 
a DAC with a 1 .5 LSB step at a code change would be said 
to exhibit 1 / 2 LSB differential non-linearity (see Figures 6 and 
7). Differential non-linearity may be expressed in fractional 
bits or in % FS. 

Differential linearity specs are just as important as linearity 
specs because the apparent quality of a converter curve 
can be significantly affected by differential non-linearity 
even though the linearity spec is good. Figure 6 shows a 
curve with a ± 1 / 2 LSB linearity and ± 1 LSB differential non- 
linearity while Figure 7 shows a curve with + 1 1 / 4 LSB linear- 
ity and ± 1 / 2 LSB differential non-linearity. In many user ap- 
plications, the curve of Figure 7 would be preferred over that 
of Figure 6 because the curve is smoother. The differential 
non-linearity spec describes the smoothness of a curve; 
therefore it is of great importance to the user. A gross exam- 
ple of differential non-linearity is shown in Figure 8 where 
the linearity spec is ±1 LSB and the differential linearity 
spec is ± 2 LSB. The effect is to allow a transfer curve with 
grossly degraded resolution; the normal 8-step curve is re- 
duced to 3 steps in Figure 8. Similarly, a 16-step curve (4-bit 
converter) with only 2 LSB differential non-linearity could be 
reduced to 6 steps (a 2.6-bit converter?). The real message 
is, "Beware of the specs." Do not ignore or omit differential 
linearity characteristics on a converter unless the linearity 
spec is tight enough to guarantee the desired differential 
linearity. As this characteristic is impractical to measure on 
a production basis, it is rarely, if ever, specified, and linearity 
is the primary specified parameter. Differential non-linearity 
can always be as much as twice the non-linearity, but no 
more. 



2LSBDIFF 
NONLINEAR 



2 LSB OIFF 
NON-LINEAR 



000 001 010 011 100 101 110 111 
DIGITAL CODE 



TL/H/5612-6 



FIGURE 8. ± 1 LSB Linear, 
+ 2 LSB Differential Non-Linear 

Monotonicity. A monotonic curve has no change in sign of 
the slope; thus all incremental elements of a monotonically 
increasing curve will have positive or zero, but never nega- 
tive slope. The converse is true for decreasing curves. The 
transfer curve of a monotonic DAC will contain steps of only 
positive or zero height, and no negative steps. Thus a 
smooth line connecting all output voltage points will contain 
no peaks or dips. The transfer function of a monotonic ADC 
will provide no decreasing output code for increasing input 
voltage. 



335 



Figure 9 shows a non-monotonic DAC transfer curve. For 
the curve to be non-monotonic, the linearity error must ex- 
ceed ± 1 / 2 LSB no matter by how little. The greater the lin- 
earity error, the more significant the negative step might be. 
A non-monotonic curve may not be a special disadvantage 
is some systems; however, it is a disaster in closed-loop 
servo systems of any type (including a DAC-controlled 
ADC). A + 1 / 2 LSB maximum linearity spec on an n-bit con- 
verter guarantees monotonicity to n bits. A converter exhib- 
iting more than + y 2 LSB non-linearity may be monotonic, 
but is not necessarily monotonic. For example, a 1 2-bit DAC 
with + 1 / 2 bit linearity to 10 bits (not ± 1 / 2 LSB) will be mono- 
tonic at 1 bits but may or may not be monotonic at 1 2 bits 
unless tested and guaranteed to be 12-bit monotonic. 




000 001 010 011 100 101 110 111 
DIGITAL CODE 

TL/H/5612-7 

FIGURE 9. Non-Monotonic 
(Must be > ± 1 / 2 LSB Non-Linear) 

Settling Time is the elapsed time after a code transition for 
DAC output to reach final value within specified limits, usual- 
ly + 1 / 2 LSB. (See also Conversion Rate below.) Settling 
time is often listed along with a slew rate specification; if so, 
it may not include slew time. If no slew rate spec is included, 
the settling time spec must be expected to include slew 
time. Settling time is usually summed with slew time to ob- 
tain total elapsed time for the output to settle to final value. 
Figure 10 delineates that part of the total elapsed time 
which is considered to be slew and that part which is settling 
time. It is apparent from this figure that the total time is 
greater for a major than for a minor code change due to 
amplifier slew limitations, but settling time may also be dif- 
ferent depending upon amplifier overload recovery charac- 
teristics. 

Slew Rate is an inherent limitation of the output amplifier in 
a DAC which limits the rate of change of output voltage after 
code transitions. Slew rate is usually anywhere from 0.2 to 
several hundred volts/jus. Delay in reaching final value of 
DAC output voltage is the sum of slew time and settling time 
as shown in Figure 10. 

Overshoot and Glitches occur whenever a code transition 
occurs in a DAC. There are two causes. The current output 
of a DAC contains switching glitches due to possible asyn- 
chronous switching of the bit currents (expected to be worst 
at half-scale transition when all bits are switched). These 



2V/DIV 






2WDIV 


- 




-j 


SETTLING TIME 










DAC OUTPUT 










[^ 


1 1 
CONTROL LOG C 








I/ 




















1 




















a 




















— - SLEW TIME 













(a) Full-Scale Step 





0m 


//OIV 




1 1 1 1 
CONTROL LOGIC 






1 












1 




OAC OUTPUT 








f 


















h 


SETTLING TIME 

1 










































'! 




WDIV 







TL/H/5612-8 



(b) 1 LSB Step 



FIGURE 10. DAC Slew and Settling Time 

glitches are normally of extremely short duration but could 
be of 1 / 2 scale amplitude. The current switching glitches are 
generally somewhat attenuated at the voltage output of the 
DAC because the output amplifier is unable to slew at a very 
high rate; they are, however, partially coupled around the 
amplifier via the amplifier feedback network and seen at the 
output. The output amplifier introduces overshoot and some 
non-critically damped ringing which may be minimized but 
not entirely eliminated except at the expense of slew rate 
and settling time. 

Temperature Coefficient of the various components of a 
DAC or ADC can produce or increase any of the several 
errors as the operating temperature varies. Zero scale off- 
set error can change due to the TC of the amplifier and 
comparator input offset voltages and currents. Scale error 
can occur due to shifts in the reference, changes in ladder 
resistance or non-compensating RC product shifts in dual- 
slope ADCs, changes in beta or reference current in current 
switches, changes in amplifier bias current, or drift in amplifi- 
er gain-set resistors. Linearity and monotonicity of the DAC 
can be affected by differential temperature drifts of the lad- 
der resistors and switches. Overshoot, settling time, and 
slew rate can be affected by temperature due to internal 
change in amplifier gain and bandwidth. In short, every 
specification except resolution and quantizing error can be 
affected by temperature changes. 



336 



Long-Term Drift, due mainly to resistor and semiconductor 
aging can affect all those characteristics which temperature 
change can affect. Characteristics most commonly affected 
are linearity, monotonicity, scale, and offset. Scale change 
due to reference aging is usually the most important 
change. 

Supply Rejection relates to the ability of a DAC or ADC to 
maintain scale, offset, TC, slew rate, and linearity when the 
supply voltage is varied. The reference must, of course, re- 
main constant unless considering a multiplying DAC. Most 
affected are current sources (affecting linearity and scale) 
and amplifiers or comparators (affecting offset and slew 
rate). Supply rejection is usually specified only as a % FS 
change at or near full scale at 25°C. 
Conversion Rate is the speed at which an ADC or DAC can 
make repetitive data conversions. It is affected by propaga- 
tion delay in counting circuits, ladder switches and compafa- 
tors; ladder RC and amplifier settling times; amplifier and 
comparator slew rates; and integrating time of dual-slope 
converters. Conversion rate is specified as a number of con- 
versions per second, or conversion time is specified as a 
number of microseconds to complete one conversion (in- 
cluding the effects of settling time). Sometimes, conversion 
rate is specified for less than full resolution, thus showing a 
misleading (high) rate. 

Clock Rate is the minimum or maximum pulse rate at which 
ADC counters may be driven. There is a fixed relationship 
between the minimum conversion rate and the clock rate 
depending upon the converter accuracy and type. All fac- 
tors which affect conversion rate of an ADC limit the clock 
rate. 

Input Impedance of an ADC describes the load placed on 
the analog source. 

Output Drive Capability describes the digital load driving 
capability of an ADC or the analog load driving capacity of a 
DAC; it is usually given as a current level or a voltage output 
into a given load. 

CODES 

Several types of DAC input or ADC output codes are in 
common use. Each has its advantages depending upon the 
system interfacing the converter. Most codes are binary in 
form; each is described and compared below. 
Natural Binary (or simply Binary) is the usual 2 n code with 
2, 4, 8, 16, . . . , 2 n progression. An input or output high or 
"1" is considered a signal, whereas a "0" is considered an 
absence of signal. This is a positive true binary signal. Zero 
scale is then all "zeros" while full scale is all "ones." 
Complementary Binary (or Inverted Binary) is the negative 
true binary system. It is identical to the binary code except 
that all binary bits are inverted. Thus, zero scale is all 
"ones" while full scale is all "zeros." 
Binary Coded Decimal (BCD) is the representation of deci- 
mal numbers in binary form. It is useful in ADC systems 
intended to drive decimal displays. Its advantage over deci- 
mal is that only 4 lines are needed to represent 10 digits. 
The disadvantage of coding DACs or ADCs in BCD is that a 
full 4 bits could represent 16 digits while only 10 are repre- 
sented in BCD. The full-scale resolution of a BCD coded 
system is less than that of a binary coded system. For 



example, a 12-bit BCD system has a resolution of only 1 
part in 1 000 compared to 1 part in 4096 for a binary system. 
This represents a loss in resolution of over 4:1. 
Offset Binary is a natural binary code except that it is offset 
(usually V2 scale) in order to represent negative and positive 
values. Maximum negative scale is represented to be all 
"zeros" while maximum positive scale is represented as all 
"ones." Zero scale (actually center scale) is then represent- 
ed as a leading "one" and all remaining "zeros." The com- 
parison with binary is shown in Figure 1 1. 
Two's Complement Binary is an alternate and more widely 
used code to represent negative values. With this code, 
zero and positive values are represented as in natural binary 
while all negative values are represented in a twos comple- 
ment form. That is, the twos complement of a number repre- 
sents a negative value so that interface to a computer or 
microprocessor is simplified. The twos complement is 
formed by complementing each bit and then adding a 1 ; any 
overflow is neglected. The decimal number -8 is represent- 
ed in twos complement as follows: start with binary code of 
decimal 8 (off scale for ± representation in 4 bits so not a 
valid code in the ± scale of 4 bits) which is 1000; comple- 
ment it to 01 1 1 ; add 0001 to get 1000. The comparison with 
offset binary is shown in Figure 11. Note that the offset 
binary representation of the + scale differs from the twos 
complement representation only in that the MSB is comple- 
mented. The conversion from offset binary to twos comple- 
ment only requires that the MSB be inverted. 




ANALOG SCALE 



(a) Zero to + Full-Scale 



011 Oil 


111 


F~ 


010 010 


110 


r* 


001 001 


101 


jJ 


101 111 


100 
011 


-% -Yi -% 0/f 




IIS 110 


010 


jH 


111 101 


001 


H 


100 

t t 


000 
U 


j 

FFSET BINARY 


[ TWOS COMPLEMENT BINARY 


SIGN + MAGNITUDE 




(b) ± Full-Scale 




FIGI 


JRE 11. ADC Codes 



TL/H/5612-9 



337 



Sign Plus Magnitude coding contains polarity information 
in the MSB (MSB = 1 indicates a negative sign); all other 
bits represent magnitude only. This code is compared to 
offset binary and twos complement in Figure 1 1. Note that 
one code is used up in providing a double code for zero. 
Sign plus magnitude code is used in certain instrument and 
audio systems; its advantage is that only one bit need be 
changed for small scale changes in the vicinity of zero, and 
plus and minus scales are symmetrical. A DVM might be an 
example of its use. 

CONTROL 

Each ADC must accept and/or provide digital control sig- 
nals telling it and/or the external system what to do and 
when to do it. Control signals should be compatible with one 
or more types of logic in common use. Control signal timing 
must be such that the converter or connected system will 
accept the signals. Common control signals are listed be- 
low. 

Start Conversion (SC) is a digital signal to an ADC which 
initiates a single conversion cycle. Typically, an SC signal 
must be present at the fall (or rise) of the clock waveform to 
initiate the cycle. A DAC needs no SC signal; however, such 
could be provided to gate digital inputs to a DAC. 
End of Conversion (EOC) is a digital signal from an ADC 
which informs the external system that the digital output 



data is valid. Typically, an EOC output can be connected to 
an SC input to cause the ADC to operate in continuous 
conversion mode. In non-continuous conversion systems, 
the SC signal is a command from the system to the ADC. A 
DAC does not supply an EOC signal. 
Clock signals are required or must be generated within an 
ADC to control counting or successive approximation regis- 
ters. The clock controls the conversion speed within the 
limitations of the ADC. DACs do not require clock signals. 

CONCLUSION 

Once the user has a working knowledge of DAC or ADC 
characteristics and specifications, he should be able to se- 
lect a converter to suit a specific system need. The likeli- 
hood of overspecification, and therefore an unnecessarily 
hjph cost, is likewise reduced. The user will also be aware 
that specific parameters, test conditions, test circuits, and 
even definitions may vary from manufacturer to manufactur- 
er. For practical production reasons, parameters may not be 
tested in the same manner for all converter types, even 
those supplied by the same manufacturer. Using information 
in this note, the user should, however, be able to sort out 
and understand those specifications (from any manufactur- 
er) pertinent to his needs. 



338 



IC Voltage Reference has 
1 ppm per Degree Drift 



National Semiconductor 
Application Note 161 




A new linear IC now provides the ultimate in highly stable 
voltage references. Now, a new monolithic IC the LM199, 
out-performs zeners and can provide a 6.9V reference with 
a temperature drift of less than 1 ppm/ and excellent long 
term stability. This new IC, uses a unique subsurface zener 
to achieve low noise and a highly stable breakdown. Includ- 
ed is an on-chip temperature stabilizer which holds the chip 
temperature at 90°C, eliminating the effects of ambient tem- 
perature changes on reference voltage. 
The planar monolithic IC offers superior performance com- 
pared to conventional reference diodes. For example, active 
circuitry buffers the reverse current to the zener giving a 
dynamic impedance of 0.5H and allows the LM199 to oper- 
ate over a 0.5 mA to 1 mA current range with no change in 
performance. The low dynamic impedance, coupled with 
low operating current significantly simplifies the current 
drive circuitry needed for operation. Since the temperature 
coefficient is independent of operating current, usually a re- 
sistor is all that is needed. 

Previously, the task of providing a stable, low temperature 
coefficient reference voltage was left to a discrete zener 
diode. However, these diodes often presented significant 
problems. For example, ordinary zeners can show many mil- 
livolts change if there is a temperature gradient across the 
package due to the zener and temperature compensation 
diode not being at the same temperature. A 1°C difference 
may cause a 2 mV shift in reference voltage. Because the 
on-chip temperature stabilizer maintains constant die tem- 
perature, the IC reference is free of voltage shifts due to 
temperature gradients. Further, the temperature stabilizer, 
as well as eliminating drift, allows exceptionally fast warm- 
up over conventional diodes. Also, the LM199 is insensitive 
to stress on the leads — another source of error with ordi- 
nary glass diodes. Finally, the LM199 shows virtually no hys- 
teresis in reference voltage when subject to temperature 
cycling over a wide temperature range. Temperature cycling 
the LM199 between 25°C, 150°C and back to 25°C causes 
less than 50 ju.V change in reference voltage. Standard ref- 
erence diodes exhibit shifts of 1 mV to 5 mV under the same 
conditions. 



SUB SURFACE ZENER IMPROVES STABILITY 

Previously, breakdown references made in monolithic IC's 
usually used the emitter-base junction of an NPN transistor 
as a zener diode. Unfortunately, this junction breaks down 
at the surface of the silicon and is therefore susceptible to 
surface effects. The breakdown is noisy, and cannot give 
long-term stabilities much better than about 0.3%. Further, 
a surface zener is especially sensitive to contamination in 
the oxide or charge on the surface of the oxide which can 
cause short-term instability or turn-on drift. 
The new zener moves the breakdown below the surface of 
the silicon into the bulk yielding a zener that is stable with 
time and exhibits very low noise. Because the new zener is 
made with well-controlled diffusions in a planar structure, it 
is extremely reproducible with an initial 2% tolerance on 
breakdown voltage. 

A cut-away view of the new zener is shown in Figure 1. First 
a small deep P+ diffusion is made into the surface of the 
silicon. This is then covered by the standard base diffusion. 
The N + emitter diffusion is then made completely covering 
the P+ diffusion. The diode then breaks down where the 
dopant concentration is greatest, that is, between the P + 
and N + . Since the P+ is completely covered by N+ the 
breakdown is below the surface and at about 6.3V. One 
connection to the diode is to the N+ and the other is to the 
P base diffusion. The current flows laterally through the 
base to the P+ or cathode of the zener. Surface breakdown 
does not occur since the base P to N + breakdown voltage 
is greater than the breakdown of the buried device. The 
buried zener has been in volume production since 1 973 as 
the reference in the LX5600 temperature transducer. 

CIRCUIT DESCRIPTION 

The block diagram of the LM199 is shown in Figure 2. Two 
electrically independent circuits are included on the same 
chip — a temperature stabilizer and a floating active zener. 
The only electrical connection between the two circuits 




BURIED LAYER 



FIGURE 1. Subsurface Zener Construction 



m n 
ri 71 



_i 



Q] DIODE Q] 



TL/H/5613-1 

FIGURE 2. Functional Block 
Diagram 



339 



is the isolation diode inherent in any junction-isolated inte- 
grated circuit. The zener may be used with or without the 
temperature stabilizer powered. The only operating restric- 
tion is that the isolation diode must never become forward 
biased and the zener must not be biased above the 40V 
breakdown of the isolation diode. 

The actual circuit is shown in Figure 3. The temperature 
stabilizer is composed of Q1 through Q9. FET Q9 provides 
current to zener D2 and Q8. Current through Q8 turns a loop 
consisting of D1, Q5, Q6, Q7, R1 and R2. About 5V is ap- 
plied to the top of R1 from the base of Q7. This causes 400 
ju,A to flow through the divider R1, R2. Transistor Q7 has a 
controlled gain of 0.3 giving Q7 a total emitter current of 
about 500 ju.A. This flows through the emitter of Q6 and 
drives another controlled gain PNP transistor Q5. The gain 
of Q5 is about 0.4 so D1 is driven with about 200 /uA. Once 
current flows through Q5, Q8 is reverse biased and the loop 
is self-sustaining. This circuitry ensures start-up. 
The resistor divider applies 400 mV to the base of Q4 while 
Q7 supplies 120 fxA to its collector. At temperatures below 
the stabilization point, 400 mV is insufficient to cause Q4 to 
conduct. Thus, all the collector current from Q7 is provided 



as base drive to a Darlington composed of Q1 and Q2. The 
Darlington is connected across the supply and initially draws 
140 mA (set by current limit transistor Q3). As the chip 
heats, the turn on voltage for Q4 decreases and Q4 starts to 
conduct. At about 90°C the current through Q4 appreciably 
increases and less drive is applied to Q1 and Q2. Power 
dissipation decreases to whatever is necessary to hold the 
chip at the stabilization temperature. In this manner, the 
chip temperature is regulated to better than 2°C for a 100°C 
temperature range. 

The zener section is relatively straight-forward. A buried ze- 
ner D3 breaks down biasing the base of transistor Q13. 
Transistor Q13 drives two buffers Q12 and 0.11. External 
current changes through the circuit are fully absorbed by the 
buffer transistors rather than D3. Current through D3 is held 
constant at 250 juA by a 2k resistor across the emitter base 
of Q1 3 while the emitter-base voltage of Q1 3 nominally tem- 
perature compensates the reference voltage. 
The other components, Q14, Q15 and Q16 set the operat- 
ing current of Q13. Frequency compensation is accom- 
plished with two junction capacitors. 




TL/H/5613-2 



FIGURE 3. Schematic Diagram of LM199 Precision Reference 



340 



PERFORMANCE 

A polysulfone thermal shield, shown in Figure 4, is supplied 
with the LM199 to minimize power dissipation and improve 
temperature regulation. Using a thermal shield as well as 
the small, high thermal resistance TO-46 package allows 
operation at low power levels without the problems of spe- 
cial IC packages with built-in thermal isolation. Since the 
LM199 is made on a standard IC assembly line with stan- 
dard assembly techniques, cost is significantly lower than if 
special techniques were used. For temperature stabilization 
only 300 mW are required at 25°C and 660 mW at -55°C. 




TL/H/5613-3 

FIGURE 4. Polysulfone Thermal Shield 

Temperature stabilizing the device at 90°C virtually elimi- 
nates temperature drift at ambient temperatures less than 
90°C. The reference is nominally temperature compensated 
and the thermal regulator further decreases the temperature 
drift. Drift is typically only 0.3 ppm/ C. Stabilizing the tem- 
perature at 90°C rather than 125°C significantly reduces 
power dissipation but still provides very low drift over a ma- 
jor portion of the operating temperature range. Above 90°C 
ambient, the temperature coefficient is only 15 ppm/°C. 
A low drift reference would be virtually useless without 
equivalent performance in long term stability and low noise. 
The subsurface breakdown technology yields both of these. 
Wideband and low frequency noise are both exceptionally 
low. Wideband noise is shown in Figure 5 and low frequency 
noise is shown over a 1 minute period in the photograph of 
Figure 6. Peak to peak noise over a 0.01 Hz to 1 Hz band- 
width is only about 0.7 jaV. 

Long term stability is perhaps one of the most difficult mea- 
surements to make. However, conditions for long-term sta- 
bility measurements on the LM199 are considerably more 
realistic than for commercially available certified zeners. 
Standard zeners are measured in ±0.05°C temperature 
controlled both at an operating current of 7.5 mA ±0.05 \ik. 
Further, the standard devices must have stress-free con- 
tacts on the leads and the test must not be interrupted dur- 
ing the measurement interval. In contrast, the LM199 is 
measured in still air of 25°C to 28°C at a reverse current of 
1 mA ±0.5%. This is more typical of actual operating condi- 
tions in instruments. 

When a group of 1 devices were monitored for long-term 
stability, the variations all correlated, which indicates chang- 
es in the measurement system (limitation of 20 ppm) rather 
than the LM199. 











\ 








\ 








0^ 


STABILIZED (Tj - 


90 CI 


v. 


I — 

Tj - 25'C 













50 

10 100 Ik 10k 100k 

FREQUENCY (Hj) 

FIGURE 5. Wideband Noise of the LM199 Reference 




0.01 Hl<K1Hl 
STABILIZED 

(T, - 90'C) 



TIME (MINUTES) 

TL/H/5613-4 

FIGURE 6. Low Frequency Noise Voltage 

Because the planar structure does not exhibit hysteresis 
with temperature cycling, long-term stability is not impaired 
if the device is switched on and off. 
The temperature stabilizer heats the small thermal mass of 
the LM199 to 90°C very quickly. Warm-up time at 25°C and 
-55"C is shown in Figure 7. This fast warm-up is significant- 
ly less than the several minutes needed by ordinary diodes 
to reach equilibrium. Typical specifications are shown in Ta- 
ble I. 



I 

T A -2SC 


i.,..~, 




/ 


r 


V \ 

T A --5 


IC 














I 










1 
1 
I 






VH" 


1SV 



4 8 12 16 20 

HEATER ON TIME -(SEC) 

TL/H/5613-5 

FIGURE 7. Fast Warmup Time of the LM199 

Table I. Typical Specifications for the LM199 

Reverse Breakdown Voltage 6.95V 

Operating Current 0.5 mA to 1 mA 



Temperature Coefficient 


0.3 ppm/°C 


Dynamic Impedance 


0.5H 


RMS Noise (10 Hz to 10 kHz) 


7juV 


Long-Term Stability 


< 20 ppm 


Temperature Stabilizer Operating Voltage 


9V to 40V 


Temperature Stabilizer Power Dissipation 




(25°C) 


300 mW 


Warm-up Time 


3 Seconds 



341 



APPLICATIONS 

The LM199 is easier to use than standard zeners, but the 
temperature stability is so good — even better than precision 
resistors— that care must be taken to prevent external cir- 
cuitry from limiting performance. Basic operation only re- 
quires energizing the temperature stabilizer from a 9V to 
40V power source and biasing the reference with between 
0.5 mA to 10 mA of current. The low dynamic impedance 
minimizes the current regulation required compared to ordi- 
nary zeners. 

The only restriction on biasing the zener is the bias applied 
to the isolation diode. Firstly, the isolation diode must not be 
forward biased. This restricts the voltage at either terminal 
of the zener to a voltage equal to or greater than the V - . 
A dc return is needed between the zener and heater to in- 
sure the voltage limitation on the isolation diodes are not 
exceeded. Figure 8 shows the basic biasing of the LM199. 
The active circuitry in the reference section of the LM199 
reduces the dynamic impedance of the zener to about 0.5(1. 
This is especially useful in biasing the reference. For exam- 
ple, a standard reference diode such as a 1 N829 operates 
at 7.5 mA and has a dynamic impedance of 15(1. A 1% 
change in current (75 liA) changes the reference voltage by 
1.1 mV. Operating the LM199 at 1 mA with the same 1% 
change in operating current (10 juA) results in a reference 
change of only 5 juV. Figure 9 shows reverse voltage 
change with current. 

Biasing current for the reference can by anywhere from 0.5 
mA to 10 mA with little change in performance. This wide 
current range allows direct replacement of most zener types 
with no other circuit changes besides the temperature stabi- 
lizer connection. Since the dynamic impedance is constant 
with current changes regulation is better than discrete ze- 
ners. For optimum regulation, lower operating currents are 



























STABILIZED 








' Y/T 











































REVERSE CURRENT ImA] 

TL/H/5613-6 

FIGURE 9. The LM199 Shows Excellent Regulation 
Against Current Changes 

preferred since the ratio of source resistance to zener im- 
pedance is higher, and the attenuation of input changes is 
greater. Further, at low currents, the voltage drop in the 
wiring is minimized. 

Mounting is an important consideration for optimum per- 
formance. Although the thermal shield minimizes the heat 
low, the LM199 should not be exposed to a direct air flow 
such as from a cooling fan. This can cause as much as a 
100% increase in power dissipation degrading the thermal 
regulation and increasing the drift. Normal conviction cur- 
rents do not degrade performance. 
Printed circuit board layout is also important. Firstly, four 
wire sensing should be used to eliminate ohmic drops in pc 
traces. Although the voltage drops are small the tempera- 
ture coefficient of the voltage developed along a copper 
trace can add significantly to the drift. For example, a trace 
with 1 (1 resistance and 2 mA current flow will develop 2 mV 
drop. The TC of copper is 0.004 %/°C so the 2 mV drop will 
change at 8 jaV/°C, this is an additional 1 ppm drift error. Of 
course, the effects of voltage drops in the printed circuit 
traces are eliminated with 4-wire operation. The heater cur- 
rent also should not be allowed to flow through the voltage 
reference traces. Over a -55°C to +125°C temperature 



■i- 




I 












\ 


t temperature 
-•stabilizer 

J 6.95V A 

} 


i 




9VT0 


_ 






-33V 







<Rs 




TL/H/5613-7 



FIGURE 8. Basic Biasing of the LM199 



342 



range the heater current will change from about 1 mA to 
over 40 mA. These magnitudes of current flowing reference 
leads or reference ground can cause huge errors compared 
to the drift of the LM1 99. 

Thermocouple effects can also use errors. The kovar leads 
from the LM199 package from a thermocouple with copper 
printed circuit board traces. Since the package of the 1 99 is 
heated, there is a heat flow along the leads of the LM199 
package. If the leads terminate into unequal sizes of copper 
on the p.c. board greater heat will be absorbed by the larger 
copper trace and a temperature difference will develop. A 
temperature difference of 1°C between the two leads of the 
reference will generate about 30 jjA Therefore, the copper 
traces to the zener should be equal in size. This will general- 
ly keep the errors due to thermocouple effects under about 
15 n V. 

The LM199 should be mounted flush on the p.c. board with 
a minimum of space between the thermal shield and the 
boards. This minimizes air flow across the kovar leads on 
the board surface which also can cause thermocouple volt- 
ages. Air currents across the leads usually appear as ultra- 
low frequency noise of about 1 juV to 20 /j,V amplitude. 
It is usually necessary to scale and buffer the output of any 
reference to some calibrated voltage. Figure 10 shows a 
simple buffered reference with a 10V output. The reference 
is applied to the non-inverting input of the LM108A. An RC 
rolloff can be inserted in series with the input to the LM108A 
to roll-off the high frequency noise. The zener heater and op 
amp are all powered from a single 1 5V supply. About 1 % 



regulation on the input supply is adequate contributing less 
than 10 /xV of error to the output. Feedback resistors 
around the LM308 scale the output to 10V. 
Although the absolute values of the resistors are not ex- 
tremely important, tracking of temperature coefficients is vi- 
tal. The 1 ppm/"C drift of the LM199 is easily exceeded by 
the temperature coefficient of most resistors. Tracking to 
better than 1 ppm is also not easy to obtain. Wirewound 
types made of Evenohm or Mangamin are good and also 
have low thermoelectric effects. Film types such as Vishay 
resistors are also good. Most potentiometers do not track 
fixed resistors so it is a good idea to minimize the adjust- 
ment range and therefore minimize their effects on the out- 
put TC. Overall temperature coefficient of the circuit shown 
in Figure 10 is worst case 3 ppm/°C. About 1 ppm is due to 
the reference, 1 ppm due to the resistors and 1 ppm due to 
the op amp. 

Figure 11 shows a standard cell replacement with a 1.01V 
output. A LM321 and LM308 are used to minimize op amp 
drift to less than 1 ^.V/°C. Note the adjustment connection 
which minimizes the TC effects of the pot. Set-up for this 
circuit requires nulling the offset of the op amp first and then 
adjusting for proper output voltage. 
The drift of the LM321 is very predictable and can be used 
to eliminate overall drift of the system. The drift changes at 
3.6 \i\l/°C per millivolt of offset so 1 mV to 2 mV of offset 
can be introduced to minimize the overall TC. 




FIGURE 10. Buffered 10V Reference 




FIGURE 11. Standard Cell Replacement 



343 



For circuits with a wide input voltage range, the reference 
can be powered from the output of the buffer as is shown in 
Figure 12. The op amp supplies regulated voltage to the 
resistor biasing the reference minimizing changes due to 
input variation. There is some change due to variation of the 
temperature stabilizer voltage so extremely wide range op- 
eration is not recommended for highest precision. An addi- 
tional resistor (shown 80 kft) is added to the unregulated 
input to insure the circuit starts up properly at the applica- 
tion of power. 

A precision power supply is shown in Figure 13. The output 
of the op amp is buffered by an IC power transistor the 
LM395. The LM395 operates as an NPN power device but 
requires only 5 /xA base current. Full overload protection 
inherent in the LM395 includes current limit, safe-area pro- 
tection, and thermal limit. 

A reference which can supply either a positive or a negative 
continuously variable output is shown in Figure 14. The ref- 
erence is biased from the ±15 input supplies as was shown 



earlier. A ten-turn pot will adjust the output from +Vz to 
- Vz continuously. For negative output the op amp operates 
as an inverter while for positive outputs it operates as a non- 
inverting connection. 

Op amp choice is important for this circuit. A low drift device 
such as the LM108A or a LM108-LM121 combination will 
provide excellent performance. The pot should be a preci- 
sion wire wound 10 turn type. It should be noted that the 
output of this circuit is not linear. 

CONCLUSIONS 

A new monolithic reference which exceeds the performance 
of conventional zeners has been developed. In fact, the 
LM199 performance is limited more by external components 
than by reference drift itself. Further, many of the problems 
associated with conventional zeners such as hysteresis, 
stress sensitivity and temperature gradient sensitivity have 
also been eliminated. Finally, long-term stability and noise 
are equal of the drift performance of the new device. 




FIGURE 12. Wide Range Input Voltage Reference 



r 



6.85V . 
LM199 




FIGURE 13. Precision Power Supply 

50k 

-*vw- 




TL/H/5613-9 



FIGURE 14. Bipolar Output Reference 



344 



LM2907 Tachometer/Speed 
Switch Building Block 
Applications 



INTRODUCTION 

Frequency to voltage converters are available in a number 
of forms from a number of sources, but invariably require 
significant additional components before they can be put to 
use in a given situation. The LM2907, LM2917 series of 
devices was developed to overcome these objections. Both 
input and output interface circuitry is included on chip so 
that a minimum number of additional components is re- 
quired to complete the function. In keeping with the systems 
building block concept, these devices provide an output 
voltage which is proportional to input frequency and provide 
zero output at zero frequency. In addition, the input may be 
referred to ground. The devices are designed to operate 



LM2907N-8 



National Semiconductor 
Application Note 162 




from a single supply voltage, which makes them particularly 
suitable for battery operation. 

PART 1— GENERAL OPERATION PRINCIPLES 

Circuit Description 

Referring to Figure 1, the family of devices all include three 
basic components: an input amplifier with built-in hysteresis; 
a charge pump frequency to voltage converter; and a versa- 
tile op amp/comparator with an uncommitted output transis- 
tor. LM2917 incorporates an active zener regulator on-chip. 
LM2907 deletes this option. Both versions are obtainable in 
14-pin and in 8-pin dual-in-line molded packages, and to 
special order in other packages. 



LM2917N-8 




TL/H/7451-1 



TL/H/7451 -2 



LM2907N 

NC NC ^ + 

14 Il3 Il2 11 10 9 



± 




CHARGE PUMP 



LM2917N 

NC NC 

1 14 In |12 |H |10 



^KJ 



± 




4 5 16 7 



- 1 



NC NC 

TL/H/7451 -3 

FIGURE 1. Block Diagrams 



345 



FT 

NC NC 

TL/H/7451 -4 



CM 



Input Hysteresis Amplifier 

The equivalent schematic diagram is shown in Figure 2. Q1 
through Q11 comprise the input hysteresis amplifier. Q1 
through Q4 comprise an input differential amplifier which, by 
virtue of PNP level shifting, enables the circuit to operate 
with signals referenced to ground. Q7, Q8, D4, and D5 com- 
prise an active load with positive feedback. This load be- 
haves as a bi-stable flip-flop which may be set or reset de- 
pending upon the currents supplied from Q2 and Q3. Con- 
sider the situation where Q2 and Q3 are conducting equally, 
i.e. the input differential voltage is zero. Assuming Q7 to be 
conducting, it will be noted that the current from Q3 will be 
drawn by Q7 and Q8 will be in the "OFF" state. This allows 
the current from Q2 to drive Q7 in parallel with D4 and a 
small resistor. D4 and Q7 are identical geometry devices, so 
that the resistor causes Q7 to be biased at a higher level 
than D4. Thus Q7 will be able to conduct more current than 
Q3 provides. In order to reverse the state of Q7 and Q8, it 
will be necessary to reduce the current from Q2 below that 
provided by Q3 by an amount which is established by R1. It 
can be shown that this requires a differential input to Q1 and 
Q4, of approximately 15mV. Since the circuit is symmetrical, 
the threshold voltage to reverse the state is 1 5 mV in the 
other direction. Thus the input amplifier has built-in hystere- 
sis at + 1 5 mV. This provides clean switching where noise 
may be present on the input signal, and allows total rejec- 
tion of noise below this amplitude where there is no input 
signal. 

Charge Pump 

The charge pump is composed of Q1 2 through Q32. R4, R5, 
and R6 provide reference voltages equal to 1 /4 and 3/4 of 
supply voltage to Q12 and Q13. When Q10 turns "ON" or 
"OFF," the base voltage at Q16 changes by an amount 
equal to the voltage across R5, that is 1 12 V cc . A capacitor 
connected between Pin 2 and ground is either charged by 
Q21 or discharged by Q22 until its voltage matches that on 
the base of Q16. When the voltage on Q16 base goes low, 
Q16 turns "ON," which results in Q18 and Q26 turning on, 
which causes the current, sourced by Q19 and Q20, to be 
shunted to ground. Thus Q21 is unable to charge pin 2. 
Meanwhile, Q27 and Q30 are turned off permitting the 
200 juA sourced by Q28 and Q29 to enter the emitters of 
Q31 and Q32 respectively. The current from Q31 is mirrored 
by Q22 through Q24 resulting in a 200 juA discharge current 
through pin 2. The external capacitor on pin 2 is thus dis- 
charged at a constant rate until it reaches the new base 
voltage on Q1 6. The time taken for this discharge to occur is 
given by: 

x CV 

t = - (D 

where C = capacitor on pin 2 

V = change in voltage on Q1 6 base 
I = current in Q22 
During this time, Q32 sources an identical current into pin 3. 
A capacitor connected to pin 3 will thus be charged by the 
same current for the same amount of time as pin 2. When 
the base voltage on Q16 goes high, Q18 and Q26 are 
turned off while Q27 and Q30 are turned "ON." In these 
conditions, Q21 and Q25 provide the currents to charge the 
capacitors on pins 2 and 3 respectively. Thus the charge 



and 



V3 = V CC - 



required to return the capacitor on pin 2 to the high level 
voltage is duplicated and used to charge the capacitor con- 
nected to pin 3. Thus in one cycle of input the capacitor on 
pin 3 gets charged twice with a charge of CV. 
Thus the total charge pumped into the capacitor on pin 3 
per cycle is: 

Q = 2 CV (2) 

Now, since V = Vcc/2 

then Q = CV C c (3) 

A resistor connected between pin 3 and ground causes a 
discharge of the capacitor on pin 3, where the total charge 
drained per cycle of input signal is equal to: 

Q1= — 
where V3 = the average voltage on pin 3 

T = period of input signal 

R = resistor connected to pin 3 

In equilibrium Q = Q1 

V3«T 
i-e., CV CC = -p- (4) 

RC 
'— (5) 

or V3 = V C c • R • C • f (6) 

where f = input frequency 

Op Amp/Comparator 

Again referring to Figure 2, the op amp/comparator includes 
Q35 through Q45. A PNP input stage again provides input 
common-mode voltages down to zero, and if pin 8 is con- 
nected to Vcc and the output taken from pin 5, the circuit 
behaves as a conventional, unity-gain-compensated opera- 
tional amplifier. However, by allowing alternate connections 
of Q45 the circuit may be used as a comparator in which 
loads to either Vcc or ground may be switched. Q45 is ca- 
pable of sinking 50 mA. Input bias current is typically 50 nA, 
and voltage gain is typically 200 V/mV. Unity gain slew rate 
is 0.2 V/jus. When operated as a comparator Q45 emitter 
will switch at the slew rate, or the collector of Q45 will 
switch at that rate multiplied by the voltage gain of Q45, 
which is user selectable. 

Active Zener Regulator 

The optional active zener regulator is also shown in Figure 
2. D8 provides the voltage reference in conjunction with 
Q33. As the supply voltage rises, D8 conducts and the base 
voltage on Q33 starts to rise. When Q33 has sufficient base 
voltage to be turned "ON," it in turn causes Q34 to conduct 
current from the power source. This reduces the current 
available for D8 and the negative feedback loop is thereby 
completed. The reference voltage is therefore the zener 
voltage on D8 plus the emitter base voltage of Q33. This 
results in a low temperature coefficient voltage. 

Input Levels and Protection 

In 8-pin versions of the LM2907, LM2917, the non-inverting 
input of the op amp/comparator is connected to the output 
of the charge pump. Also, one input to the input hysteresis 
amplifier is connected to ground. The other input (pin 1) is 
then protected from transients by, first a 1 0kfl series resis- 



346 




347 



tor, R3 (Figure 2) which is located in a floating isolation 
pocket, and secondly by clamp diode D1 . Since the voltage 
swing on the base of Q1 is thus restricted, the only restric- 
tion on the allowable voltage on pin 1 is the breakdown 
voltage of the 10 kft resistor. This allows input swings to 
+ 28V. In 1 4-pin versions the link to D1 is opened in order to 
allow the base of Q1 to be biased at some higher voltage. 
Q5 clamps the negative swing on the base of Q1 to about 
300 mV. This prevents substrate injection in the region of 
Q1 which might otherwise cause false switching or errone- 
ous discharge of one of the timing capacitors. 
The differential input options (LM2907-14, LM2917-14), give 
the user the option of setting his own input switching level 
and still having the hysteresis around that level for excellent 
noise rejection in any application. 

HOW TO USE IT 

Basic f to V Converter 

The operation of the LM2907, LM291 7 series is best under- 
stood by observing the basic converter shown in Figure 3. In 
this configuration, a frequency signal is applied to the input 
of the charge pump at pin 1 . The voltage appearing at pin 2 
will swing between two values which are approximately 1/4 
(Vcc) - V BE and 3/4 (V C c) - V B e- The voltage at pin 3 will 
have a value equal to Vcc • 'in • C1 • R1 • K, where K is 
the gain constant (normally 1 .0). 

The emitter output (pin 4) is connected to the inverting input 
of the op amp so that pin 4 will follow pin 3 and provide a 
low impedance output voltage proportional to input frequen- 
cy. The linearity of this voltage is typically better than 0.3% 
of full scale. 

Choosing R1, C1 and C2 

There are some limitations on the choice of R1, C1 and C2 
(Figure 3) which should be considered for optimum perform- 
ance. C1 also provides internal compensation for the 
charge pump and should be kept larger than 100 pF. Small- 
er values can cause an error current on R1, especially at 
low temperatures. Three considerations must be met when 
choosing R1. 

First, the output current at pin 3 is internally fixed and there- 
fore V3 max, divided by R1, must be less than or equal to 
this value. 

V3max 



R1 s 



Second, if R1 is too large, it can become a significant frac- 
tion of the output impedance at pin 3 which degrades linear- 
ity. Finally, ripple voltage must be considered, and the size 
of C2 is affected by R1. An expression that describes the 
ripple content on pin 3 for a single R1, C2 combination is: 

» V CC C1/ Vcc * f|N * C1 \ 
Vripple = — • - ( 1 J P -p 

It appears R1 can be chosen independent of ripple, howev- 
er response time, or the time it takes Vqut to stabilize at a 
new frequency increases as the size of C2 increases, so a 
compromise between ripple, response time, and linearity 
must be cosen carefully. R1 should be selected according 
to the following relationship: 
C is selected according to: 

_ . _ V3 Full Scale 

R1 • Vcc • f FULL SCALE 

Next decide on the maximum ripple which can be accepted 
and plug into the following equation to determine C2: 
VCC T C1 (^ _y 3 



C2 



Vcc, C1 / V 3 \ 

2 V R |pp LE \ Rfa) 



Vripple V ' R-|l2 
The kind of capacitor used for timing capacitor C1 will deter- 
mine the accuracy of the unit over the temperature range. 
Figure 15 illustrates the tachometer output as a function of 
temperature for the two devices. Note that the LM2907 op- 
erating from a fixed external supply has a negative tempera- 
ture coefficient which enables the device to be used with 
capacitors which have a positive temperature coefficient 
and thus obtain overall stabililty. In the case of the LM2917 
the internal zener supply voltage has a positive coefficient 
which causes the overall tachometer output to have a very 
low temperature coefficient and requires that the capacitor 
temperature coefficient be balanced by the temperature co- 
efficient of R1. 

Using Zener Regulated Options (LM2917) 

For those applications where an output voltage or current 
must be obtained independently of the supply voltage varia- 
tions, the LM2917 is offered. The reference typically has an 
1 1 H source resistance. In choosing a dropping resistor from 
the unregulated supply to the device note that the tachome- 
ter and op amp circuitry alone require about 3 mA at the 
voltage level provided by the zener. At low supply voltages, 



I3MIN 



where V3 max is the full scale output voltage required 
1 3MIN is determined from the data sheet (150 \ik) 



X 



zs~ ■ 



vcc 
Q 




►VOUT 



FIGURE 3. Basic f to V Converter 



TL/H/7451-6 



348 



there must be some current flowing in the resistor above the 
3 mA circuit current to operate the regulator. As an exam- 
ple, if the raw supply varies from 9V to 16V, a resistance of 
470fl will minimize these zener voltage variations to 160 
mV. If the resistor goes under 400fl or over 600ft the zener 
variation quickly rises above 200 mV for the same input vari- 
ation. Take care also that the power dissipation of the IC is 
not exceeded at higher supply voltages. Figure 4 shows 
suitable dropping resistor values. 




100 500 Ik 1.5k 2k 2.5k 
POWER SUPPLY DROPPING RESISTOR - (OHMS) 

TL/H/7451-7 

FIGURE 4. Zener Regular Bias Resistor Range 



Input Interface Circuits 

The ground referenced input capability of the LM2907-8 al- 
lows direct coupling to transformer inputs, or variable reluc- 
tance pickups. Figure 5(a) illustrates this connection. In 
many cases, the frequency signal must be obtained from 
another circuit whose output may not go below ground. This 
may be remedied by using ac coupling to the input of the 
LM2907 as illustrated in Figure 5(b). This approach is very 
suitable for use with phototransistors for optical pickups. 
Noisy signal sources may be coupled as shown in Figure 
5(c). The signal is bandpass filtered. This can be used, for 
example, for tachometers operating from breakerpoints on a 
conventional Kettering ignition system. Remember that the 
minimum input signal required by the LM2907 is only 30 
m Vp-p, but this signal must be able to swing at least 1 5 mV 
on either side of the inverting input. The maximum signal 
which can be applied to the LM2907 input, is ±28V. The 
input bias current is a typically 100 nA. A path to ground 
must be provided for this current through the source or by 
other means as illustrated. With 14-pin package versions of 
LM2907, LM2917, it is possible to bias the inverting input to 
the tachometer as illustrated in Figure 5(d). This enables the 
circuit to operate with input signals that do not go to ground, 
but are referenced at higher voltages. Alternatively, this 
method increases the noise immunity where large signal 




-T3 




X 



7> 



f INO-^^^- 



i 



if 



> 



*1 



TL/H/7451-8 

(a) Ground Referenced Inputs 



TL/H/7451-9 

(b) AC Coupled Input 



TL/H/7451-10 

(c) Bandpass Filtered Input 
Reduces Noise 




_rn 



> 



i 



TL/H/7451-11 



(d) Above Ground Sensing 



TL/H